libpcsxcore/psxcounters.c

   1 /***************************************************************************
   2  *   Copyright (C) 2010 by Blade_Arma                                      *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
  18  ***************************************************************************/
  19
  20 /*
  21  * Internal PSX counters.
  22  */
  23
  24 #include "psxcounters.h"
  25 #include "debug.h"
  26
  27 /******************************************************************************/
  28
  29 typedef struct Rcnt
  30 {
  31     u16 mode, target;
  32     u32 rate, irq, counterState, irqState;
  33     u32 cycle, cycleStart;
  34 } Rcnt;
  35
  36 enum
  37 {
  38     Rc0Gate           = 0x0001, // 0    not implemented
  39     Rc1Gate           = 0x0001, // 0    not implemented
  40     Rc2Disable        = 0x0001, // 0    partially implemented
  41     RcUnknown1        = 0x0002, // 1    ?
  42     RcUnknown2        = 0x0004, // 2    ?
  43     RcCountToTarget   = 0x0008, // 3
  44     RcIrqOnTarget     = 0x0010, // 4
  45     RcIrqOnOverflow   = 0x0020, // 5
  46     RcIrqRegenerate   = 0x0040, // 6
  47     RcUnknown7        = 0x0080, // 7    ?
  48     Rc0PixelClock     = 0x0100, // 8    fake implementation
  49     Rc1HSyncClock     = 0x0100, // 8
  50     Rc2Unknown8       = 0x0100, // 8    ?
  51     Rc0Unknown9       = 0x0200, // 9    ?
  52     Rc1Unknown9       = 0x0200, // 9    ?
  53     Rc2OneEighthClock = 0x0200, // 9
  54     RcUnknown10       = 0x0400, // 10   ?
  55     RcCountEqTarget   = 0x0800, // 11
  56     RcOverflow        = 0x1000, // 12
  57     RcUnknown13       = 0x2000, // 13   ? (always zero)
  58     RcUnknown14       = 0x4000, // 14   ? (always zero)
  59     RcUnknown15       = 0x8000, // 15   ? (always zero)
  60 };
  61
  62 #define CounterQuantity           ( 4 )
  63 //static const u32 CounterQuantity  = 4;
  64
  65 static const u32 CountToOverflow  = 0;
  66 static const u32 CountToTarget    = 1;
  67
  68 static const u32 FrameRate[]      = { 60, 50 };
  69 static const u32 VBlankStart[]    = { 240, 256 };
  70 static const u32 HSyncTotal[]     = { 263, 313 };
  71 static const u32 SpuUpdInterval[] = { 32, 32 };
  72
  73 static const s32 VerboseLevel     = 0;
  74
  75 /******************************************************************************/
  76
  77 static Rcnt rcnts[ CounterQuantity ];
  78
  79 static u32 hSyncCount = 0;
  80 static u32 spuSyncCount = 0;
  81 static u32 hsync_steps = 0;
  82 static u32 gpu_wants_hcnt = 0;
  83
  84 u32 psxNextCounter = 0, psxNextsCounter = 0;
  85
  86 /******************************************************************************/
  87
  88 static inline
  89 void setIrq( u32 irq )
  90 {
  91     psxHu32ref(0x1070) |= SWAPu32(irq);
  92 }
  93
  94 static
  95 void verboseLog( s32 level, const char *str, ... )
  96 {
  97     if( level <= VerboseLevel )
  98     {
  99         va_list va;
 100         char buf[ 4096 ];
 101
 102         va_start( va, str );
 103         vsprintf( buf, str, va );
 104         va_end( va );
 105
 106         printf( "%s", buf );
 107         fflush( stdout );
 108     }
 109 }
 110
 111 /******************************************************************************/
 112
 113 static inline
 114 void _psxRcntWcount( u32 index, u32 value )
 115 {
 116     if( value > 0xffff )
 117     {
 118         verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
 119         value &= 0xffff;
 120     }
 121
 122     rcnts[index].cycleStart  = psxRegs.cycle;
 123     rcnts[index].cycleStart -= value * rcnts[index].rate;
 124
 125     // TODO: <=.
 126     if( value < rcnts[index].target )
 127     {
 128         rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
 129         rcnts[index].counterState = CountToTarget;
 130     }
 131     else
 132     {
 133         rcnts[index].cycle = 0xffff * rcnts[index].rate;
 134         rcnts[index].counterState = CountToOverflow;
 135     }
 136 }
 137
 138 static inline
 139 u32 _psxRcntRcount( u32 index )
 140 {
 141     u32 count;
 142
 143     count  = psxRegs.cycle;
 144     count -= rcnts[index].cycleStart;
 145     if (rcnts[index].rate > 1)
 146         count /= rcnts[index].rate;
 147
 148     if( count > 0xffff )
 149     {
 150         verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
 151         count &= 0xffff;
 152     }
 153
 154     return count;
 155 }
 156
 157 /******************************************************************************/
 158
 159 static
 160 void psxRcntSet()
 161 {
 162     s32 countToUpdate;
 163     u32 i;
 164
 165     psxNextsCounter = psxRegs.cycle;
 166     psxNextCounter  = 0x7fffffff;
 167
 168     for( i = 0; i < CounterQuantity; ++i )
 169     {
 170         countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
 171
 172         if( countToUpdate < 0 )
 173         {
 174             psxNextCounter = 0;
 175             break;
 176         }
 177
 178         if( countToUpdate < (s32)psxNextCounter )
 179         {
 180             psxNextCounter = countToUpdate;
 181         }
 182     }
 183 }
 184
 185 /******************************************************************************/
 186
 187 static
 188 void psxRcntReset( u32 index )
 189 {
 190     u32 count;
 191
 192     if( rcnts[index].counterState == CountToTarget )
 193     {
 194         if( rcnts[index].mode & RcCountToTarget )
 195         {
 196             count  = psxRegs.cycle;
 197             count -= rcnts[index].cycleStart;
 198             if (rcnts[index].rate > 1)
 199                 count /= rcnts[index].rate;
 200             count -= rcnts[index].target;
 201         }
 202         else
 203         {
 204             count = _psxRcntRcount( index );
 205         }
 206
 207         _psxRcntWcount( index, count );
 208
 209         if( rcnts[index].mode & RcIrqOnTarget )
 210         {
 211             if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
 212             {
 213                 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
 214                 setIrq( rcnts[index].irq );
 215                 rcnts[index].irqState = 1;
 216             }
 217         }
 218
 219         rcnts[index].mode |= RcCountEqTarget;
 220     }
 221     else if( rcnts[index].counterState == CountToOverflow )
 222     {
 223         count  = psxRegs.cycle;
 224         count -= rcnts[index].cycleStart;
 225         if (rcnts[index].rate > 1)
 226             count /= rcnts[index].rate;
 227         count -= 0xffff;
 228
 229         _psxRcntWcount( index, count );
 230
 231         if( rcnts[index].mode & RcIrqOnOverflow )
 232         {
 233             if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
 234             {
 235                 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
 236                 setIrq( rcnts[index].irq );
 237                 rcnts[index].irqState = 1;
 238             }
 239         }
 240
 241         rcnts[index].mode |= RcOverflow;
 242     }
 243
 244     rcnts[index].mode |= RcUnknown10;
 245
 246     psxRcntSet();
 247 }
 248
 249 void psxRcntUpdate()
 250 {
 251     u32 cycle;
 252
 253     cycle = psxRegs.cycle;
 254
 255     // rcnt 0.
 256     if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
 257     {
 258         psxRcntReset( 0 );
 259     }
 260
 261     // rcnt 1.
 262     if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
 263     {
 264         psxRcntReset( 1 );
 265     }
 266
 267     // rcnt 2.
 268     if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
 269     {
 270         psxRcntReset( 2 );
 271     }
 272
 273     // rcnt base.
 274     if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
 275     {
 276         u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
 277         u32 next_vsync, next_lace;
 278
 279         spuSyncCount += hsync_steps;
 280         hSyncCount += hsync_steps;
 281
 282         // Update spu.
 283         if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
 284         {
 285             spuSyncCount = 0;
 286
 287             if( SPU_async )
 288             {
 289                 SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
 290             }
 291         }
 292
 293         // VSync irq.
 294         if( hSyncCount == VBlankStart[Config.PsxType] )
 295         {
 296             GPU_vBlank( 1, &hSyncCount, &gpu_wants_hcnt );
 297
 298             // For the best times. :D
 299             //setIrq( 0x01 );
 300         }
 301
 302         // Update lace. (with InuYasha fix)
 303         if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
 304         {
 305             hSyncCount = 0;
 306
 307             GPU_vBlank( 0, &hSyncCount, &gpu_wants_hcnt );
 308             setIrq( 0x01 );
 309
 310             EmuUpdate();
 311             GPU_updateLace();
 312         }
 313
 314         // Schedule next call, in hsyncs
 315         hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
 316         next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow
 317         next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
 318         if( next_vsync && next_vsync < hsync_steps )
 319             hsync_steps = next_vsync;
 320         if( next_lace && next_lace < hsync_steps )
 321             hsync_steps = next_lace;
 322         if( gpu_wants_hcnt )
 323             hsync_steps = 1;
 324
 325         rcnts[3].cycleStart = cycle - leftover_cycles;
 326         rcnts[3].cycle = hsync_steps * rcnts[3].target;
 327         psxRcntSet();
 328     }
 329
 330 #ifndef NDEBUG
 331     DebugVSync();
 332 #endif
 333 }
 334
 335 /******************************************************************************/
 336
 337 void psxRcntWcount( u32 index, u32 value )
 338 {
 339     verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
 340
 341     psxRcntUpdate();
 342
 343     _psxRcntWcount( index, value );
 344     psxRcntSet();
 345 }
 346
 347 void psxRcntWmode( u32 index, u32 value )
 348 {
 349     verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
 350
 351     psxRcntUpdate();
 352
 353     rcnts[index].mode = value;
 354     rcnts[index].irqState = 0;
 355
 356     switch( index )
 357     {
 358         case 0:
 359             if( value & Rc0PixelClock )
 360             {
 361                 rcnts[index].rate = 5;
 362             }
 363             else
 364             {
 365                 rcnts[index].rate = 1;
 366             }
 367         break;
 368         case 1:
 369             if( value & Rc1HSyncClock )
 370             {
 371                 rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
 372             }
 373             else
 374             {
 375                 rcnts[index].rate = 1;
 376             }
 377         break;
 378         case 2:
 379             if( value & Rc2OneEighthClock )
 380             {
 381                 rcnts[index].rate = 8;
 382             }
 383             else
 384             {
 385                 rcnts[index].rate = 1;
 386             }
 387
 388             // TODO: wcount must work.
 389             if( value & Rc2Disable )
 390             {
 391                 rcnts[index].rate = 0xffffffff;
 392             }
 393         break;
 394     }
 395
 396     _psxRcntWcount( index, 0 );
 397     psxRcntSet();
 398 }
 399
 400 void psxRcntWtarget( u32 index, u32 value )
 401 {
 402     verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
 403
 404     psxRcntUpdate();
 405
 406     rcnts[index].target = value;
 407
 408     _psxRcntWcount( index, _psxRcntRcount( index ) );
 409     psxRcntSet();
 410 }
 411
 412 /******************************************************************************/
 413
 414 u32 psxRcntRcount( u32 index )
 415 {
 416     u32 count;
 417
 418     psxRcntUpdate();
 419
 420     count = _psxRcntRcount( index );
 421
 422     // Parasite Eve 2 fix.
 423     if( Config.RCntFix )
 424     {
 425         if( index == 2 )
 426         {
 427             if( rcnts[index].counterState == CountToTarget )
 428             {
 429                 count /= BIAS;
 430             }
 431         }
 432     }
 433
 434     verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
 435
 436     return count;
 437 }
 438
 439 u32 psxRcntRmode( u32 index )
 440 {
 441     u16 mode;
 442
 443     psxRcntUpdate();
 444
 445     mode = rcnts[index].mode;
 446     rcnts[index].mode &= 0xe7ff;
 447
 448     verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
 449
 450     return mode;
 451 }
 452
 453 u32 psxRcntRtarget( u32 index )
 454 {
 455     verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
 456
 457     return rcnts[index].target;
 458 }
 459
 460 /******************************************************************************/
 461
 462 void psxRcntInit()
 463 {
 464     s32 i;
 465
 466     // rcnt 0.
 467     rcnts[0].rate   = 1;
 468     rcnts[0].irq    = 0x10;
 469
 470     // rcnt 1.
 471     rcnts[1].rate   = 1;
 472     rcnts[1].irq    = 0x20;
 473
 474     // rcnt 2.
 475     rcnts[2].rate   = 1;
 476     rcnts[2].irq    = 0x40;
 477
 478     // rcnt base.
 479     rcnts[3].rate   = 1;
 480     rcnts[3].mode   = RcCountToTarget;
 481     rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
 482
 483     for( i = 0; i < CounterQuantity; ++i )
 484     {
 485         _psxRcntWcount( i, 0 );
 486     }
 487
 488     hSyncCount = 0;
 489     spuSyncCount = 0;
 490     hsync_steps = 1;
 491
 492     psxRcntSet();
 493 }
 494
 495 /******************************************************************************/
 496
 497 s32 psxRcntFreeze( gzFile f, s32 Mode )
 498 {
 499     gzfreeze( &rcnts, sizeof(rcnts) );
 500     gzfreeze( &hSyncCount, sizeof(hSyncCount) );
 501     gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
 502     gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
 503     gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
 504
 505     if (Mode == 0)
 506         hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
 507
 508     return 0;
 509 }
 510
 511 /******************************************************************************/