libpcsxcore/psxhw.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
  18  ***************************************************************************/
  19
  20 /*
  21 * Functions for PSX hardware control.
  22 */
  23
  24 #include "psxhw.h"
  25 #include "psxevents.h"
  26 #include "mdec.h"
  27 #include "cdrom.h"
  28 #include "gpu.h"
  29
  30 void psxHwReset() {
  31         memset(psxH, 0, 0x10000);
  32
  33         mdecInit(); // initialize mdec decoder
  34         cdrReset();
  35         psxRcntInit();
  36         HW_GPU_STATUS = SWAP32(0x10802000);
  37 }
  38
  39 void psxHwWriteIstat(u32 value)
  40 {
  41         u32 stat = psxHu16(0x1070) & value;
  42         psxHu16ref(0x1070) = SWAPu16(stat);
  43
  44         psxRegs.CP0.n.Cause &= ~0x400;
  45         if (stat & psxHu16(0x1074))
  46                 psxRegs.CP0.n.Cause |= 0x400;
  47 }
  48
  49 void psxHwWriteImask(u32 value)
  50 {
  51         u32 stat = psxHu16(0x1070);
  52         psxHu16ref(0x1074) = SWAPu16(value);
  53         if (stat & value) {
  54                 //if ((psxRegs.CP0.n.SR & 0x401) == 0x401)
  55                 //      log_unhandled("irq on unmask @%08x\n", psxRegs.pc);
  56                 set_event(PSXINT_NEWDRC_CHECK, 1);
  57         }
  58         psxRegs.CP0.n.Cause &= ~0x400;
  59         if (stat & value)
  60                 psxRegs.CP0.n.Cause |= 0x400;
  61 }
  62
  63 #define make_dma_func(n, abort_func) \
  64 void psxHwWriteChcr##n(u32 value) \
  65 { \
  66         u32 old = SWAPu32(HW_DMA##n##_CHCR); \
  67         if (n == 6) { value &= 0x51000002; value |= 2; } \
  68         else        { value &= 0x71770703; } \
  69         if (value == old) \
  70                 return; \
  71         if (old & 0x01000000) \
  72                 log_unhandled("%u dma" #n " %08x -> %08x\n", psxRegs.cycle, old, value); \
  73         HW_DMA##n##_CHCR = SWAPu32(value); \
  74         if ((value ^ old) & 0x01000000) { \
  75                 if (!(value & 0x01000000)) \
  76                         abort_func; \
  77                 else if (SWAPu32(HW_DMA_PCR) & (8u << (n * 4))) \
  78                         psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), value); \
  79         } \
  80 }
  81
  82 make_dma_func(0,)
  83 make_dma_func(1,)
  84 make_dma_func(2, psxAbortDma2())
  85 make_dma_func(3,)
  86 make_dma_func(4,)
  87 make_dma_func(6,)
  88
  89 void psxHwWriteDmaIcr32(u32 value)
  90 {
  91         u32 tmp = value & 0x00ff803f;
  92         tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
  93         if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
  94             || tmp & HW_DMA_ICR_BUS_ERROR) {
  95                 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
  96                         psxHu32ref(0x1070) |= SWAP32(8);
  97                 tmp |= HW_DMA_ICR_IRQ_SENT;
  98         }
  99         HW_DMA_ICR = SWAPu32(tmp);
 100 }
 101
 102 void psxHwWriteGpuSR(u32 value)
 103 {
 104         u32 old_sr = HW_GPU_STATUS, new_sr;
 105         GPU_writeStatus(value);
 106         gpuSyncPluginSR();
 107         new_sr = HW_GPU_STATUS;
 108         // "The Next Tetris" seems to rely on the field order after enable
 109         if ((old_sr ^ new_sr) & new_sr & SWAP32(PSXGPU_ILACE))
 110                 frame_counter |= 1;
 111 }
 112
 113 u32 psxHwReadGpuSR(void)
 114 {
 115         u32 v, c = psxRegs.cycle;
 116
 117         // meh2, syncing for img bit, might want to avoid it..
 118         gpuSyncPluginSR();
 119         v = SWAP32(HW_GPU_STATUS);
 120         v |= ((s32)(psxRegs.gpuIdleAfter - c) >> 31) & PSXGPU_nBUSY;
 121
 122         // XXX: because of large timeslices can't use hSyncCount, using rough
 123         // approximization instead. Perhaps better use hcounter code here or something.
 124         if (hSyncCount < 240 && (v & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
 125                 v |= PSXGPU_LCF & (c << 20);
 126         return v;
 127 }
 128
 129 u32 sio1ReadStat16(void)
 130 {
 131         // Armored Core, F1 Link cable misdetection
 132         return 0xa0;
 133 }
 134
 135 u8 psxHwRead8(u32 add) {
 136         u8 hard;
 137
 138         switch (add & 0xffff) {
 139         case 0x1040: hard = sioRead8(); break;
 140         case 0x1800: hard = cdrRead0(); break;
 141         case 0x1801: hard = cdrRead1(); break;
 142         case 0x1802: hard = cdrRead2(); break;
 143         case 0x1803: hard = cdrRead3(); break;
 144
 145         case 0x1041: case 0x1042: case 0x1043:
 146         case 0x1044: case 0x1045:
 147         case 0x1046: case 0x1047:
 148         case 0x1048: case 0x1049:
 149         case 0x104a: case 0x104b:
 150         case 0x104c: case 0x104d:
 151         case 0x104e: case 0x104f:
 152         case 0x1050: case 0x1051:
 153         case 0x1054: case 0x1055:
 154         case 0x1058: case 0x1059:
 155         case 0x105a: case 0x105b:
 156         case 0x105c: case 0x105d:
 157         case 0x1100: case 0x1101:
 158         case 0x1104: case 0x1105:
 159         case 0x1108: case 0x1109:
 160         case 0x1110: case 0x1111:
 161         case 0x1114: case 0x1115:
 162         case 0x1118: case 0x1119:
 163         case 0x1120: case 0x1121:
 164         case 0x1124: case 0x1125:
 165         case 0x1128: case 0x1129:
 166         case 0x1810: case 0x1811:
 167         case 0x1812: case 0x1813:
 168         case 0x1814: case 0x1815:
 169         case 0x1816: case 0x1817:
 170         case 0x1820: case 0x1821:
 171         case 0x1822: case 0x1823:
 172         case 0x1824: case 0x1825:
 173         case 0x1826: case 0x1827:
 174                 log_unhandled("unhandled r8  %08x @%08x\n", add, psxRegs.pc);
 175                 // falthrough
 176         default:
 177                 if (0x1f801c00 <= add && add < 0x1f802000) {
 178                         u16 val = SPU_readRegister(add & ~1, psxRegs.cycle);
 179                         hard = (add & 1) ? val >> 8 : val;
 180                         break;
 181                 }
 182                 hard = psxHu8(add);
 183         }
 184
 185         //printf("r8  %08x       %02x @%08x\n", add, hard, psxRegs.pc);
 186         return hard;
 187 }
 188
 189 u16 psxHwRead16(u32 add) {
 190         unsigned short hard;
 191
 192         switch (add & 0xffff) {
 193         case 0x1040: hard = sioRead8(); break;
 194         case 0x1044: hard = sioReadStat16(); break;
 195         case 0x1048: hard = sioReadMode16(); break;
 196         case 0x104a: hard = sioReadCtrl16(); break;
 197         case 0x104e: hard = sioReadBaud16(); break;
 198         case 0x1054: hard = sio1ReadStat16(); break;
 199         case 0x1100: hard = psxRcntRcount0(); break;
 200         case 0x1104: hard = psxRcntRmode(0); break;
 201         case 0x1108: hard = psxRcntRtarget(0); break;
 202         case 0x1110: hard = psxRcntRcount1(); break;
 203         case 0x1114: hard = psxRcntRmode(1); break;
 204         case 0x1118: hard = psxRcntRtarget(1); break;
 205         case 0x1120: hard = psxRcntRcount2(); break;
 206         case 0x1124: hard = psxRcntRmode(2); break;
 207         case 0x1128: hard = psxRcntRtarget(2); break;
 208
 209         case 0x1042:
 210         case 0x1046:
 211         case 0x104c:
 212         case 0x1050:
 213         case 0x1058:
 214         case 0x105a:
 215         case 0x105c:
 216         case 0x1800:
 217         case 0x1802:
 218         case 0x1810:
 219         case 0x1812:
 220         case 0x1814:
 221         case 0x1816:
 222         case 0x1820:
 223         case 0x1822:
 224         case 0x1824:
 225         case 0x1826:
 226                 log_unhandled("unhandled r16 %08x @%08x\n", add, psxRegs.pc);
 227                 // falthrough
 228         default:
 229                 if (0x1f801c00 <= add && add < 0x1f802000) {
 230                         hard = SPU_readRegister(add, psxRegs.cycle);
 231                         break;
 232                 }
 233                 hard = psxHu16(add);
 234         }
 235
 236         //printf("r16 %08x     %04x @%08x\n", add, hard, psxRegs.pc);
 237         return hard;
 238 }
 239
 240 u32 psxHwRead32(u32 add) {
 241         u32 hard;
 242
 243         switch (add & 0xffff) {
 244         case 0x1040: hard = sioRead8(); break;
 245         case 0x1044: hard = sioReadStat16(); break;
 246         case 0x1100: hard = psxRcntRcount0(); break;
 247         case 0x1104: hard = psxRcntRmode(0); break;
 248         case 0x1108: hard = psxRcntRtarget(0); break;
 249         case 0x1110: hard = psxRcntRcount1(); break;
 250         case 0x1114: hard = psxRcntRmode(1); break;
 251         case 0x1118: hard = psxRcntRtarget(1); break;
 252         case 0x1120: hard = psxRcntRcount2(); break;
 253         case 0x1124: hard = psxRcntRmode(2); break;
 254         case 0x1128: hard = psxRcntRtarget(2); break;
 255         case 0x1810: hard = GPU_readData(); break;
 256         case 0x1814: hard = psxHwReadGpuSR(); break;
 257         case 0x1820: hard = mdecRead0(); break;
 258         case 0x1824: hard = mdecRead1(); break;
 259
 260         case 0x1048:
 261         case 0x104c:
 262         case 0x1050:
 263         case 0x1054:
 264         case 0x1058:
 265         case 0x105c:
 266         case 0x1800:
 267                 log_unhandled("unhandled r32 %08x @%08x\n", add, psxRegs.pc);
 268                 // falthrough
 269         default:
 270                 if (0x1f801c00 <= add && add < 0x1f802000) {
 271                         hard = SPU_readRegister(add, psxRegs.cycle);
 272                         hard |= SPU_readRegister(add + 2, psxRegs.cycle) << 16;
 273                         break;
 274                 }
 275                 hard = psxHu32(add);
 276         }
 277         //printf("r32 %08x %08x @%08x\n", add, hard, psxRegs.pc);
 278         return hard;
 279 }
 280
 281 void psxHwWrite8(u32 add, u32 value) {
 282         switch (add & 0xffff) {
 283         case 0x1040: sioWrite8(value); return;
 284         case 0x10f6:
 285                 // nocash documents it as forced w32, but still games use this?
 286                 break;
 287         case 0x1800: cdrWrite0(value); return;
 288         case 0x1801: cdrWrite1(value); return;
 289         case 0x1802: cdrWrite2(value); return;
 290         case 0x1803: cdrWrite3(value); return;
 291         case 0x2041: break; // "POST (external 7 segment display)"
 292
 293         default:
 294                 if (0x1f801c00 <= add && add < 0x1f802000) {
 295                         log_unhandled("spu w8 %02x @%08x\n", value, psxRegs.pc);
 296                         if (!(add & 1))
 297                                 SPU_writeRegister(add, value, psxRegs.cycle);
 298                         return;
 299                 }
 300                 else
 301                         log_unhandled("unhandled w8  %08x %08x @%08x\n",
 302                                 add, value, psxRegs.pc);
 303         }
 304         psxHu8(add) = value;
 305 }
 306
 307 void psxHwWrite16(u32 add, u32 value) {
 308         switch (add & 0xffff) {
 309         case 0x1040: sioWrite8(value); return;
 310         case 0x1044: sioWriteStat16(value); return;
 311         case 0x1048: sioWriteMode16(value); return;
 312         case 0x104a: sioWriteCtrl16(value); return;
 313         case 0x104e: sioWriteBaud16(value); return;
 314         case 0x1070: psxHwWriteIstat(value); return;
 315         case 0x1074: psxHwWriteImask(value); return;
 316         case 0x1100: psxRcntWcount(0, value); return;
 317         case 0x1104: psxRcntWmode(0, value); return;
 318         case 0x1108: psxRcntWtarget(0, value); return;
 319         case 0x1110: psxRcntWcount(1, value); return;
 320         case 0x1114: psxRcntWmode(1, value); return;
 321         case 0x1118: psxRcntWtarget(1, value); return;
 322         case 0x1120: psxRcntWcount(2, value); return;
 323         case 0x1124: psxRcntWmode(2, value); return;
 324         case 0x1128: psxRcntWtarget(2, value); return;
 325
 326         // forced write32:
 327         case 0x1088: // DMA0 chcr (MDEC in DMA)
 328         case 0x108c: psxHwWriteChcr0(value); return;
 329         case 0x1098: // DMA1 chcr (MDEC out DMA)
 330         case 0x109c: psxHwWriteChcr1(value); return;
 331         case 0x10a8: // DMA2 chcr (GPU DMA)
 332         case 0x10ac: psxHwWriteChcr2(value); return;
 333         case 0x10b8: // DMA3 chcr (CDROM DMA)
 334         case 0x10bc: psxHwWriteChcr3(value); return;
 335         case 0x10c8: // DMA4 chcr (SPU DMA)
 336         case 0x10cc: psxHwWriteChcr4(value); return;
 337         case 0x10e8: // DMA6 chcr (OT clear)
 338         case 0x10ec: psxHwWriteChcr6(value); return;
 339         case 0x10f4: psxHwWriteDmaIcr32(value); return;
 340
 341         // forced write32 with no immediate effect:
 342         case 0x1014:
 343         case 0x1060:
 344         case 0x1080:
 345         case 0x1090:
 346         case 0x10a0:
 347         case 0x10b0:
 348         case 0x10c0:
 349         case 0x10d0:
 350         case 0x10e0:
 351         case 0x10f0:
 352                 psxHu32ref(add) = SWAPu32(value);
 353                 return;
 354
 355         case 0x1800:
 356         case 0x1802:
 357         case 0x1810:
 358         case 0x1812:
 359         case 0x1814:
 360         case 0x1816:
 361         case 0x1820:
 362         case 0x1822:
 363         case 0x1824:
 364         case 0x1826:
 365                 log_unhandled("unhandled w16 %08x @%08x\n", add, psxRegs.pc);
 366                 break;
 367
 368         default:
 369                 if (0x1f801c00 <= add && add < 0x1f802000) {
 370                         SPU_writeRegister(add, value, psxRegs.cycle);
 371                         return;
 372                 }
 373                 else if (0x1f801000 <= add && add < 0x1f801800)
 374                         log_unhandled("unhandled w16 %08x %08x @%08x\n",
 375                                 add, value, psxRegs.pc);
 376         }
 377         psxHu16ref(add) = SWAPu16(value);
 378 }
 379
 380 void psxHwWrite32(u32 add, u32 value) {
 381         switch (add & 0xffff) {
 382         case 0x1040: sioWrite8(value); return;
 383         case 0x1070: psxHwWriteIstat(value); return;
 384         case 0x1074: psxHwWriteImask(value); return;
 385         case 0x1088: // DMA0 chcr (MDEC in DMA)
 386         case 0x108c: psxHwWriteChcr0(value); return;
 387         case 0x1098: // DMA1 chcr (MDEC out DMA)
 388         case 0x109c: psxHwWriteChcr1(value); return;
 389         case 0x10a8: // DMA2 chcr (GPU DMA)
 390         case 0x10ac: psxHwWriteChcr2(value); return;
 391         case 0x10b8: // DMA3 chcr (CDROM DMA)
 392         case 0x10bc: psxHwWriteChcr3(value); return;
 393         case 0x10c8: // DMA4 chcr (SPU DMA)
 394         case 0x10cc: psxHwWriteChcr4(value); return;
 395         case 0x10e8: // DMA6 chcr (OT clear)
 396         case 0x10ec: psxHwWriteChcr6(value); return;
 397         case 0x10f4: psxHwWriteDmaIcr32(value); return;
 398
 399         case 0x1810: GPU_writeData(value); return;
 400         case 0x1814: psxHwWriteGpuSR(value); return;
 401         case 0x1820: mdecWrite0(value); break;
 402         case 0x1824: mdecWrite1(value); break;
 403
 404         case 0x1100: psxRcntWcount(0, value & 0xffff); return;
 405         case 0x1104: psxRcntWmode(0, value); return;
 406         case 0x1108: psxRcntWtarget(0, value & 0xffff); return;
 407         case 0x1110: psxRcntWcount(1, value & 0xffff); return;
 408         case 0x1114: psxRcntWmode(1, value); return;
 409         case 0x1118: psxRcntWtarget(1, value & 0xffff); return;
 410         case 0x1120: psxRcntWcount(2, value & 0xffff); return;
 411         case 0x1124: psxRcntWmode(2, value); return;
 412         case 0x1128: psxRcntWtarget(2, value & 0xffff); return;
 413
 414         case 0x1044:
 415         case 0x1048:
 416         case 0x104c:
 417         case 0x1050:
 418         case 0x1054:
 419         case 0x1058:
 420         case 0x105c:
 421         case 0x1800:
 422                 log_unhandled("unhandled w32 %08x %08x @%08x\n", add, value, psxRegs.pc);
 423                 break;
 424
 425         default:
 426                 if (0x1f801c00 <= add && add < 0x1f802000) {
 427                         SPU_writeRegister(add, value&0xffff, psxRegs.cycle);
 428                         SPU_writeRegister(add + 2, value>>16, psxRegs.cycle);
 429                         return;
 430                 }
 431         }
 432         psxHu32ref(add) = SWAPu32(value);
 433 }
 434
 435 int psxHwFreeze(void *f, int Mode) {
 436         return 0;
 437 }