libpcsxcore/r3000a.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
  18  ***************************************************************************/
  19
  20 /*
  21 * R3000A CPU functions.
  22 */
  23
  24 #include "r3000a.h"
  25 #include "cdrom.h"
  26 #include "mdec.h"
  27 #include "gte.h"
  28
  29 R3000Acpu *psxCpu = NULL;
  30 #ifdef DRC_DISABLE
  31 psxRegisters psxRegs;
  32 #endif
  33
  34 int psxInit() {
  35         SysPrintf(_("Running PCSX Version %s (%s).\n"), PACKAGE_VERSION, __DATE__);
  36
  37 #ifndef DRC_DISABLE
  38         if (Config.Cpu == CPU_INTERPRETER) {
  39                 psxCpu = &psxInt;
  40         } else psxCpu = &psxRec;
  41 #else
  42         psxCpu = &psxInt;
  43 #endif
  44
  45         Log = 0;
  46
  47         if (psxMemInit() == -1) return -1;
  48
  49         return psxCpu->Init();
  50 }
  51
  52 void psxReset() {
  53         psxMemReset();
  54
  55         memset(&psxRegs, 0, sizeof(psxRegs));
  56
  57         psxRegs.pc = 0xbfc00000; // Start in bootstrap
  58
  59         psxRegs.CP0.r[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
  60         psxRegs.CP0.r[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
  61
  62         psxCpu->Reset();
  63
  64         psxHwReset();
  65         psxBiosInit();
  66
  67         if (!Config.HLE)
  68                 psxExecuteBios();
  69
  70 #ifdef EMU_LOG
  71         EMU_LOG("*BIOS END*\n");
  72 #endif
  73         Log = 0;
  74 }
  75
  76 void psxShutdown() {
  77         psxMemShutdown();
  78         psxBiosShutdown();
  79
  80         psxCpu->Shutdown();
  81 }
  82
  83 void psxException(u32 code, u32 bd) {
  84         #ifdef ICACHE_EMULATION
  85         /* Dynarecs may use this codepath and crash as a result.
  86          * This should only be used for the interpreter. - Gameblabla
  87          * */
  88         if (Config.icache_emulation && Config.Cpu == CPU_INTERPRETER)
  89         {
  90                 psxRegs.code = SWAPu32(*Read_ICache(psxRegs.pc));
  91         }
  92         else
  93         #endif
  94         {
  95                 psxRegs.code = PSXMu32(psxRegs.pc);
  96         }
  97
  98         if (!Config.HLE && ((((psxRegs.code) >> 24) & 0xfe) == 0x4a)) {
  99                 // "hokuto no ken" / "Crash Bandicot 2" ...
 100                 // BIOS does not allow to return to GTE instructions
 101                 // (just skips it, supposedly because it's scheduled already)
 102                 // so we execute it here
 103                 extern void (*psxCP2[64])(void *cp2regs);
 104                 psxCP2[psxRegs.code & 0x3f](&psxRegs.CP2D);
 105         }
 106
 107         // Set the Cause
 108         psxRegs.CP0.n.Cause = (psxRegs.CP0.n.Cause & 0x300) | code;
 109
 110         // Set the EPC & PC
 111         if (bd) {
 112 #ifdef PSXCPU_LOG
 113                 PSXCPU_LOG("bd set!!!\n");
 114 #endif
 115                 psxRegs.CP0.n.Cause |= 0x80000000;
 116                 psxRegs.CP0.n.EPC = (psxRegs.pc - 4);
 117         } else
 118                 psxRegs.CP0.n.EPC = (psxRegs.pc);
 119
 120         if (psxRegs.CP0.n.Status & 0x400000)
 121                 psxRegs.pc = 0xbfc00180;
 122         else
 123                 psxRegs.pc = 0x80000080;
 124
 125         // Set the Status
 126         psxRegs.CP0.n.Status = (psxRegs.CP0.n.Status &~0x3f) |
 127                                                   ((psxRegs.CP0.n.Status & 0xf) << 2);
 128
 129         if (Config.HLE) psxBiosException();
 130 }
 131
 132 void psxBranchTest() {
 133         if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
 134                 psxRcntUpdate();
 135
 136         if (psxRegs.interrupt) {
 137                 if ((psxRegs.interrupt & (1 << PSXINT_SIO)) && !Config.Sio) { // sio
 138                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) {
 139                                 psxRegs.interrupt &= ~(1 << PSXINT_SIO);
 140                                 sioInterrupt();
 141                         }
 142                 }
 143                 if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr
 144                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) {
 145                                 psxRegs.interrupt &= ~(1 << PSXINT_CDR);
 146                                 cdrInterrupt();
 147                         }
 148                 }
 149                 if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read
 150                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) {
 151                                 psxRegs.interrupt &= ~(1 << PSXINT_CDREAD);
 152                                 cdrReadInterrupt();
 153                         }
 154                 }
 155                 if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma
 156                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) {
 157                                 psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA);
 158                                 gpuInterrupt();
 159                         }
 160                 }
 161                 if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma
 162                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) {
 163                                 psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA);
 164                                 mdec1Interrupt();
 165                         }
 166                 }
 167                 if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma
 168                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) {
 169                                 psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA);
 170                                 spuInterrupt();
 171                         }
 172                 }
 173                 if (psxRegs.interrupt & (1 << PSXINT_MDECINDMA)) { // mdec in
 174                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECINDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECINDMA].cycle) {
 175                                 psxRegs.interrupt &= ~(1 << PSXINT_MDECINDMA);
 176                                 mdec0Interrupt();
 177                         }
 178                 }
 179                 if (psxRegs.interrupt & (1 << PSXINT_GPUOTCDMA)) { // gpu otc
 180                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle) {
 181                                 psxRegs.interrupt &= ~(1 << PSXINT_GPUOTCDMA);
 182                                 gpuotcInterrupt();
 183                         }
 184                 }
 185                 if (psxRegs.interrupt & (1 << PSXINT_CDRDMA)) { // cdrom
 186                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDMA].sCycle) >= psxRegs.intCycle[PSXINT_CDRDMA].cycle) {
 187                                 psxRegs.interrupt &= ~(1 << PSXINT_CDRDMA);
 188                                 cdrDmaInterrupt();
 189                         }
 190                 }
 191                 if (psxRegs.interrupt & (1 << PSXINT_CDRPLAY)) { // cdr play timing
 192                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRPLAY].sCycle) >= psxRegs.intCycle[PSXINT_CDRPLAY].cycle) {
 193                                 psxRegs.interrupt &= ~(1 << PSXINT_CDRPLAY);
 194                                 cdrPlayInterrupt();
 195                         }
 196                 }
 197                 if (psxRegs.interrupt & (1 << PSXINT_CDRLID)) { // cdr lid states
 198                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRLID].sCycle) >= psxRegs.intCycle[PSXINT_CDRLID].cycle) {
 199                                 psxRegs.interrupt &= ~(1 << PSXINT_CDRLID);
 200                                 cdrLidSeekInterrupt();
 201                         }
 202                 }
 203                 if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update
 204                         if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) {
 205                                 psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE);
 206                                 spuUpdate();
 207                         }
 208                 }
 209         }
 210
 211         if (psxHu32(0x1070) & psxHu32(0x1074)) {
 212                 if ((psxRegs.CP0.n.Status & 0x401) == 0x401) {
 213 #ifdef PSXCPU_LOG
 214                         PSXCPU_LOG("Interrupt: %x %x\n", psxHu32(0x1070), psxHu32(0x1074));
 215 #endif
 216 //                      SysPrintf("Interrupt (%x): %x %x\n", psxRegs.cycle, psxHu32(0x1070), psxHu32(0x1074));
 217                         psxException(0x400, 0);
 218                 }
 219         }
 220 }
 221
 222 void psxJumpTest() {
 223         if (!Config.HLE && Config.PsxOut) {
 224                 u32 call = psxRegs.GPR.n.t1 & 0xff;
 225                 switch (psxRegs.pc & 0x1fffff) {
 226                         case 0xa0:
 227 #ifdef PSXBIOS_LOG
 228                                 if (call != 0x28 && call != 0xe) {
 229                                         PSXBIOS_LOG("Bios call a0: %s (%x) %x,%x,%x,%x\n", biosA0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
 230 #endif
 231                                 if (biosA0[call])
 232                                         biosA0[call]();
 233                                 break;
 234                         case 0xb0:
 235 #ifdef PSXBIOS_LOG
 236                                 if (call != 0x17 && call != 0xb) {
 237                                         PSXBIOS_LOG("Bios call b0: %s (%x) %x,%x,%x,%x\n", biosB0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
 238 #endif
 239                                 if (biosB0[call])
 240                                         biosB0[call]();
 241                                 break;
 242                         case 0xc0:
 243 #ifdef PSXBIOS_LOG
 244                                 PSXBIOS_LOG("Bios call c0: %s (%x) %x,%x,%x,%x\n", biosC0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
 245 #endif
 246                                 if (biosC0[call])
 247                                         biosC0[call]();
 248                                 break;
 249                 }
 250         }
 251 }
 252
 253 void psxExecuteBios() {
 254         while (psxRegs.pc != 0x80030000)
 255                 psxCpu->ExecuteBlock();
 256 }
 257