libpcsxcore/r3000a.h

   1 /***************************************************************************
   2  *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
  18  ***************************************************************************/
  19
  20 #ifndef __R3000A_H__
  21 #define __R3000A_H__
  22
  23 #ifdef __cplusplus
  24 extern "C" {
  25 #endif
  26
  27 #include "psxcommon.h"
  28 #include "psxmem.h"
  29 #include "psxcounters.h"
  30 #include "psxbios.h"
  31
  32 typedef struct {
  33         int  (*Init)();
  34         void (*Reset)();
  35         void (*Execute)();              /* executes up to a break */
  36         void (*ExecuteBlock)(); /* executes up to a jump */
  37         void (*Clear)(u32 Addr, u32 Size);
  38         void (*Shutdown)();
  39 } R3000Acpu;
  40
  41 extern R3000Acpu *psxCpu;
  42 extern R3000Acpu psxInt;
  43 #if (defined(__x86_64__) || defined(__i386__) || defined(__sh__) || defined(__ppc__) || defined(__arm__)) && !defined(NOPSXREC)
  44 extern R3000Acpu psxRec;
  45 #define PSXREC
  46 #endif
  47
  48 typedef union {
  49 #if defined(__BIGENDIAN__)
  50         struct { u8 h3, h2, h, l; } b;
  51         struct { s8 h3, h2, h, l; } sb;
  52         struct { u16 h, l; } w;
  53         struct { s16 h, l; } sw;
  54 #else
  55         struct { u8 l, h, h2, h3; } b;
  56         struct { u16 l, h; } w;
  57         struct { s8 l, h, h2, h3; } sb;
  58         struct { s16 l, h; } sw;
  59 #endif
  60 } PAIR;
  61
  62 typedef union {
  63         struct {
  64                 u32   r0, at, v0, v1, a0, a1, a2, a3,
  65                                                 t0, t1, t2, t3, t4, t5, t6, t7,
  66                                                 s0, s1, s2, s3, s4, s5, s6, s7,
  67                                                 t8, t9, k0, k1, gp, sp, s8, ra, lo, hi;
  68         } n;
  69         u32 r[34]; /* Lo, Hi in r[32] and r[33] */
  70         PAIR p[34];
  71 } psxGPRRegs;
  72
  73 typedef union {
  74         struct {
  75                 u32     Index,     Random,    EntryLo0,  EntryLo1,
  76                                                 Context,   PageMask,  Wired,     Reserved0,
  77                                                 BadVAddr,  Count,     EntryHi,   Compare,
  78                                                 Status,    Cause,     EPC,       PRid,
  79                                                 Config,    LLAddr,    WatchLO,   WatchHI,
  80                                                 XContext,  Reserved1, Reserved2, Reserved3,
  81                                                 Reserved4, Reserved5, ECC,       CacheErr,
  82                                                 TagLo,     TagHi,     ErrorEPC,  Reserved6;
  83         } n;
  84         u32 r[32];
  85         PAIR p[32];
  86 } psxCP0Regs;
  87
  88 typedef struct {
  89         short x, y;
  90 } SVector2D;
  91
  92 typedef struct {
  93         short z, pad;
  94 } SVector2Dz;
  95
  96 typedef struct {
  97         short x, y, z, pad;
  98 } SVector3D;
  99
 100 typedef struct {
 101         short x, y, z, pad;
 102 } LVector3D;
 103
 104 typedef struct {
 105         unsigned char r, g, b, c;
 106 } CBGR;
 107
 108 typedef struct {
 109         short m11, m12, m13, m21, m22, m23, m31, m32, m33, pad;
 110 } SMatrix3D;
 111
 112 typedef union {
 113         struct {
 114                 SVector3D     v0, v1, v2;
 115                 CBGR          rgb;
 116                 s32          otz;
 117                 s32          ir0, ir1, ir2, ir3;
 118                 SVector2D     sxy0, sxy1, sxy2, sxyp;
 119                 SVector2Dz    sz0, sz1, sz2, sz3;
 120                 CBGR          rgb0, rgb1, rgb2;
 121                 s32          reserved;
 122                 s32          mac0, mac1, mac2, mac3;
 123                 u32 irgb, orgb;
 124                 s32          lzcs, lzcr;
 125         } n;
 126         u32 r[32];
 127         PAIR p[32];
 128 } psxCP2Data;
 129
 130 typedef union {
 131         struct {
 132                 SMatrix3D rMatrix;
 133                 s32      trX, trY, trZ;
 134                 SMatrix3D lMatrix;
 135                 s32      rbk, gbk, bbk;
 136                 SMatrix3D cMatrix;
 137                 s32      rfc, gfc, bfc;
 138                 s32      ofx, ofy;
 139                 s32      h;
 140                 s32      dqa, dqb;
 141                 s32      zsf3, zsf4;
 142                 s32      flag;
 143         } n;
 144         u32 r[32];
 145         PAIR p[32];
 146 } psxCP2Ctrl;
 147
 148 enum {
 149         PSXINT_SIO = 0,
 150         PSXINT_CDR,
 151         PSXINT_CDREAD,
 152         PSXINT_GPUDMA,
 153         PSXINT_MDECOUTDMA,
 154         PSXINT_SPUDMA,
 155         PSXINT_GPUBUSY,
 156         PSXINT_MDECINDMA,
 157         PSXINT_GPUOTCDMA,
 158         PSXINT_CDRDMA,
 159         PSXINT_NEWDRC_CHECK,
 160         PSXINT_RCNT,
 161         PSXINT_CDRLID,
 162         PSXINT_CDRPLAY,
 163         PSXINT_SPU_UPDATE,
 164         PSXINT_COUNT
 165 };
 166
 167 typedef struct psxCP2Regs {
 168         psxCP2Data CP2D;        /* Cop2 data registers */
 169         psxCP2Ctrl CP2C;        /* Cop2 control registers */
 170 } psxCP2Regs;
 171
 172 typedef struct {
 173         psxGPRRegs GPR;         /* General Purpose Registers */
 174         psxCP0Regs CP0;         /* Coprocessor0 Registers */
 175         union {
 176                 struct {
 177                         psxCP2Data CP2D;        /* Cop2 data registers */
 178                         psxCP2Ctrl CP2C;        /* Cop2 control registers */
 179                 };
 180                 psxCP2Regs CP2;
 181         };
 182     u32 pc;                             /* Program counter */
 183     u32 code;                   /* The instruction */
 184         u32 cycle;
 185         u32 interrupt;
 186         struct { u32 sCycle, cycle; } intCycle[32];
 187 } psxRegisters;
 188
 189 extern psxRegisters psxRegs;
 190
 191 /* new_dynarec stuff */
 192 extern u32 event_cycles[PSXINT_COUNT];
 193 extern u32 next_interupt;
 194
 195 void new_dyna_save(void);
 196 void new_dyna_after_save(void);
 197 void new_dyna_restore(void);
 198
 199 #define new_dyna_set_event(e, c) { \
 200         s32 c_ = c; \
 201         u32 abs_ = psxRegs.cycle + c_; \
 202         s32 odi_ = next_interupt - psxRegs.cycle; \
 203         event_cycles[e] = abs_; \
 204         if (c_ < odi_) { \
 205                 /*printf("%u: next_interupt %d -> %d (%u)\n", psxRegs.cycle, odi_, c_, abs_);*/ \
 206                 next_interupt = abs_; \
 207         } \
 208 }
 209
 210 #if defined(__BIGENDIAN__)
 211
 212 #define _i32(x) *(s32 *)&x
 213 #define _u32(x) x
 214
 215 #define _i16(x) (((short *)&x)[1])
 216 #define _u16(x) (((unsigned short *)&x)[1])
 217
 218 #define _i8(x) (((char *)&x)[3])
 219 #define _u8(x) (((unsigned char *)&x)[3])
 220
 221 #else
 222
 223 #define _i32(x) *(s32 *)&x
 224 #define _u32(x) x
 225
 226 #define _i16(x) *(short *)&x
 227 #define _u16(x) *(unsigned short *)&x
 228
 229 #define _i8(x) *(char *)&x
 230 #define _u8(x) *(unsigned char *)&x
 231
 232 #endif
 233
 234 /**** R3000A Instruction Macros ****/
 235 #define _PC_       psxRegs.pc       // The next PC to be executed
 236
 237 #define _fOp_(code)             ((code >> 26)       )  // The opcode part of the instruction register
 238 #define _fFunct_(code)  ((code      ) & 0x3F)  // The funct part of the instruction register
 239 #define _fRd_(code)             ((code >> 11) & 0x1F)  // The rd part of the instruction register
 240 #define _fRt_(code)             ((code >> 16) & 0x1F)  // The rt part of the instruction register
 241 #define _fRs_(code)             ((code >> 21) & 0x1F)  // The rs part of the instruction register
 242 #define _fSa_(code)             ((code >>  6) & 0x1F)  // The sa part of the instruction register
 243 #define _fIm_(code)             ((u16)code)            // The immediate part of the instruction register
 244 #define _fTarget_(code) (code & 0x03ffffff)    // The target part of the instruction register
 245
 246 #define _fImm_(code)    ((s16)code)            // sign-extended immediate
 247 #define _fImmU_(code)   (code&0xffff)          // zero-extended immediate
 248
 249 #define _Op_     _fOp_(psxRegs.code)
 250 #define _Funct_  _fFunct_(psxRegs.code)
 251 #define _Rd_     _fRd_(psxRegs.code)
 252 #define _Rt_     _fRt_(psxRegs.code)
 253 #define _Rs_     _fRs_(psxRegs.code)
 254 #define _Sa_     _fSa_(psxRegs.code)
 255 #define _Im_     _fIm_(psxRegs.code)
 256 #define _Target_ _fTarget_(psxRegs.code)
 257
 258 #define _Imm_    _fImm_(psxRegs.code)
 259 #define _ImmU_   _fImmU_(psxRegs.code)
 260
 261 #define _rRs_   psxRegs.GPR.r[_Rs_]   // Rs register
 262 #define _rRt_   psxRegs.GPR.r[_Rt_]   // Rt register
 263 #define _rRd_   psxRegs.GPR.r[_Rd_]   // Rd register
 264 #define _rSa_   psxRegs.GPR.r[_Sa_]   // Sa register
 265 #define _rFs_   psxRegs.CP0.r[_Rd_]   // Fs register
 266
 267 #define _c2dRs_ psxRegs.CP2D.r[_Rs_]  // Rs cop2 data register
 268 #define _c2dRt_ psxRegs.CP2D.r[_Rt_]  // Rt cop2 data register
 269 #define _c2dRd_ psxRegs.CP2D.r[_Rd_]  // Rd cop2 data register
 270 #define _c2dSa_ psxRegs.CP2D.r[_Sa_]  // Sa cop2 data register
 271
 272 #define _rHi_   psxRegs.GPR.n.hi   // The HI register
 273 #define _rLo_   psxRegs.GPR.n.lo   // The LO register
 274
 275 #define _JumpTarget_    ((_Target_ * 4) + (_PC_ & 0xf0000000))   // Calculates the target during a jump instruction
 276 #define _BranchTarget_  ((s16)_Im_ * 4 + _PC_)                 // Calculates the target during a branch instruction
 277
 278 #define _SetLink(x)     psxRegs.GPR.r[x] = _PC_ + 4;       // Sets the return address in the link register
 279
 280 int  psxInit();
 281 void psxReset();
 282 void psxShutdown();
 283 void psxException(u32 code, u32 bd);
 284 void psxBranchTest();
 285 void psxExecuteBios();
 286 int  psxTestLoadDelay(int reg, u32 tmp);
 287 void psxDelayTest(int reg, u32 bpc);
 288 void psxTestSWInts();
 289 void psxJumpTest();
 290
 291 #ifdef __cplusplus
 292 }
 293 #endif
 294 #endif