drc: something works on arm64

[pcsx_rearmed.git] / libpcsxcore / gte.c

diff --git a/libpcsxcore/gte.c b/libpcsxcore/gte.c
index 77dff1b..e05f33d 100644 (file)
--- a/libpcsxcore/gte.c
+++ b/libpcsxcore/gte.c
@@ -149,7 +149,13 @@
 #define gteBFC (((s32 *)regs->CP2C.r)[23])
 #define gteOFX (((s32 *)regs->CP2C.r)[24])
 #define gteOFY (((s32 *)regs->CP2C.r)[25])
-#define gteH   (regs->CP2C.p[26].sw.l)
+// senquack - gteH register is u16, not s16, and used in GTE that way.
+//  HOWEVER when read back by CPU using CFC2, it will be incorrectly
+//  sign-extended by bug in original hardware, according to Nocash docs
+//  GTE section 'Screen Offset and Distance'. The emulator does this
+//  sign extension when it is loaded to GTE by CTC2.
+//#define gteH   (psxRegs.CP2C.p[26].sw.l)
+#define gteH   (psxRegs.CP2C.p[26].w.l)
 #define gteDQA (regs->CP2C.p[27].sw.l)
 #define gteDQB (((s32 *)regs->CP2C.r)[28])
 #define gteZSF3 (regs->CP2C.p[29].sw.l)
@@ -254,7 +260,18 @@ static inline u32 limE_(psxCP2Regs *regs, u32 result) {
 #define A3U(x) (x)
 #endif
 
+
+//senquack - n param should be unsigned (will be 'gteH' reg which is u16)
+#ifdef GTE_USE_NATIVE_DIVIDE
+INLINE u32 DIVIDE(u16 n, u16 d) {
+       if (n < d * 2) {
+               return ((u32)n << 16) / d;
+       }
+       return 0xffffffff;
+}
+#else
 #include "gte_divider.h"
+#endif // GTE_USE_NATIVE_DIVIDE
 
 #ifndef FLAGLESS
 
@@ -305,9 +322,10 @@ static inline void MTC2(u32 value, int reg) {
 
                case 28:
                        gteIRGB = value;
-                       gteIR1 = (value & 0x1f) << 7;
-                       gteIR2 = (value & 0x3e0) << 2;
-                       gteIR3 = (value & 0x7c00) >> 3;
+                       // not gteIR1 etc. just to be consistent with dynarec
+                       regs->CP2D.n.ir1 = (value & 0x1f) << 7;
+                       regs->CP2D.n.ir2 = (value & 0x3e0) << 2;
+                       regs->CP2D.n.ir3 = (value & 0x7c00) >> 3;
                        break;
 
                case 30: