/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
- * Mupen64plus - assem_arm.c *
- * Copyright (C) 2009-2010 Ari64 *
+ * Mupen64plus/PCSX - assem_arm.c *
+ * Copyright (C) 2009-2011 Ari64 *
+ * Copyright (C) 2010-2011 GraÅžvydas "notaz" Ignotas *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
/* Literal pool */
add_literal(int addr,int val)
{
+ assert(literalcount<sizeof(literals)/sizeof(literals[0]));
literals[literalcount][0]=addr;
literals[literalcount][1]=val;
literalcount++;
return i_ptr;
}
+// find where external branch is liked to using addr of it's stub:
+// get address that insn one after stub loads (dyna_linker arg1),
+// treat it as a pointer to branch insn,
+// return addr where that branch jumps to
int get_pointer(void *stub)
{
//printf("get_pointer(%x)\n",(int)stub);
int *ptr=(int *)(stub+4);
- assert((*ptr&0x0ff00000)==0x05900000);
+ assert((*ptr&0x0fff0000)==0x059f0000);
u_int offset=*ptr&0xfff;
int **l_ptr=(void *)ptr+offset+8;
int *i_ptr=*l_ptr;
u_int *ptr=(u_int *)addr;
#ifdef ARMv5_ONLY
// get from literal pool
- assert((*ptr&0xFFF00000)==0xe5900000);
+ assert((*ptr&0xFFFF0000)==0xe59f0000);
u_int offset=*ptr&0xfff;
u_int *l_ptr=(void *)ptr+offset+8;
u_int source=l_ptr[0];
u_int *ptr=(u_int *)addr;
#ifdef ARMv5_ONLY
// get from literal pool
- assert((*ptr&0xFFF00000)==0xe5900000);
+ assert((*ptr&0xFFFF0000)==0xe59f0000);
u_int offset=*ptr&0xfff;
u_int *l_ptr=(void *)ptr+offset+8;
u_int source=l_ptr[0];
void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
{
int n;
+ int dirty=0;
// see if it's already allocated (and dealloc it)
for(n=0;n<HOST_REGS;n++)
{
- if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {cur->regmap[n]=-1;}
+ if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {
+ dirty=(cur->dirty>>n)&1;
+ cur->regmap[n]=-1;
+ }
}
cur->regmap[hr]=reg;
cur->dirty&=~(1<<hr);
+ cur->dirty|=dirty<<hr;
cur->isconst&=~(1<<hr);
}
}
u_int genimm(u_int imm,u_int *encoded)
{
- if(imm==0) {*encoded=0;return 1;}
+ *encoded=0;
+ if(imm==0) return 1;
int i=32;
while(i>0)
{
#ifdef FORCE32
if(r&64) {
printf("64bit load in 32bit mode!\n");
- exit(1);
+ assert(0);
+ return;
}
#endif
if((r&63)==0)
#ifdef FORCE32
if(r&64) {
printf("64bit store in 32bit mode!\n");
- exit(1);
+ assert(0);
+ return;
}
#endif
int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
void emit_testimm(int rs,int imm)
{
u_int armval;
- assem_debug("tst %s,$%d\n",regname[rs],imm);
+ assem_debug("tst %s,#%d\n",regname[rs],imm);
genimm_checked(imm,&armval);
output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
}
assert(rs<16);
assert(rt<16);
if(imm!=0) {
- assert(imm>-65536&&imm<65536);
u_int armval;
if(genimm(imm,&armval)) {
assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],imm);
output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
}else if(imm<0) {
+ assert(imm>-65536);
assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
}else{
+ assert(imm<65536);
assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
output_w32(0xe2800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
}
+void emit_lsls_imm(int rs,int imm,int rt)
+{
+ assert(imm>0);
+ assert(imm<32);
+ assem_debug("lsls %s,%s,#%d\n",regname[rt],regname[rs],imm);
+ output_w32(0xe1b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
+}
+
void emit_shrimm(int rs,u_int imm,int rt)
{
assert(imm>0);
#endif
}
+void emit_signextend8(int rs,int rt)
+{
+ #ifdef ARMv5_ONLY
+ emit_shlimm(rs,24,rt);
+ emit_sarimm(rt,24,rt);
+ #else
+ assem_debug("sxtb %s,%s\n",regname[rt],regname[rs]);
+ output_w32(0xe6af0070|rd_rn_rm(rt,0,rs));
+ #endif
+}
+
void emit_shl(u_int rs,u_int shift,u_int rt)
{
assert(rs<16);
{
u_int armval;
if(genimm(imm,&armval)) {
- assem_debug("cmp %s,$%d\n",regname[rs],imm);
+ assem_debug("cmp %s,#%d\n",regname[rs],imm);
output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
}else if(genimm(-imm,&armval)) {
- assem_debug("cmn %s,$%d\n",regname[rs],imm);
+ assem_debug("cmn %s,#%d\n",regname[rs],imm);
output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
}else if(imm>0) {
assert(imm<65536);
}
void emit_callreg(u_int r)
{
- assem_debug("call *%%%s\n",regname[r]);
- assert(0);
+ assert(r<15);
+ assem_debug("blx %s\n",regname[r]);
+ output_w32(0xe12fff30|r);
}
void emit_jmpreg(u_int r)
{
assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
}
+void emit_ldrcc_dualindexed(int rs1, int rs2, int rt)
+{
+ assem_debug("ldrcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
+ output_w32(0x37900000|rd_rn_rm(rt,rs1,rs2));
+}
+void emit_ldrccb_dualindexed(int rs1, int rs2, int rt)
+{
+ assem_debug("ldrccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
+ output_w32(0x37d00000|rd_rn_rm(rt,rs1,rs2));
+}
+void emit_ldrccsb_dualindexed(int rs1, int rs2, int rt)
+{
+ assem_debug("ldrccsb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
+ output_w32(0x319000d0|rd_rn_rm(rt,rs1,rs2));
+}
+void emit_ldrcch_dualindexed(int rs1, int rs2, int rt)
+{
+ assem_debug("ldrcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
+ output_w32(0x319000b0|rd_rn_rm(rt,rs1,rs2));
+}
+void emit_ldrccsh_dualindexed(int rs1, int rs2, int rt)
+{
+ assem_debug("ldrccsh %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
+ output_w32(0x319000f0|rd_rn_rm(rt,rs1,rs2));
+}
void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
{
if(map<0) emit_readword_indexed(addr, rs, rt);
}
}
}
+void emit_strcc_dualindexed(int rs1, int rs2, int rt)
+{
+ assem_debug("strcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
+ output_w32(0x37800000|rd_rn_rm(rt,rs1,rs2));
+}
+void emit_strccb_dualindexed(int rs1, int rs2, int rt)
+{
+ assem_debug("strccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
+ output_w32(0x37c00000|rd_rn_rm(rt,rs1,rs2));
+}
+void emit_strcch_dualindexed(int rs1, int rs2, int rt)
+{
+ assem_debug("strcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
+ output_w32(0x318000b0|rd_rn_rm(rt,rs1,rs2));
+}
void emit_writeword(int rt, int addr)
{
u_int offset = addr-(u_int)&dynarec_local;
#include "pcsxmem_inline.c"
#endif
+// trashes r2
+static void pass_args(int a0, int a1)
+{
+ if(a0==1&&a1==0) {
+ // must swap
+ emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
+ }
+ else if(a0!=0&&a1==0) {
+ emit_mov(a1,1);
+ if (a0>=0) emit_mov(a0,0);
+ }
+ else {
+ if(a0>=0&&a0!=0) emit_mov(a0,0);
+ if(a1>=0&&a1!=1) emit_mov(a1,1);
+ }
+}
+
do_readstub(int n)
{
assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
rt=get_reg(i_regmap,rt1[i]);
}
assert(rs>=0);
+#ifdef PCSX
+ int r,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0;
+ reglist|=(1<<rs);
+ for(r=0;r<=12;r++) {
+ if(((1<<r)&0x13ff)&&((1<<r)®list)==0) {
+ temp=r; break;
+ }
+ }
+ if(rt>=0)
+ reglist&=~(1<<rt);
+ if(temp==-1) {
+ save_regs(reglist);
+ regs_saved=1;
+ temp=(rs==0)?2:0;
+ }
+ if((regs_saved||(reglist&2)==0)&&temp!=1&&rs!=1)
+ temp2=1;
+ emit_readword((int)&mem_rtab,temp);
+ emit_shrimm(rs,12,temp2);
+ emit_readword_dualindexedx4(temp,temp2,temp2);
+ emit_lsls_imm(temp2,1,temp2);
+ if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
+ switch(type) {
+ case LOADB_STUB: emit_ldrccsb_dualindexed(temp2,rs,rt); break;
+ case LOADBU_STUB: emit_ldrccb_dualindexed(temp2,rs,rt); break;
+ case LOADH_STUB: emit_ldrccsh_dualindexed(temp2,rs,rt); break;
+ case LOADHU_STUB: emit_ldrcch_dualindexed(temp2,rs,rt); break;
+ case LOADW_STUB: emit_ldrcc_dualindexed(temp2,rs,rt); break;
+ }
+ }
+ if(regs_saved) {
+ restore_jump=(int)out;
+ emit_jcc(0); // jump to reg restore
+ }
+ else
+ emit_jcc(stubs[n][2]); // return address
+
+ if(!regs_saved)
+ save_regs(reglist);
+ int handler=0;
+ if(type==LOADB_STUB||type==LOADBU_STUB)
+ handler=(int)jump_handler_read8;
+ if(type==LOADH_STUB||type==LOADHU_STUB)
+ handler=(int)jump_handler_read16;
+ if(type==LOADW_STUB)
+ handler=(int)jump_handler_read32;
+ assert(handler!=0);
+ pass_args(rs,temp2);
+ int cc=get_reg(i_regmap,CCREG);
+ if(cc<0)
+ emit_loadreg(CCREG,2);
+ emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*stubs[n][6]+2,2);
+ emit_call(handler);
+ if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
+ switch(type) {
+ case LOADB_STUB: emit_signextend8(0,rt); break;
+ case LOADBU_STUB: emit_andimm(0,0xff,rt); break;
+ case LOADH_STUB: emit_signextend16(0,rt); break;
+ case LOADHU_STUB: emit_andimm(0,0xffff,rt); break;
+ case LOADW_STUB: if(rt!=0) emit_mov(0,rt); break;
+ }
+ }
+ if(restore_jump)
+ set_jump_target(restore_jump,(int)out);
+ restore_regs(reglist);
+ emit_jmp(stubs[n][2]); // return address
+#else // !PCSX
if(addr<0) addr=rt;
if(addr<0&&itype[i]!=C1LS&&itype[i]!=C2LS&&itype[i]!=LOADLR) addr=get_reg(i_regmap,-1);
assert(addr>=0);
}
}
emit_jmp(stubs[n][2]); // return address
+#endif // !PCSX
}
+#ifdef PCSX
+// return memhandler, or get directly accessable address and return 0
+u_int get_direct_memhandler(void *table,u_int addr,int type,u_int *addr_host)
+{
+ u_int l1,l2=0;
+ l1=((u_int *)table)[addr>>12];
+ if((l1&(1<<31))==0) {
+ u_int v=l1<<1;
+ *addr_host=v+addr;
+ return 0;
+ }
+ else {
+ l1<<=1;
+ if(type==LOADB_STUB||type==LOADBU_STUB||type==STOREB_STUB)
+ l2=((u_int *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
+ else if(type==LOADH_STUB||type==LOADHU_STUB||type==STOREH_STUB)
+ l2=((u_int *)l1)[0x1000/4 + (addr&0xfff)/2];
+ else
+ l2=((u_int *)l1)[(addr&0xfff)/4];
+ if((l2&(1<<31))==0) {
+ u_int v=l2<<1;
+ *addr_host=v+(addr&0xfff);
+ return 0;
+ }
+ return l2<<1;
+ }
+}
+#endif
+
inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
{
int rs=get_reg(regmap,target);
int rt=get_reg(regmap,target);
if(rs<0) rs=get_reg(regmap,-1);
assert(rs>=0);
+#ifdef PCSX
+ u_int handler,host_addr=0;
+ if(pcsx_direct_read(type,addr,target?rs:-1,rt))
+ return;
+ handler=get_direct_memhandler(mem_rtab,addr,type,&host_addr);
+ if (handler==0) {
+ if(rt<0)
+ return;
+ if(target==0||addr!=host_addr)
+ emit_movimm(host_addr,rs);
+ switch(type) {
+ case LOADB_STUB: emit_movsbl_indexed(0,rs,rt); break;
+ case LOADBU_STUB: emit_movzbl_indexed(0,rs,rt); break;
+ case LOADH_STUB: emit_movswl_indexed(0,rs,rt); break;
+ case LOADHU_STUB: emit_movzwl_indexed(0,rs,rt); break;
+ case LOADW_STUB: emit_readword_indexed(0,rs,rt); break;
+ default: assert(0);
+ }
+ return;
+ }
+
+ // call a memhandler
+ if(rt>=0)
+ reglist&=~(1<<rt);
+ save_regs(reglist);
+ if(target==0)
+ emit_movimm(addr,0);
+ else if(rs!=0)
+ emit_mov(rs,0);
+ int cc=get_reg(regmap,CCREG);
+ if(cc<0)
+ emit_loadreg(CCREG,2);
+ emit_readword((int)&last_count,3);
+ emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
+ emit_add(2,3,3);
+ emit_writeword(3,(int)&Count);
+
+ int offset=(int)handler-(int)out-8;
+ if(offset<-33554432||offset>=33554432) {
+ // unreachable memhandler, a plugin func perhaps
+ emit_movimm(handler,1);
+ emit_callreg(1);
+ }
+ else
+ emit_call(handler);
+ if(rt>=0) {
+ switch(type) {
+ case LOADB_STUB: emit_signextend8(0,rt); break;
+ case LOADBU_STUB: emit_andimm(0,0xff,rt); break;
+ case LOADH_STUB: emit_signextend16(0,rt); break;
+ case LOADHU_STUB: emit_andimm(0,0xffff,rt); break;
+ case LOADW_STUB: if(rt!=0) emit_mov(0,rt); break;
+ default: assert(0);
+ }
+ }
+ restore_regs(reglist);
+#else // if !PCSX
int ftable=0;
if(type==LOADB_STUB||type==LOADBU_STUB)
ftable=(int)readmemb;
ftable=(int)readmemd;
#endif
assert(ftable!=0);
-#ifdef PCSX
- if(pcsx_direct_read(type,addr,target?rs:-1,rt))
- return;
-#endif
if(target==0)
emit_movimm(addr,rs);
emit_writeword(rs,(int)&address);
//emit_pusha();
save_regs(reglist);
+#ifndef PCSX
+ if((signed int)addr>=(signed int)0xC0000000) {
+ // Theoretically we can have a pagefault here, if the TLB has never
+ // been enabled and the address is outside the range 80000000..BFFFFFFF
+ // Write out the registers so the pagefault can be handled. This is
+ // a very rare case and likely represents a bug.
+ int ds=regmap!=regs[i].regmap;
+ if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
+ if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
+ else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty);
+ }
+#endif
//emit_shrimm(rs,16,1);
int cc=get_reg(regmap,CCREG);
if(cc<0) {
if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
}
}
+#endif // !PCSX
}
do_writestub(int n)
}
assert(rs>=0);
assert(rt>=0);
+#ifdef PCSX
+ int rtmp,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0,ra;
+ int reglist2=reglist|(1<<rs)|(1<<rt);
+ for(rtmp=0;rtmp<=12;rtmp++) {
+ if(((1<<rtmp)&0x13ff)&&((1<<rtmp)®list2)==0) {
+ temp=rtmp; break;
+ }
+ }
+ if(temp==-1) {
+ save_regs(reglist);
+ regs_saved=1;
+ for(rtmp=0;rtmp<=3;rtmp++)
+ if(rtmp!=rs&&rtmp!=rt)
+ {temp=rtmp;break;}
+ }
+ if((regs_saved||(reglist2&8)==0)&&temp!=3&&rs!=3&&rt!=3)
+ temp2=3;
+ emit_readword((int)&mem_wtab,temp);
+ emit_shrimm(rs,12,temp2);
+ emit_readword_dualindexedx4(temp,temp2,temp2);
+ emit_lsls_imm(temp2,1,temp2);
+ switch(type) {
+ case STOREB_STUB: emit_strccb_dualindexed(temp2,rs,rt); break;
+ case STOREH_STUB: emit_strcch_dualindexed(temp2,rs,rt); break;
+ case STOREW_STUB: emit_strcc_dualindexed(temp2,rs,rt); break;
+ default: assert(0);
+ }
+ if(regs_saved) {
+ restore_jump=(int)out;
+ emit_jcc(0); // jump to reg restore
+ }
+ else
+ emit_jcc(stubs[n][2]); // return address (invcode check)
+
+ if(!regs_saved)
+ save_regs(reglist);
+ int handler=0;
+ switch(type) {
+ case STOREB_STUB: handler=(int)jump_handler_write8; break;
+ case STOREH_STUB: handler=(int)jump_handler_write16; break;
+ case STOREW_STUB: handler=(int)jump_handler_write32; break;
+ }
+ assert(handler!=0);
+ pass_args(rs,rt);
+ if(temp2!=3)
+ emit_mov(temp2,3);
+ int cc=get_reg(i_regmap,CCREG);
+ if(cc<0)
+ emit_loadreg(CCREG,2);
+ emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*stubs[n][6]+2,2);
+ // returns new cycle_count
+ emit_call(handler);
+ emit_addimm(0,-CLOCK_DIVIDER*stubs[n][6]-2,cc<0?2:cc);
+ if(cc<0)
+ emit_storereg(CCREG,2);
+ if(restore_jump)
+ set_jump_target(restore_jump,(int)out);
+ restore_regs(reglist);
+ ra=stubs[n][2];
+ if(!restore_jump) ra+=4*3; // skip invcode check
+ emit_jmp(ra);
+#else // if !PCSX
if(addr<0) addr=get_reg(i_regmap,-1);
assert(addr>=0);
int ftable=0;
// emit_loadreg(CCREG,cc);
//}
emit_jmp(stubs[n][2]); // return address
+#endif // !PCSX
}
inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
assert(rs>=0);
assert(rt>=0);
#ifdef PCSX
+ u_int handler,host_addr=0;
if(pcsx_direct_write(type,addr,rs,rt,regmap))
return;
-#endif
+ handler=get_direct_memhandler(mem_wtab,addr,type,&host_addr);
+ if (handler==0) {
+ if(target==0||addr!=host_addr)
+ emit_movimm(host_addr,rs);
+ switch(type) {
+ case STOREB_STUB: emit_writebyte_indexed(rt,0,rs); break;
+ case STOREH_STUB: emit_writehword_indexed(rt,0,rs); break;
+ case STOREW_STUB: emit_writeword_indexed(rt,0,rs); break;
+ default: assert(0);
+ }
+ return;
+ }
+
+ // call a memhandler
+ save_regs(reglist);
+ pass_args(target!=0?rs:-1,rt);
+ if(target==0)
+ emit_movimm(addr,0);
+ int cc=get_reg(regmap,CCREG);
+ if(cc<0)
+ emit_loadreg(CCREG,2);
+ emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
+ emit_movimm(handler,3);
+ // returns new cycle_count
+ emit_call((int)jump_handler_write_h);
+ emit_addimm(0,-CLOCK_DIVIDER*(adj+1),cc<0?2:cc);
+ if(cc<0)
+ emit_storereg(CCREG,2);
+ restore_regs(reglist);
+#else // if !pcsx
int ftable=0;
if(type==STOREB_STUB)
ftable=(int)writememb;
}
//emit_pusha();
save_regs(reglist);
+#ifndef PCSX
+ // rearmed note: load_all_consts prevents BIOS boot, some bug?
+ if((signed int)addr>=(signed int)0xC0000000) {
+ // Theoretically we can have a pagefault here, if the TLB has never
+ // been enabled and the address is outside the range 80000000..BFFFFFFF
+ // Write out the registers so the pagefault can be handled. This is
+ // a very rare case and likely represents a bug.
+ int ds=regmap!=regs[i].regmap;
+ if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
+ if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
+ else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty);
+ }
+#endif
//emit_shrimm(rs,16,1);
int cc=get_reg(regmap,CCREG);
if(cc<0) {
}
//emit_popa();
restore_regs(reglist);
+#endif
}
do_unalignedwritestub(int n)
reglist|=(1<<addr);
reglist&=~(1<<temp2);
+#if 1
+ // don't bother with it and call write handler
+ save_regs(reglist);
+ pass_args(addr,rt);
+ int cc=get_reg(i_regmap,CCREG);
+ if(cc<0)
+ emit_loadreg(CCREG,2);
+ emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*stubs[n][6]+2,2);
+ emit_call((int)(opcode[i]==0x2a?jump_handle_swl:jump_handle_swr));
+ emit_addimm(0,-CLOCK_DIVIDER*stubs[n][6]-2,cc<0?2:cc);
+ if(cc<0)
+ emit_storereg(CCREG,2);
+ restore_regs(reglist);
+ emit_jmp(stubs[n][2]); // return address
+#else
emit_andimm(addr,0xfffffffc,temp2);
emit_writeword(temp2,(int)&address);
}
restore_regs(reglist);
emit_jmp(stubs[n][2]); // return address
+#endif
}
void printregs(int edi,int esi,int ebp,int esp,int b,int d,int c,int a)
}
}
}
+
+#ifdef PCSX
+static void speculate_mov(int rs,int rt)
+{
+ if(rt!=0) {
+ smrv_strong_next|=1<<rt;
+ smrv[rt]=smrv[rs];
+ }
+}
+
+static void speculate_mov_weak(int rs,int rt)
+{
+ if(rt!=0) {
+ smrv_weak_next|=1<<rt;
+ smrv[rt]=smrv[rs];
+ }
+}
+
+static void speculate_register_values(int i)
+{
+ if(i==0) {
+ memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
+ // gp,sp are likely to stay the same throughout the block
+ smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
+ smrv_weak_next=~smrv_strong_next;
+ //printf(" llr %08x\n", smrv[4]);
+ }
+ smrv_strong=smrv_strong_next;
+ smrv_weak=smrv_weak_next;
+ switch(itype[i]) {
+ case ALU:
+ if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
+ else if((smrv_strong>>rs2[i])&1) speculate_mov(rs2[i],rt1[i]);
+ else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
+ else if((smrv_weak>>rs2[i])&1) speculate_mov_weak(rs2[i],rt1[i]);
+ else {
+ smrv_strong_next&=~(1<<rt1[i]);
+ smrv_weak_next&=~(1<<rt1[i]);
+ }
+ break;
+ case SHIFTIMM:
+ smrv_strong_next&=~(1<<rt1[i]);
+ smrv_weak_next&=~(1<<rt1[i]);
+ // fallthrough
+ case IMM16:
+ if(rt1[i]&&is_const(®s[i],rt1[i])) {
+ int value,hr=get_reg(regs[i].regmap,rt1[i]);
+ if(hr>=0) {
+ if(get_final_value(hr,i,&value))
+ smrv[rt1[i]]=value;
+ else smrv[rt1[i]]=constmap[i][hr];
+ smrv_strong_next|=1<<rt1[i];
+ }
+ }
+ else {
+ if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
+ else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
+ }
+ break;
+ case LOAD:
+ if(start<0x2000&&(rt1[i]==26||(smrv[rt1[i]]>>24)==0xa0)) {
+ // special case for BIOS
+ smrv[rt1[i]]=0xa0000000;
+ smrv_strong_next|=1<<rt1[i];
+ break;
+ }
+ // fallthrough
+ case SHIFT:
+ case LOADLR:
+ case MOV:
+ smrv_strong_next&=~(1<<rt1[i]);
+ smrv_weak_next&=~(1<<rt1[i]);
+ break;
+ case COP0:
+ case COP2:
+ if(opcode2[i]==0||opcode2[i]==2) { // MFC/CFC
+ smrv_strong_next&=~(1<<rt1[i]);
+ smrv_weak_next&=~(1<<rt1[i]);
+ }
+ break;
+ case C2LS:
+ if (opcode[i]==0x32) { // LWC2
+ smrv_strong_next&=~(1<<rt1[i]);
+ smrv_weak_next&=~(1<<rt1[i]);
+ }
+ break;
+ }
+#if 0
+ int r=4;
+ printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
+ ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
+#endif
+}
+
+enum {
+ MTYPE_8000 = 0,
+ MTYPE_8020,
+ MTYPE_0000,
+ MTYPE_A000,
+ MTYPE_1F80,
+};
+
+static int get_ptr_mem_type(u_int a)
+{
+ if(a < 0x00200000) {
+ if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
+ // return wrong, must use memhandler for BIOS self-test to pass
+ // 007 does similar stuff from a00 mirror, weird stuff
+ return MTYPE_8000;
+ return MTYPE_0000;
+ }
+ if(0x1f800000 <= a && a < 0x1f801000)
+ return MTYPE_1F80;
+ if(0x80200000 <= a && a < 0x80800000)
+ return MTYPE_8020;
+ if(0xa0000000 <= a && a < 0xa0200000)
+ return MTYPE_A000;
+ return MTYPE_8000;
+}
+#endif
+
+static int emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override)
+{
+ int jaddr,type=0;
+
+#ifdef PCSX
+ int mr=rs1[i];
+ if(((smrv_strong|smrv_weak)>>mr)&1) {
+ type=get_ptr_mem_type(smrv[mr]);
+ //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
+ }
+ else {
+ // use the mirror we are running on
+ type=get_ptr_mem_type(start);
+ //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
+ }
+
+ if(type==MTYPE_8020) { // RAM 80200000+ mirror
+ emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
+ addr=*addr_reg_override=HOST_TEMPREG;
+ type=0;
+ }
+ else if(type==MTYPE_0000) { // RAM 0 mirror
+ emit_orimm(addr,0x80000000,HOST_TEMPREG);
+ addr=*addr_reg_override=HOST_TEMPREG;
+ type=0;
+ }
+ else if(type==MTYPE_A000) { // RAM A mirror
+ emit_andimm(addr,~0x20000000,HOST_TEMPREG);
+ addr=*addr_reg_override=HOST_TEMPREG;
+ type=0;
+ }
+ else if(type==MTYPE_1F80) { // scratchpad
+ emit_addimm(addr,-0x1f800000,HOST_TEMPREG);
+ emit_cmpimm(HOST_TEMPREG,0x1000);
+ jaddr=(int)out;
+ emit_jc(0);
+ }
+#endif
+
+ if(type==0)
+ {
+ emit_cmpimm(addr,RAM_SIZE);
+ jaddr=(int)out;
+ #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
+ // Hint to branch predictor that the branch is unlikely to be taken
+ if(rs1[i]>=28)
+ emit_jno_unlikely(0);
+ else
+ #endif
+ emit_jno(0);
+ }
+
+ return jaddr;
+}
+
#define shift_assemble shift_assemble_arm
void loadlr_assemble_arm(int i,struct regstat *i_regs)
int s,th,tl,temp,temp2,addr,map=-1;
int offset;
int jaddr=0;
- int memtarget,c=0;
+ int memtarget=0,c=0;
+ int fastload_reg_override=0;
u_int hr,reglist=0;
th=get_reg(i_regs->regmap,rt1[i]|64);
tl=get_reg(i_regs->regmap,rt1[i]);
else addr=s;
if(s>=0) {
c=(i_regs->wasconst>>s)&1;
- memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
- if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
+ if(c) {
+ memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
+ if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
+ }
}
if(!using_tlb) {
if(!c) {
}else{
emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
}
- emit_cmpimm(addr,RAM_SIZE);
- jaddr=(int)out;
- emit_jno(0);
+ jaddr=emit_fastpath_cmp_jump(i,temp2,&fastload_reg_override);
}
else {
if (opcode[i]==0x22||opcode[i]==0x26) {
}
map=get_reg(i_regs->regmap,TLREG);
assert(map>=0);
+ reglist&=~(1<<map);
map=do_tlb_r(addr,temp2,map,0,a,c?-1:temp,c,constmap[i][s]+offset);
if(c) {
if (opcode[i]==0x22||opcode[i]==0x26) {
}
if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
if(!c||memtarget) {
+ int a=temp2;
+ if(fastload_reg_override) a=fastload_reg_override;
//emit_readword_indexed((int)rdram-0x80000000,temp2,temp2);
- emit_readword_indexed_tlb(0,temp2,map,temp2);
+ emit_readword_indexed_tlb(0,a,map,temp2);
if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
}
else
//emit_storereg(rt1[i],tl); // DEBUG
}
if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
- // FIXME: little endian
+ // FIXME: little endian, fastload_reg_override
int temp2h=get_reg(i_regs->regmap,FTEMP|64);
if(!c||memtarget) {
//if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
signed char temp=get_reg(i_regs->regmap,-1);
u_int c2op=source[i]&0x3f;
u_int hr,reglist=0;
+ int need_flags;
for(hr=0;hr<HOST_REGS;hr++) {
if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
}
emit_addimm(cc,gte_cycletab[c2op]/2,cc); // XXX: could just adjust ccadj?
emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0); // cop2 regs
emit_writeword(1,(int)&psxRegs.code);
- emit_call((int)gte_handlers[c2op]);
+ need_flags=!(gte_unneeded[i+1]>>63); // +1 because of how liveness detection works
+ assem_debug("gte unneeded %016llx, need_flags %d\n",gte_unneeded[i+1],need_flags);
+#ifdef ARMv5_ONLY
+ // let's take more risk here
+ need_flags=need_flags&>e_reads_flags;
+#endif
+ emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op]));
}
if(i>=slen-1||itype[i+1]!=C2OP)
assert(quotient>=0);
assert(remainder>=0);
emit_movs(d1,remainder);
- emit_negmi(remainder,remainder);
+ emit_movimm(0xffffffff,quotient);
+ emit_negmi(quotient,quotient); // .. quotient and ..
+ emit_negmi(remainder,remainder); // .. remainder for div0 case (will be negated back after jump)
emit_movs(d2,HOST_TEMPREG);
emit_jeq((int)out+52); // Division by zero
emit_negmi(HOST_TEMPREG,HOST_TEMPREG);
signed char remainder=get_reg(i_regs->regmap,HIREG);
assert(quotient>=0);
assert(remainder>=0);
+ emit_mov(d1,remainder);
+ emit_movimm(0xffffffff,quotient); // div0 case
emit_test(d2,d2);
- emit_jeq((int)out+44); // Division by zero
+ emit_jeq((int)out+40); // Division by zero
emit_clz(d2,HOST_TEMPREG);
emit_movimm(1<<31,quotient);
emit_shl(d2,HOST_TEMPREG,d2);
- emit_mov(d1,remainder);
emit_shr(quotient,HOST_TEMPREG,quotient);
emit_cmp(remainder,d2);
emit_subcs(remainder,d2,remainder);
}
}
else // 64-bit
+#ifndef FORCE32
{
if(opcode2[i]==0x1C) // DMULT
{
if(lol>=0) emit_loadreg(LOREG,lol);
}
}
+#else
+ assert(0);
+#endif
}
else
{
if(hr!=EXCLUDE_REG) {
reg=pre[hr];
if(((~u)>>(reg&63))&1) {
- if(reg==entry[hr]||(reg>0&&entry[hr]<0)) {
+ if(reg>0) {
if(((dirty_pre&~dirty)>>hr)&1) {
if(reg>0&®<34) {
emit_storereg(reg,hr);
}
}
}
- else // Check if register moved to a different register
- if((new_hr=get_reg(entry,reg))>=0) {
- if((dirty_pre>>hr)&(~dirty>>new_hr)&1) {
- if(reg>0&®<34) {
- emit_storereg(reg,hr);
- if( ((is32_pre&~uu)>>reg)&1 ) {
- emit_sarimm(hr,31,HOST_TEMPREG);
- emit_storereg(reg|64,HOST_TEMPREG);
- }
- }
- else if(reg>=64) {
- emit_storereg(reg,hr);
- }
- }
- }
}
}
}
notaz.gp2x.de / pcsx_rearmed.git / blobdiff