drc: allow translation cache in data segment

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / assem_arm.h

diff --git a/libpcsxcore/new_dynarec/assem_arm.h b/libpcsxcore/new_dynarec/assem_arm.h
index 917d276..7ed8caf 100644 (file)
--- a/libpcsxcore/new_dynarec/assem_arm.h
+++ b/libpcsxcore/new_dynarec/assem_arm.h
@@ -22,6 +22,10 @@
 //#undef USE_MINI_HT
 #endif
 
+#ifndef __ANDROID__
+#define BASE_ADDR_FIXED 1
+#endif
+
 #ifdef FORCE32
 #define REG_SHIFT 2
 #else
@@ -54,8 +58,16 @@
 
 extern char *invc_ptr;
 
-#define BASE_ADDR 0x1000000 // Code generator target address
 #define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
 
+// Code generator target address
+#ifdef BASE_ADDR_FIXED
+// "round" address helpful for debug
+#define BASE_ADDR 0x1000000
+#else
+extern char translation_cache[1 << TARGET_SIZE_2];
+#define BASE_ADDR translation_cache
+#endif
+
 // This is defined in linkage_arm.s, but gcc -O3 likes this better
 #define rdram ((unsigned int *)0x80000000)