fully reinit drc on change

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / emu_if.c

diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c
index 38d9492..02e108f 100644 (file)
--- a/libpcsxcore/new_dynarec/emu_if.c
+++ b/libpcsxcore/new_dynarec/emu_if.c
@@ -110,6 +110,8 @@ void pcsx_mtc0(u32 reg, u32 val)
        evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
        MTC0(reg, val);
        gen_interupt();
+       if (Cause & Status & 0x0300) // possible sw irq
+               pending_exception = 1;
 }
 
 void pcsx_mtc0_ds(u32 reg, u32 val)
@@ -208,13 +210,13 @@ const uint64_t gte_reg_reads[64] = {
        [GTE_OP]    = GCBITS3(0,2,4)       | GDBITS3(9,10,11),
        [GTE_DPCS]  = GCBITS3(21,22,23)    | GDBITS4(6,8,21,22),
        [GTE_INTPL] = GCBITS3(21,22,23)    | GDBITS7(6,8,9,10,11,21,22),
-       [GTE_MVMVA] = 0x00ffffff00000000ll | GDBITS6(0,1,2,3,4,5), // XXX: maybe decode further?
-       [GTE_NCDS]  = 0x00ffff0000000000ll | GDBITS5(0,1,6,21,22),
-       [GTE_CDP]   = 0x00fff00000000000ll | GDBITS7(6,8,9,10,11,21,22),
+       [GTE_MVMVA] = 0x00ffffff00000000ll | GDBITS9(0,1,2,3,4,5,9,10,11), // XXX: maybe decode further?
+       [GTE_NCDS]  = 0x00ffff0000000000ll | GDBITS6(0,1,6,8,21,22),
+       [GTE_CDP]   = 0x00ffe00000000000ll | GDBITS7(6,8,9,10,11,21,22),
        [GTE_NCDT]  = 0x00ffff0000000000ll | GDBITS8(0,1,2,3,4,5,6,8),
-       [GTE_NCCS]  = 0x00ffff0000000000ll | GDBITS6(0,1,6,8,21,22),
+       [GTE_NCCS]  = 0x001fff0000000000ll | GDBITS5(0,1,6,21,22),
        [GTE_CC]    = 0x001fe00000000000ll | GDBITS6(6,9,10,11,21,22),
-       [GTE_NCS]   = 0x001fff0000000000ll | GDBITS4(0,1,21,22),
+       [GTE_NCS]   = 0x001fff0000000000ll | GDBITS5(0,1,6,21,22),
        [GTE_NCT]   = 0x001fff0000000000ll | GDBITS7(0,1,2,3,4,5,6),
        [GTE_SQR]   =                        GDBITS3(9,10,11),
        [GTE_DCPL]  = GCBITS3(21,22,23)    | GDBITS7(6,8,9,10,11,21,22),
@@ -266,9 +268,9 @@ static int ari64_init()
                if (psxCP2[i] != psxNULL)
                        gte_handlers[i] = psxCP2[i];
 
-#if !defined(DRC_DBG)
-#ifdef __arm__
+#if defined(__arm__) && !defined(DRC_DBG)
        gte_handlers[0x06] = gteNCLIP_arm;
+#ifdef HAVE_ARMV5
        gte_handlers_nf[0x01] = gteRTPS_nf_arm;
        gte_handlers_nf[0x30] = gteRTPT_nf_arm;
 #endif
@@ -342,6 +344,7 @@ static void ari64_clear(u32 addr, u32 size)
 static void ari64_shutdown()
 {
        new_dynarec_cleanup();
+       new_dyna_pcsx_mem_shutdown();
 }
 
 extern void intExecute();
@@ -356,7 +359,7 @@ extern void intExecuteBlockT();
 R3000Acpu psxRec = {
        ari64_init,
        ari64_reset,
-#if defined(__arm__)
+#ifndef DRC_DISABLE
        ari64_execute,
        ari64_execute_until,
 #else
@@ -373,7 +376,7 @@ void do_insn_trace() {}
 void do_insn_cmp() {}
 #endif
 
-#if defined(__x86_64__) || defined(__i386__)
+#ifdef DRC_DISABLE
 unsigned int address;
 int pending_exception, stop;
 unsigned int next_interupt;
@@ -383,7 +386,7 @@ int new_dynarec_hacks;
 void *psxH_ptr;
 void *zeromem_ptr;
 u8 zero_mem[0x1000];
-void new_dynarec_init() {}
+void new_dynarec_init() { (void)ari64_execute; }
 void new_dyna_start() {}
 void new_dynarec_cleanup() {}
 void new_dynarec_clear_full() {}
@@ -392,6 +395,7 @@ void invalidate_block(unsigned int block) {}
 void new_dyna_pcsx_mem_init(void) {}
 void new_dyna_pcsx_mem_reset(void) {}
 void new_dyna_pcsx_mem_load_state(void) {}
+void new_dyna_pcsx_mem_shutdown(void) {}
 #endif
 
 #ifdef DRC_DBG