#include "../cdrom.h"
#include "../psxdma.h"
#include "../mdec.h"
+#include "../gte_arm.h"
#include "../gte_neon.h"
+#define FLAGLESS
+#include "../gte.h"
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
// from interpreter
extern void MTC0(int reg, u32 val);
-void pcsx_mtc0(u32 reg)
+void pcsx_mtc0(u32 reg, u32 val)
{
- evprintf("MTC0 %d #%x @%08x %u\n", reg, readmem_word, psxRegs.pc, psxRegs.cycle);
- MTC0(reg, readmem_word);
+ evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
+ MTC0(reg, val);
gen_interupt();
}
-void pcsx_mtc0_ds(u32 reg)
+void pcsx_mtc0_ds(u32 reg, u32 val)
{
- evprintf("MTC0 %d #%x @%08x %u\n", reg, readmem_word, psxRegs.pc, psxRegs.cycle);
- MTC0(reg, readmem_word);
+ evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
+ MTC0(reg, val);
}
void new_dyna_save(void)
int i;
for (i = 0; i < PSXINT_COUNT; i++)
event_cycles[i] = psxRegs.intCycle[i].sCycle + psxRegs.intCycle[i].cycle;
+
+ new_dyna_pcsx_mem_load_state();
}
+/* GTE stuff */
void *gte_handlers[64];
+void *gte_handlers_nf[64] = {
+ NULL , gteRTPS_nf , NULL , NULL , NULL , NULL , gteNCLIP_nf, NULL , // 00
+ NULL , NULL , NULL , NULL , gteOP_nf , NULL , NULL , NULL , // 08
+ gteDPCS_nf, gteINTPL_nf, gteMVMVA_nf, gteNCDS_nf, gteCDP_nf, NULL , gteNCDT_nf , NULL , // 10
+ NULL , NULL , NULL , gteNCCS_nf, gteCC_nf , NULL , gteNCS_nf , NULL , // 18
+ gteNCT_nf , NULL , NULL , NULL , NULL , NULL , NULL , NULL , // 20
+ gteSQR_nf , gteDCPL_nf , gteDPCT_nf , NULL , NULL , gteAVSZ3_nf, gteAVSZ4_nf, NULL , // 28
+ gteRTPT_nf, NULL , NULL , NULL , NULL , NULL , NULL , NULL , // 30
+ NULL , NULL , NULL , NULL , NULL , gteGPF_nf , gteGPL_nf , gteNCCT_nf, // 38
+};
+
+const char *gte_regnames[64] = {
+ NULL , "RTPS" , NULL , NULL , NULL , NULL , "NCLIP", NULL , // 00
+ NULL , NULL , NULL , NULL , "OP" , NULL , NULL , NULL , // 08
+ "DPCS", "INTPL", "MVMVA", "NCDS", "CDP", NULL , "NCDT" , NULL , // 10
+ NULL , NULL , NULL , "NCCS", "CC" , NULL , "NCS" , NULL , // 18
+ "NCT" , NULL , NULL , NULL , NULL , NULL , NULL , NULL , // 20
+ "SQR" , "DCPL" , "DPCT" , NULL , NULL , "AVSZ3", "AVSZ4", NULL , // 28
+ "RTPT", NULL , NULL , NULL , NULL , NULL , NULL , NULL , // 30
+ NULL , NULL , NULL , NULL , NULL , "GPF" , "GPL" , "NCCT", // 38
+};
+
/* from gte.txt.. not sure if this is any good. */
const char gte_cycletab[64] = {
/* 1 2 3 4 5 6 7 8 9 a b c d e f */
23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 5, 39,
};
+#define GCBIT(x) \
+ (1ll << (32+x))
+#define GDBIT(x) \
+ (1ll << (x))
+#define GCBITS3(b0,b1,b2) \
+ (GCBIT(b0) | GCBIT(b1) | GCBIT(b2))
+#define GDBITS2(b0,b1) \
+ (GDBIT(b0) | GDBIT(b1))
+#define GDBITS3(b0,b1,b2) \
+ (GDBITS2(b0,b1) | GDBIT(b2))
+#define GDBITS4(b0,b1,b2,b3) \
+ (GDBITS3(b0,b1,b2) | GDBIT(b3))
+#define GDBITS5(b0,b1,b2,b3,b4) \
+ (GDBITS4(b0,b1,b2,b3) | GDBIT(b4))
+#define GDBITS6(b0,b1,b2,b3,b4,b5) \
+ (GDBITS5(b0,b1,b2,b3,b4) | GDBIT(b5))
+#define GDBITS7(b0,b1,b2,b3,b4,b5,b6) \
+ (GDBITS6(b0,b1,b2,b3,b4,b5) | GDBIT(b6))
+#define GDBITS8(b0,b1,b2,b3,b4,b5,b6,b7) \
+ (GDBITS7(b0,b1,b2,b3,b4,b5,b6) | GDBIT(b7))
+#define GDBITS9(b0,b1,b2,b3,b4,b5,b6,b7,b8) \
+ (GDBITS8(b0,b1,b2,b3,b4,b5,b6,b7) | GDBIT(b8))
+#define GDBITS10(b0,b1,b2,b3,b4,b5,b6,b7,b8,b9) \
+ (GDBITS9(b0,b1,b2,b3,b4,b5,b6,b7,b8) | GDBIT(b9))
+
+const uint64_t gte_reg_reads[64] = {
+ [GTE_RTPS] = 0x1f0000ff00000000ll | GDBITS7(0,1,13,14,17,18,19),
+ [GTE_NCLIP] = GDBITS3(12,13,14),
+ [GTE_OP] = GCBITS3(0,2,4) | GDBITS3(9,10,11),
+ [GTE_DPCS] = GCBITS3(21,22,23) | GDBITS4(6,8,21,22),
+ [GTE_INTPL] = GCBITS3(21,22,23) | GDBITS7(6,8,9,10,11,21,22),
+ [GTE_MVMVA] = 0x00ffffff00000000ll | GDBITS6(0,1,2,3,4,5), // XXX: maybe decode further?
+ [GTE_NCDS] = 0x00ffff0000000000ll | GDBITS5(0,1,6,21,22),
+ [GTE_CDP] = 0x00fff00000000000ll | GDBITS7(6,8,9,10,11,21,22),
+ [GTE_NCDT] = 0x00ffff0000000000ll | GDBITS8(0,1,2,3,4,5,6,8),
+ [GTE_NCCS] = 0x00ffff0000000000ll | GDBITS6(0,1,6,8,21,22),
+ [GTE_CC] = 0x001fe00000000000ll | GDBITS6(6,9,10,11,21,22),
+ [GTE_NCS] = 0x001fff0000000000ll | GDBITS4(0,1,21,22),
+ [GTE_NCT] = 0x001fff0000000000ll | GDBITS7(0,1,2,3,4,5,6),
+ [GTE_SQR] = GDBITS3(9,10,11),
+ [GTE_DCPL] = GCBITS3(21,22,23) | GDBITS7(6,8,9,10,11,21,22),
+ [GTE_DPCT] = GCBITS3(21,22,23) | GDBITS4(8,20,21,22),
+ [GTE_AVSZ3] = GCBIT(29) | GDBITS3(17,18,19),
+ [GTE_AVSZ4] = GCBIT(30) | GDBITS4(16,17,18,19),
+ [GTE_RTPT] = 0x1f0000ff00000000ll | GDBITS7(0,1,2,3,4,5,19),
+ [GTE_GPF] = GDBITS7(6,8,9,10,11,21,22),
+ [GTE_GPL] = GDBITS10(6,8,9,10,11,21,22,25,26,27),
+ [GTE_NCCT] = 0x001fff0000000000ll | GDBITS7(0,1,2,3,4,5,6),
+};
+
+// note: this excludes gteFLAG that is always written to
+const uint64_t gte_reg_writes[64] = {
+ [GTE_RTPS] = 0x0f0f7f00ll,
+ [GTE_NCLIP] = GDBIT(24),
+ [GTE_OP] = GDBITS6(9,10,11,25,26,27),
+ [GTE_DPCS] = GDBITS9(9,10,11,20,21,22,25,26,27),
+ [GTE_INTPL] = GDBITS9(9,10,11,20,21,22,25,26,27),
+ [GTE_MVMVA] = GDBITS6(9,10,11,25,26,27),
+ [GTE_NCDS] = GDBITS9(9,10,11,20,21,22,25,26,27),
+ [GTE_CDP] = GDBITS9(9,10,11,20,21,22,25,26,27),
+ [GTE_NCDT] = GDBITS9(9,10,11,20,21,22,25,26,27),
+ [GTE_NCCS] = GDBITS9(9,10,11,20,21,22,25,26,27),
+ [GTE_CC] = GDBITS9(9,10,11,20,21,22,25,26,27),
+ [GTE_NCS] = GDBITS9(9,10,11,20,21,22,25,26,27),
+ [GTE_NCT] = GDBITS9(9,10,11,20,21,22,25,26,27),
+ [GTE_SQR] = GDBITS6(9,10,11,25,26,27),
+ [GTE_DCPL] = GDBITS9(9,10,11,20,21,22,25,26,27),
+ [GTE_DPCT] = GDBITS9(9,10,11,20,21,22,25,26,27),
+ [GTE_AVSZ3] = GDBITS2(7,24),
+ [GTE_AVSZ4] = GDBITS2(7,24),
+ [GTE_RTPT] = 0x0f0f7f00ll,
+ [GTE_GPF] = GDBITS9(9,10,11,20,21,22,25,26,27),
+ [GTE_GPL] = GDBITS9(9,10,11,20,21,22,25,26,27),
+ [GTE_NCCT] = GDBITS9(9,10,11,20,21,22,25,26,27),
+};
+
static int ari64_init()
{
extern void (*psxCP2[64])();
for (i = 0; i < ARRAY_SIZE(gte_handlers); i++)
if (psxCP2[i] != psxNULL)
gte_handlers[i] = psxCP2[i];
-#ifndef DRC_DBG
+
+#if !defined(DRC_DBG)
+#ifdef __arm__
+ gte_handlers[0x06] = gteNCLIP_arm;
+ gte_handlers_nf[0x01] = gteRTPS_nf_arm;
+ gte_handlers_nf[0x30] = gteRTPT_nf_arm;
+#endif
#ifdef __ARM_NEON__
- gte_handlers[0x01] = gteRTPS_neon;
- gte_handlers[0x30] = gteRTPT_neon;
- gte_handlers[0x12] = gteMVMVA_neon;
- gte_handlers[0x06] = gteNCLIP_neon;
+ // compiler's _nf version is still a lot slower than neon
+ // _nf_arm RTPS is roughly the same, RTPT slower
+ gte_handlers[0x01] = gte_handlers_nf[0x01] = gteRTPS_neon;
+ gte_handlers[0x30] = gte_handlers_nf[0x30] = gteRTPT_neon;
+#endif
#endif
+#ifdef DRC_DBG
+ memcpy(gte_handlers_nf, gte_handlers, sizeof(gte_handlers_nf));
#endif
psxH_ptr = psxH;
+ zeromem_ptr = zero_mem;
return 0;
}
#endif
#if defined(__x86_64__) || defined(__i386__)
-unsigned int address, readmem_word, word;
-unsigned short hword;
-unsigned char byte;
+unsigned int address;
int pending_exception, stop;
unsigned int next_interupt;
+int new_dynarec_did_compile;
+int cycle_multiplier;
+int new_dynarec_hacks;
void *psxH_ptr;
+void *zeromem_ptr;
+u8 zero_mem[0x1000];
void new_dynarec_init() {}
void new_dyna_start() {}
void new_dynarec_cleanup() {}
void invalidate_block(unsigned int block) {}
void new_dyna_pcsx_mem_init(void) {}
void new_dyna_pcsx_mem_reset(void) {}
+void new_dyna_pcsx_mem_load_state(void) {}
#endif
#ifdef DRC_DBG
notaz.gp2x.de / pcsx_rearmed.git / blobdiff