gte: split arm code for pollux, generate flagless handlers

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / emu_if.h

diff --git a/libpcsxcore/new_dynarec/emu_if.h b/libpcsxcore/new_dynarec/emu_if.h
index f5e4b55..e16cca5 100644 (file)
--- a/libpcsxcore/new_dynarec/emu_if.h
+++ b/libpcsxcore/new_dynarec/emu_if.h
@@ -1,5 +1,10 @@
+#include "new_dynarec.h"
 #include "../r3000a.h"
 
+#ifndef __ARM_ARCH_7A__
+#define ARMv5_ONLY
+#endif
+
 extern char invalid_code[0x100000];
 
 /* weird stuff */
@@ -13,13 +18,20 @@ extern int reg[];
 extern int hi, lo;
 
 /* same as psxRegs.CP0.n.* */
+extern int reg_cop0[];
 #define Status   psxRegs.CP0.n.Status
 #define Cause    psxRegs.CP0.n.Cause
 #define EPC      psxRegs.CP0.n.EPC
 #define BadVAddr psxRegs.CP0.n.BadVAddr
 #define Context  psxRegs.CP0.n.Context
 #define EntryHi  psxRegs.CP0.n.EntryHi
-#define Count    psxRegs.CP0.n.Count
+#define Count    psxRegs.cycle // psxRegs.CP0.n.Count
+
+/* COP2/GTE */
+extern int reg_cop2d[], reg_cop2c[];
+extern void *gte_handlers[64];
+extern void *gte_handlers_nf[64];
+extern const char gte_cycletab[64];
 
 /* dummy */
 extern int FCR0, FCR31;
@@ -38,10 +50,18 @@ extern unsigned int word;   /* write */
 extern unsigned short hword;
 extern unsigned char byte;
 
-/* cycles */
+extern void *psxH_ptr;
+
+// same as invalid_code, just a region for ram write checks (inclusive)
+extern u32 inv_code_start, inv_code_end;
+
+/* cycles/irqs */
 extern unsigned int next_interupt;
+extern int pending_exception;
 
 /* called by drc */
-void MFC0();
-void MTC0();
+void pcsx_mtc0(u32 reg);
+void pcsx_mtc0_ds(u32 reg);
 
+/* misc */
+extern void (*psxHLEt[])();