/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Mupen64plus - new_dynarec.c *
- * Copyright (C) 2009-2010 Ari64 *
+ * Copyright (C) 2009-2011 Ari64 *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
#include <stdlib.h>
#include <stdint.h> //include for uint64_t
#include <assert.h>
+#include <errno.h>
+#include <sys/mman.h>
+#ifdef __MACH__
+#include <libkern/OSCacheControl.h>
+#endif
+#ifdef _3DS
+#include <3ds_utils.h>
+#endif
+#ifdef VITA
+#include <psp2/kernel/sysmem.h>
+static int sceBlock;
+#endif
+#include "new_dynarec_config.h"
+#include "../psxhle.h" //emulator interface
#include "emu_if.h" //emulator interface
-#include <sys/mman.h>
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
+#endif
+
+//#define DISASM
+//#define assem_debug printf
+//#define inv_debug printf
+#define assem_debug(...)
+#define inv_debug(...)
#ifdef __i386__
#include "assem_x86.h"
#define MAXBLOCK 4096
#define MAX_OUTPUT_BLOCK_SIZE 262144
-#define CLOCK_DIVIDER 2
+
+// stubs
+enum stub_type {
+ CC_STUB = 1,
+ FP_STUB = 2,
+ LOADB_STUB = 3,
+ LOADH_STUB = 4,
+ LOADW_STUB = 5,
+ LOADD_STUB = 6,
+ LOADBU_STUB = 7,
+ LOADHU_STUB = 8,
+ STOREB_STUB = 9,
+ STOREH_STUB = 10,
+ STOREW_STUB = 11,
+ STORED_STUB = 12,
+ STORELR_STUB = 13,
+ INVCODE_STUB = 14,
+};
struct regstat
{
uint64_t uu;
u_int wasconst;
u_int isconst;
- uint64_t constmap[HOST_REGS];
+ u_int loadedconst; // host regs that have constants loaded
+ u_int waswritten; // MIPS regs that were used as store base before
};
+// note: asm depends on this layout
struct ll_entry
{
u_int vaddr;
- u_int reg32;
+ u_int reg_sv_flags;
void *addr;
struct ll_entry *next;
};
- u_int start;
- u_int *source;
- u_int pagelimit;
- char insn[MAXBLOCK][10];
- u_char itype[MAXBLOCK];
- u_char opcode[MAXBLOCK];
- u_char opcode2[MAXBLOCK];
- u_char bt[MAXBLOCK];
- u_char rs1[MAXBLOCK];
- u_char rs2[MAXBLOCK];
- u_char rt1[MAXBLOCK];
- u_char rt2[MAXBLOCK];
- u_char us1[MAXBLOCK];
- u_char us2[MAXBLOCK];
- u_char dep1[MAXBLOCK];
- u_char dep2[MAXBLOCK];
- u_char lt1[MAXBLOCK];
- int imm[MAXBLOCK];
- u_int ba[MAXBLOCK];
- char likely[MAXBLOCK];
- char is_ds[MAXBLOCK];
- char ooo[MAXBLOCK];
- uint64_t unneeded_reg[MAXBLOCK];
- uint64_t unneeded_reg_upper[MAXBLOCK];
- uint64_t branch_unneeded_reg[MAXBLOCK];
- uint64_t branch_unneeded_reg_upper[MAXBLOCK];
- uint64_t p32[MAXBLOCK];
- uint64_t pr32[MAXBLOCK];
- signed char regmap_pre[MAXBLOCK][HOST_REGS];
- signed char regmap[MAXBLOCK][HOST_REGS];
- signed char regmap_entry[MAXBLOCK][HOST_REGS];
- uint64_t constmap[MAXBLOCK][HOST_REGS];
- struct regstat regs[MAXBLOCK];
- struct regstat branch_regs[MAXBLOCK];
- signed char minimum_free_regs[MAXBLOCK];
- u_int needed_reg[MAXBLOCK];
- uint64_t requires_32bit[MAXBLOCK];
- u_int wont_dirty[MAXBLOCK];
- u_int will_dirty[MAXBLOCK];
- int ccadj[MAXBLOCK];
- int slen;
- u_int instr_addr[MAXBLOCK];
- u_int link_addr[MAXBLOCK][3];
- int linkcount;
- u_int stubs[MAXBLOCK*3][8];
- int stubcount;
- u_int literals[1024][2];
- int literalcount;
- int is_delayslot;
- int cop1_usable;
+struct ht_entry
+{
+ u_int vaddr[2];
+ void *tcaddr[2];
+};
+
+struct code_stub
+{
+ enum stub_type type;
+ void *addr;
+ void *retaddr;
+ u_int a;
+ uintptr_t b;
+ uintptr_t c;
+ u_int d;
+ u_int e;
+};
+
+struct link_entry
+{
+ void *addr;
+ u_int target;
+ u_int ext;
+};
+
+ // used by asm:
u_char *out;
- struct ll_entry *jump_in[4096];
- struct ll_entry *jump_out[4096];
+ struct ht_entry hash_table[65536] __attribute__((aligned(16)));
+ struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
struct ll_entry *jump_dirty[4096];
- u_int hash_table[65536][4] __attribute__((aligned(16)));
- char shadow[1048576] __attribute__((aligned(16)));
- void *copy;
- int expirep;
-#ifndef PCSX
- u_int using_tlb;
+
+ static struct ll_entry *jump_out[4096];
+ static u_int start;
+ static u_int *source;
+ static char insn[MAXBLOCK][10];
+ static u_char itype[MAXBLOCK];
+ static u_char opcode[MAXBLOCK];
+ static u_char opcode2[MAXBLOCK];
+ static u_char bt[MAXBLOCK];
+ static u_char rs1[MAXBLOCK];
+ static u_char rs2[MAXBLOCK];
+ static u_char rt1[MAXBLOCK];
+ static u_char rt2[MAXBLOCK];
+ static u_char us1[MAXBLOCK];
+ static u_char us2[MAXBLOCK];
+ static u_char dep1[MAXBLOCK];
+ static u_char dep2[MAXBLOCK];
+ static u_char lt1[MAXBLOCK];
+ static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
+ static uint64_t gte_rt[MAXBLOCK];
+ static uint64_t gte_unneeded[MAXBLOCK];
+ static u_int smrv[32]; // speculated MIPS register values
+ static u_int smrv_strong; // mask or regs that are likely to have correct values
+ static u_int smrv_weak; // same, but somewhat less likely
+ static u_int smrv_strong_next; // same, but after current insn executes
+ static u_int smrv_weak_next;
+ static int imm[MAXBLOCK];
+ static u_int ba[MAXBLOCK];
+ static char likely[MAXBLOCK];
+ static char is_ds[MAXBLOCK];
+ static char ooo[MAXBLOCK];
+ static uint64_t unneeded_reg[MAXBLOCK];
+ static uint64_t unneeded_reg_upper[MAXBLOCK];
+ static uint64_t branch_unneeded_reg[MAXBLOCK];
+ static uint64_t branch_unneeded_reg_upper[MAXBLOCK];
+ static signed char regmap_pre[MAXBLOCK][HOST_REGS];
+ static uint64_t current_constmap[HOST_REGS];
+ static uint64_t constmap[MAXBLOCK][HOST_REGS];
+ static struct regstat regs[MAXBLOCK];
+ static struct regstat branch_regs[MAXBLOCK];
+ static signed char minimum_free_regs[MAXBLOCK];
+ static u_int needed_reg[MAXBLOCK];
+ static u_int wont_dirty[MAXBLOCK];
+ static u_int will_dirty[MAXBLOCK];
+ static int ccadj[MAXBLOCK];
+ static int slen;
+ static void *instr_addr[MAXBLOCK];
+ static struct link_entry link_addr[MAXBLOCK];
+ static int linkcount;
+ static struct code_stub stubs[MAXBLOCK*3];
+ static int stubcount;
+ static u_int literals[1024][2];
+ static int literalcount;
+ static int is_delayslot;
+ static int cop1_usable;
+ static char shadow[1048576] __attribute__((aligned(16)));
+ static void *copy;
+ static int expirep;
+ static u_int stop_after_jal;
+#ifndef RAM_FIXED
+ static u_int ram_offset;
#else
- static const u_int using_tlb=0;
+ static const u_int ram_offset=0;
#endif
- static u_int sp_in_mirror;
- u_int stop_after_jal;
+
+ int new_dynarec_hacks;
+ int new_dynarec_did_compile;
extern u_char restore_candidate[512];
extern int cycle_count;
#define CSREG 35 // Coprocessor status
#define CCREG 36 // Cycle count
#define INVCP 37 // Pointer to invalid_code
-#define MMREG 38 // Pointer to memory_map
+//#define MMREG 38 // Pointer to memory_map
#define ROREG 39 // ram offset (if rdram!=0x80000000)
#define TEMPREG 40
#define FTEMP 40 // FPU temporary register
#define PTEMP 41 // Prefetch temporary register
-#define TLREG 42 // TLB mapping offset
+//#define TLREG 42 // TLB mapping offset
#define RHASH 43 // Return address hash
#define RHTBL 44 // Return address hash table address
#define RTEMP 45 // JR/JALR address register
#define MAXREG 45
#define AGEN1 46 // Address generation temporary register
-#define AGEN2 47 // Address generation temporary register
-#define MGEN1 48 // Maptable address generation temporary register
-#define MGEN2 49 // Maptable address generation temporary register
+//#define AGEN2 47 // Address generation temporary register
+//#define MGEN1 48 // Maptable address generation temporary register
+//#define MGEN2 49 // Maptable address generation temporary register
#define BTREG 50 // Branch target temporary register
/* instruction types */
#define STORE 2 // Store
#define LOADLR 3 // Unaligned load
#define STORELR 4 // Unaligned store
-#define MOV 5 // Move
+#define MOV 5 // Move
#define ALU 6 // Arithmetic/logic
#define MULTDIV 7 // Multiply/divide
#define SHIFT 8 // Shift by register
#define C2OP 29 // Coprocessor 2 operation
#define INTCALL 30// Call interpreter to handle rare corner cases
- /* stubs */
-#define CC_STUB 1
-#define FP_STUB 2
-#define LOADB_STUB 3
-#define LOADH_STUB 4
-#define LOADW_STUB 5
-#define LOADD_STUB 6
-#define LOADBU_STUB 7
-#define LOADHU_STUB 8
-#define STOREB_STUB 9
-#define STOREH_STUB 10
-#define STOREW_STUB 11
-#define STORED_STUB 12
-#define STORELR_STUB 13
-#define INVCODE_STUB 14
-
/* branch codes */
#define TAKEN 1
#define NOTTAKEN 2
void invalidate_block(u_int block);
void invalidate_addr(u_int addr);
void remove_hash(int vaddr);
-void jump_vaddr();
void dyna_linker();
void dyna_linker_ds();
void verify_code();
void cc_interrupt();
void fp_exception();
void fp_exception_ds();
-void jump_syscall();
void jump_syscall_hle();
-void jump_eret();
void jump_hlecall();
void jump_intcall();
void new_dyna_leave();
-// TLB
-void TLBWI_new();
-void TLBWR_new();
-void read_nomem_new();
-void read_nomemb_new();
-void read_nomemh_new();
-void read_nomemd_new();
-void write_nomem_new();
-void write_nomemb_new();
-void write_nomemh_new();
-void write_nomemd_new();
-void write_rdram_new();
-void write_rdramb_new();
-void write_rdramh_new();
-void write_rdramd_new();
-extern u_int memory_map[1048576];
-
// Needed by assembler
-void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
-void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
-void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
-void load_all_regs(signed char i_regmap[]);
-void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
-void load_regs_entry(int t);
-void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
+static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
+static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
+static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
+static void load_all_regs(signed char i_regmap[]);
+static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
+static void load_regs_entry(int t);
+static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
+
+static int verify_dirty(u_int *ptr);
+static int get_final_value(int hr, int i, int *value);
+static void add_stub(enum stub_type type, void *addr, void *retaddr,
+ u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
+static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
+ int i, int addr_reg, struct regstat *i_regs, int ccadj, u_int reglist);
+static void add_to_linker(void *addr, u_int target, int ext);
+
+static void mprotect_w_x(void *start, void *end, int is_x)
+{
+#ifdef NO_WRITE_EXEC
+ #if defined(VITA)
+ // *Open* enables write on all memory that was
+ // allocated by sceKernelAllocMemBlockForVM()?
+ if (is_x)
+ sceKernelCloseVMDomain();
+ else
+ sceKernelOpenVMDomain();
+ #else
+ u_long mstart = (u_long)start & ~4095ul;
+ u_long mend = (u_long)end;
+ if (mprotect((void *)mstart, mend - mstart,
+ PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
+ SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
+ #endif
+#endif
+}
+
+static void start_tcache_write(void *start, void *end)
+{
+ mprotect_w_x(start, end, 0);
+}
+
+static void end_tcache_write(void *start, void *end)
+{
+#ifdef __arm__
+ size_t len = (char *)end - (char *)start;
+ #if defined(__BLACKBERRY_QNX__)
+ msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
+ #elif defined(__MACH__)
+ sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
+ #elif defined(VITA)
+ sceKernelSyncVMDomain(sceBlock, start, len);
+ #elif defined(_3DS)
+ ctr_flush_invalidate_cache();
+ #else
+ __clear_cache(start, end);
+ #endif
+ (void)len;
+#endif
+
+ mprotect_w_x(start, end, 1);
+}
+
+static void *start_block(void)
+{
+ u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
+ if (end > translation_cache + (1<<TARGET_SIZE_2))
+ end = translation_cache + (1<<TARGET_SIZE_2);
+ start_tcache_write(out, end);
+ return out;
+}
-int tracedebug=0;
+static void end_block(void *start)
+{
+ end_tcache_write(start, out);
+}
//#define DEBUG_CYCLE_COUNT 1
-void nullf() {}
-//#define assem_debug printf
-//#define inv_debug printf
-#define assem_debug nullf
-#define inv_debug nullf
+#define NO_CYCLE_PENALTY_THR 12
-static void tlb_hacks()
+int cycle_multiplier; // 100 for 1.0
+
+static int CLOCK_ADJUST(int x)
{
-#ifndef DISABLE_TLB
- // Goldeneye hack
- if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
- {
- u_int addr;
- int n;
- switch (ROM_HEADER->Country_code&0xFF)
- {
- case 0x45: // U
- addr=0x34b30;
- break;
- case 0x4A: // J
- addr=0x34b70;
- break;
- case 0x50: // E
- addr=0x329f0;
- break;
- default:
- // Unknown country code
- addr=0;
- break;
- }
- u_int rom_addr=(u_int)rom;
- #ifdef ROM_COPY
- // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
- // in the lower 4G of memory to use this hack. Copy it if necessary.
- if((void *)rom>(void *)0xffffffff) {
- munmap(ROM_COPY, 67108864);
- if(mmap(ROM_COPY, 12582912,
- PROT_READ | PROT_WRITE,
- MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
- -1, 0) <= 0) {printf("mmap() failed\n");}
- memcpy(ROM_COPY,rom,12582912);
- rom_addr=(u_int)ROM_COPY;
- }
- #endif
- if(addr) {
- for(n=0x7F000;n<0x80000;n++) {
- memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
- }
- }
- }
-#endif
+ int s=(x>>31)|1;
+ return (x * cycle_multiplier + s * 50) / 100;
}
static u_int get_page(u_int vaddr)
{
-#ifndef PCSX
- u_int page=(vaddr^0x80000000)>>12;
-#else
u_int page=vaddr&~0xe0000000;
if (page < 0x1000000)
page &= ~0x0e00000; // RAM mirrors
page>>=12;
-#endif
-#ifndef DISABLE_TLB
- if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
-#endif
if(page>2048) page=2048+(page&2047);
return page;
}
+// no virtual mem in PCSX
static u_int get_vpage(u_int vaddr)
{
- u_int vpage=(vaddr^0x80000000)>>12;
-#ifndef DISABLE_TLB
- if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
-#endif
- if(vpage>2048) vpage=2048+(vpage&2047);
- return vpage;
+ return get_page(vaddr);
+}
+
+static struct ht_entry *hash_table_get(u_int vaddr)
+{
+ return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
+}
+
+static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
+{
+ ht_bin->vaddr[1] = ht_bin->vaddr[0];
+ ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
+ ht_bin->vaddr[0] = vaddr;
+ ht_bin->tcaddr[0] = tcaddr;
+}
+
+// some messy ari64's code, seems to rely on unsigned 32bit overflow
+static int doesnt_expire_soon(void *tcaddr)
+{
+ u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
+ return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
}
// Get address from virtual address
//printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
head=jump_in[page];
while(head!=NULL) {
- if(head->vaddr==vaddr&&head->reg32==0) {
- //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
- int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
- ht_bin[3]=ht_bin[1];
- ht_bin[2]=ht_bin[0];
- ht_bin[1]=(int)head->addr;
- ht_bin[0]=vaddr;
+ if(head->vaddr==vaddr) {
+ //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr);
+ hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
return head->addr;
}
head=head->next;
}
head=jump_dirty[vpage];
while(head!=NULL) {
- if(head->vaddr==vaddr&&head->reg32==0) {
- //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
+ if(head->vaddr==vaddr) {
+ //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr);
// Don't restore blocks which are about to expire from the cache
- if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
- if(verify_dirty(head->addr)) {
+ if (doesnt_expire_soon(head->addr))
+ if (verify_dirty(head->addr)) {
//printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
invalid_code[vaddr>>12]=0;
- memory_map[vaddr>>12]|=0x40000000;
+ inv_code_start=inv_code_end=~0;
if(vpage<2048) {
-#ifndef DISABLE_TLB
- if(tlb_LUT_r[vaddr>>12]) {
- invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
- memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
- }
-#endif
restore_candidate[vpage>>3]|=1<<(vpage&7);
}
else restore_candidate[page>>3]|=1<<(page&7);
- int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
- if(ht_bin[0]==vaddr) {
- ht_bin[1]=(int)head->addr; // Replace existing entry
- }
+ struct ht_entry *ht_bin = hash_table_get(vaddr);
+ if (ht_bin->vaddr[0] == vaddr)
+ ht_bin->tcaddr[0] = head->addr; // Replace existing entry
else
- {
- ht_bin[3]=ht_bin[1];
- ht_bin[2]=ht_bin[0];
- ht_bin[1]=(int)head->addr;
- ht_bin[0]=vaddr;
- }
+ hash_table_add(ht_bin, vaddr, head->addr);
+
return head->addr;
}
}
void *get_addr_ht(u_int vaddr)
{
//printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
- int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
- if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
- if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
- return get_addr(vaddr);
-}
-
-void *get_addr_32(u_int vaddr,u_int flags)
-{
-#ifdef FORCE32
+ const struct ht_entry *ht_bin = hash_table_get(vaddr);
+ if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
+ if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
return get_addr(vaddr);
-#else
- //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
- int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
- if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
- if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
- u_int page=get_page(vaddr);
- u_int vpage=get_vpage(vaddr);
- struct ll_entry *head;
- head=jump_in[page];
- while(head!=NULL) {
- if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
- //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
- if(head->reg32==0) {
- int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
- if(ht_bin[0]==-1) {
- ht_bin[1]=(int)head->addr;
- ht_bin[0]=vaddr;
- }else if(ht_bin[2]==-1) {
- ht_bin[3]=(int)head->addr;
- ht_bin[2]=vaddr;
- }
- //ht_bin[3]=ht_bin[1];
- //ht_bin[2]=ht_bin[0];
- //ht_bin[1]=(int)head->addr;
- //ht_bin[0]=vaddr;
- }
- return head->addr;
- }
- head=head->next;
- }
- head=jump_dirty[vpage];
- while(head!=NULL) {
- if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
- //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
- // Don't restore blocks which are about to expire from the cache
- if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
- if(verify_dirty(head->addr)) {
- //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
- invalid_code[vaddr>>12]=0;
- memory_map[vaddr>>12]|=0x40000000;
- if(vpage<2048) {
-#ifndef DISABLE_TLB
- if(tlb_LUT_r[vaddr>>12]) {
- invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
- memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
- }
-#endif
- restore_candidate[vpage>>3]|=1<<(vpage&7);
- }
- else restore_candidate[page>>3]|=1<<(page&7);
- if(head->reg32==0) {
- int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
- if(ht_bin[0]==-1) {
- ht_bin[1]=(int)head->addr;
- ht_bin[0]=vaddr;
- }else if(ht_bin[2]==-1) {
- ht_bin[3]=(int)head->addr;
- ht_bin[2]=vaddr;
- }
- //ht_bin[3]=ht_bin[1];
- //ht_bin[2]=ht_bin[0];
- //ht_bin[1]=(int)head->addr;
- //ht_bin[0]=vaddr;
- }
- return head->addr;
- }
- }
- head=head->next;
- }
- //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
- int r=new_recompile_block(vaddr);
- if(r==0) return get_addr(vaddr);
- // Execute in unmapped page, generate pagefault execption
- Status|=2;
- Cause=(vaddr<<31)|0x8;
- EPC=(vaddr&1)?vaddr-5:vaddr;
- BadVAddr=(vaddr&~1);
- Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
- EntryHi=BadVAddr&0xFFFFE000;
- return get_addr_ht(0x80000000);
-#endif
}
void clear_all_regs(signed char regmap[])
for (hr=0;hr<HOST_REGS;hr++) {
if((cur->dirty>>hr)&1) {
reg=cur->regmap[hr];
- if(reg>=64)
+ if(reg>=64)
if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
}
}
for (hr=0;hr<HOST_REGS;hr++) {
if(cur->regmap[hr]==reg) {
cur->isconst|=1<<hr;
- cur->constmap[hr]=value;
+ current_constmap[hr]=value;
}
else if((cur->regmap[hr]^64)==reg) {
cur->isconst|=1<<hr;
- cur->constmap[hr]=value>>32;
+ current_constmap[hr]=value>>32;
}
}
}
int is_const(struct regstat *cur,signed char reg)
{
int hr;
+ if(reg<0) return 0;
if(!reg) return 1;
for (hr=0;hr<HOST_REGS;hr++) {
if((cur->regmap[hr]&63)==reg) {
if(!reg) return 0;
for (hr=0;hr<HOST_REGS;hr++) {
if(cur->regmap[hr]==reg) {
- return cur->constmap[hr];
+ return current_constmap[hr];
}
}
- printf("Unknown constant in r%d\n",reg);
+ SysPrintf("Unknown constant in r%d\n",reg);
exit(1);
}
if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
hsn[FTEMP]=0;
}
- // Don't remove the TLB registers either
- if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
- hsn[TLREG]=0;
- }
// Don't remove the miniht registers
if(itype[i]==UJUMP||itype[i]==RJUMP)
{
int j;
int b=-1;
int rn=10;
- int hr;
- u_char hsn[MAXREG+1];
- int preferred_reg;
-
- memset(hsn,10,sizeof(hsn));
- lsn(hsn,i,&preferred_reg);
-
+
if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
{
if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
}
}
}*/
- for(hr=0;hr<HOST_REGS;hr++) {
- if(hr!=EXCLUDE_REG) {
- if(rn<hsn[hr]) return 1;
- }
- }
+ if(rn<10) return 1;
+ (void)b;
return 0;
}
void alloc_all(struct regstat *cur,int i)
{
int hr;
-
+
for(hr=0;hr<HOST_REGS;hr++) {
if(hr!=EXCLUDE_REG) {
if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
}
}
-
-void div64(int64_t dividend,int64_t divisor)
-{
- lo=dividend/divisor;
- hi=dividend%divisor;
- //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
- // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
-}
-void divu64(uint64_t dividend,uint64_t divisor)
-{
- lo=dividend/divisor;
- hi=dividend%divisor;
- //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
- // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
-}
-
-void mult64(uint64_t m1,uint64_t m2)
-{
- unsigned long long int op1, op2, op3, op4;
- unsigned long long int result1, result2, result3, result4;
- unsigned long long int temp1, temp2, temp3, temp4;
- int sign = 0;
-
- if (m1 < 0)
- {
- op2 = -m1;
- sign = 1 - sign;
- }
- else op2 = m1;
- if (m2 < 0)
- {
- op4 = -m2;
- sign = 1 - sign;
- }
- else op4 = m2;
-
- op1 = op2 & 0xFFFFFFFF;
- op2 = (op2 >> 32) & 0xFFFFFFFF;
- op3 = op4 & 0xFFFFFFFF;
- op4 = (op4 >> 32) & 0xFFFFFFFF;
-
- temp1 = op1 * op3;
- temp2 = (temp1 >> 32) + op1 * op4;
- temp3 = op2 * op3;
- temp4 = (temp3 >> 32) + op2 * op4;
-
- result1 = temp1 & 0xFFFFFFFF;
- result2 = temp2 + (temp3 & 0xFFFFFFFF);
- result3 = (result2 >> 32) + temp4;
- result4 = (result3 >> 32);
-
- lo = result1 | (result2 << 32);
- hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
- if (sign)
- {
- hi = ~hi;
- if (!lo) hi++;
- else lo = ~lo + 1;
- }
-}
-
-void multu64(uint64_t m1,uint64_t m2)
-{
- unsigned long long int op1, op2, op3, op4;
- unsigned long long int result1, result2, result3, result4;
- unsigned long long int temp1, temp2, temp3, temp4;
-
- op1 = m1 & 0xFFFFFFFF;
- op2 = (m1 >> 32) & 0xFFFFFFFF;
- op3 = m2 & 0xFFFFFFFF;
- op4 = (m2 >> 32) & 0xFFFFFFFF;
-
- temp1 = op1 * op3;
- temp2 = (temp1 >> 32) + op1 * op4;
- temp3 = op2 * op3;
- temp4 = (temp3 >> 32) + op2 * op4;
-
- result1 = temp1 & 0xFFFFFFFF;
- result2 = temp2 + (temp3 & 0xFFFFFFFF);
- result3 = (result2 >> 32) + temp4;
- result4 = (result3 >> 32);
-
- lo = result1 | (result2 << 32);
- hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
-
- //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
- // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
-}
-
-uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
-{
- if(bits) {
- original<<=64-bits;
- original>>=64-bits;
- loaded<<=bits;
- original|=loaded;
- }
- else original=loaded;
- return original;
-}
-uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
-{
- if(bits^56) {
- original>>=64-(bits^56);
- original<<=64-(bits^56);
- loaded>>=bits^56;
- original|=loaded;
- }
- else original=loaded;
- return original;
-}
-
#ifdef __i386__
#include "assem_x86.c"
#endif
new_entry=malloc(sizeof(struct ll_entry));
assert(new_entry!=NULL);
new_entry->vaddr=vaddr;
- new_entry->reg32=0;
+ new_entry->reg_sv_flags=0;
new_entry->addr=addr;
new_entry->next=*head;
*head=new_entry;
}
-// Add virtual address mapping for 32-bit compiled block
-void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
+void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
{
ll_add(head,vaddr,addr);
-#ifndef FORCE32
- (*head)->reg32=reg32;
-#endif
+ (*head)->reg_sv_flags=reg_sv_flags;
}
// Check if an address is already compiled
// but don't return addresses which are about to expire from the cache
void *check_addr(u_int vaddr)
{
- u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
- if(ht_bin[0]==vaddr) {
- if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
- if(isclean(ht_bin[1])) return (void *)ht_bin[1];
- }
- if(ht_bin[2]==vaddr) {
- if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
- if(isclean(ht_bin[3])) return (void *)ht_bin[3];
+ struct ht_entry *ht_bin = hash_table_get(vaddr);
+ size_t i;
+ for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
+ if (ht_bin->vaddr[i] == vaddr)
+ if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
+ if (isclean(ht_bin->tcaddr[i]))
+ return ht_bin->tcaddr[i];
}
u_int page=get_page(vaddr);
struct ll_entry *head;
head=jump_in[page];
- while(head!=NULL) {
- if(head->vaddr==vaddr&&head->reg32==0) {
- if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
+ while (head != NULL) {
+ if (head->vaddr == vaddr) {
+ if (doesnt_expire_soon(head->addr)) {
// Update existing entry with current address
- if(ht_bin[0]==vaddr) {
- ht_bin[1]=(int)head->addr;
+ if (ht_bin->vaddr[0] == vaddr) {
+ ht_bin->tcaddr[0] = head->addr;
return head->addr;
}
- if(ht_bin[2]==vaddr) {
- ht_bin[3]=(int)head->addr;
+ if (ht_bin->vaddr[1] == vaddr) {
+ ht_bin->tcaddr[1] = head->addr;
return head->addr;
}
// Insert into hash table with low priority.
// Don't evict existing entries, as they are probably
// addresses that are being accessed frequently.
- if(ht_bin[0]==-1) {
- ht_bin[1]=(int)head->addr;
- ht_bin[0]=vaddr;
- }else if(ht_bin[2]==-1) {
- ht_bin[3]=(int)head->addr;
- ht_bin[2]=vaddr;
+ if (ht_bin->vaddr[0] == -1) {
+ ht_bin->vaddr[0] = vaddr;
+ ht_bin->tcaddr[0] = head->addr;
+ }
+ else if (ht_bin->vaddr[1] == -1) {
+ ht_bin->vaddr[1] = vaddr;
+ ht_bin->tcaddr[1] = head->addr;
}
return head->addr;
}
void remove_hash(int vaddr)
{
//printf("remove hash: %x\n",vaddr);
- int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
- if(ht_bin[2]==vaddr) {
- ht_bin[2]=ht_bin[3]=-1;
+ struct ht_entry *ht_bin = hash_table_get(vaddr);
+ if (ht_bin->vaddr[1] == vaddr) {
+ ht_bin->vaddr[1] = -1;
+ ht_bin->tcaddr[1] = NULL;
}
- if(ht_bin[0]==vaddr) {
- ht_bin[0]=ht_bin[2];
- ht_bin[1]=ht_bin[3];
- ht_bin[2]=ht_bin[3]=-1;
+ if (ht_bin->vaddr[0] == vaddr) {
+ ht_bin->vaddr[0] = ht_bin->vaddr[1];
+ ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
+ ht_bin->vaddr[1] = -1;
+ ht_bin->tcaddr[1] = NULL;
}
}
-void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
+void ll_remove_matching_addrs(struct ll_entry **head,uintptr_t addr,int shift)
{
struct ll_entry *next;
while(*head) {
- if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
- ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
+ if(((uintptr_t)((*head)->addr)>>shift)==(addr>>shift) ||
+ ((uintptr_t)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
{
- inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
+ inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr);
remove_hash((*head)->vaddr);
next=(*head)->next;
free(*head);
{
struct ll_entry *cur;
struct ll_entry *next;
- if(cur=*head) {
+ if((cur=*head)) {
*head=0;
while(cur) {
next=cur->next;
}
// Dereference the pointers and remove if it matches
-void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
+static void ll_kill_pointers(struct ll_entry *head,uintptr_t addr,int shift)
{
while(head) {
- int ptr=get_pointer(head->addr);
- inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
+ uintptr_t ptr = (uintptr_t)get_pointer(head->addr);
+ inv_debug("EXP: Lookup pointer to %lx at %p (%x)\n",(long)ptr,head->addr,head->vaddr);
if(((ptr>>shift)==(addr>>shift)) ||
(((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
{
- inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
- u_int host_addr=(u_int)kill_pointer(head->addr);
+ inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
+ void *host_addr=find_extjump_insn(head->addr);
#ifdef __arm__
- needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
+ mark_clear_cache(host_addr);
#endif
+ set_jump_target(host_addr, head->addr);
}
head=head->next;
}
head=jump_out[page];
jump_out[page]=0;
while(head!=NULL) {
- inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
- u_int host_addr=(u_int)kill_pointer(head->addr);
+ inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
+ void *host_addr=find_extjump_insn(head->addr);
#ifdef __arm__
- needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
+ mark_clear_cache(host_addr);
#endif
+ set_jump_target(host_addr, head->addr);
next=head->next;
free(head);
head=next;
}
}
-void invalidate_block(u_int block)
+
+static void invalidate_block_range(u_int block, u_int first, u_int last)
{
u_int page=get_page(block<<12);
- u_int vpage=get_vpage(block<<12);
- inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
- //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
- u_int first,last;
- first=last=page;
- struct ll_entry *head;
- head=jump_dirty[vpage];
- //printf("page=%d vpage=%d\n",page,vpage);
- while(head!=NULL) {
- u_int start,end;
- if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
- get_bounds((int)head->addr,&start,&end);
- //printf("start: %x end: %x\n",start,end);
- if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
- if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
- if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
- if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
- }
- }
-#ifndef DISABLE_TLB
- if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
- if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
- if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
- if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
- }
- }
-#endif
- }
- head=head->next;
- }
//printf("first=%d last=%d\n",first,last);
invalidate_page(page);
assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
#ifdef __arm__
do_clear_cache();
#endif
-
+
// Don't trap writes
invalid_code[block]=1;
-#ifdef PCSX
- invalid_code[((u_int)0x80000000>>12)|page]=1;
-#endif
-#ifndef DISABLE_TLB
- // If there is a valid TLB entry for this page, remove write protect
- if(tlb_LUT_w[block]) {
- assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
- // CHECK: Is this right?
- memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
- u_int real_block=tlb_LUT_w[block]>>12;
- invalid_code[real_block]=1;
- if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
- }
- else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
-#endif
#ifdef USE_MINI_HT
memset(mini_ht,-1,sizeof(mini_ht));
#endif
}
+
+void invalidate_block(u_int block)
+{
+ u_int page=get_page(block<<12);
+ u_int vpage=get_vpage(block<<12);
+ inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
+ //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
+ u_int first,last;
+ first=last=page;
+ struct ll_entry *head;
+ head=jump_dirty[vpage];
+ //printf("page=%d vpage=%d\n",page,vpage);
+ while(head!=NULL) {
+ u_int start,end;
+ if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
+ get_bounds(head->addr,&start,&end);
+ //printf("start: %x end: %x\n",start,end);
+ if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
+ if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
+ if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
+ if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
+ }
+ }
+ }
+ head=head->next;
+ }
+ invalidate_block_range(block,first,last);
+}
+
void invalidate_addr(u_int addr)
{
+ //static int rhits;
+ // this check is done by the caller
+ //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
+ u_int page=get_vpage(addr);
+ if(page<2048) { // RAM
+ struct ll_entry *head;
+ u_int addr_min=~0, addr_max=0;
+ u_int mask=RAM_SIZE-1;
+ u_int addr_main=0x80000000|(addr&mask);
+ int pg1;
+ inv_code_start=addr_main&~0xfff;
+ inv_code_end=addr_main|0xfff;
+ pg1=page;
+ if (pg1>0) {
+ // must check previous page too because of spans..
+ pg1--;
+ inv_code_start-=0x1000;
+ }
+ for(;pg1<=page;pg1++) {
+ for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
+ u_int start,end;
+ get_bounds(head->addr,&start,&end);
+ if(ram_offset) {
+ start-=ram_offset;
+ end-=ram_offset;
+ }
+ if(start<=addr_main&&addr_main<end) {
+ if(start<addr_min) addr_min=start;
+ if(end>addr_max) addr_max=end;
+ }
+ else if(addr_main<start) {
+ if(start<inv_code_end)
+ inv_code_end=start-1;
+ }
+ else {
+ if(end>inv_code_start)
+ inv_code_start=end;
+ }
+ }
+ }
+ if (addr_min!=~0) {
+ inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
+ inv_code_start=inv_code_end=~0;
+ invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
+ return;
+ }
+ else {
+ inv_code_start=(addr&~mask)|(inv_code_start&mask);
+ inv_code_end=(addr&~mask)|(inv_code_end&mask);
+ inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
+ return;
+ }
+ }
invalidate_block(addr>>12);
}
+
// This is called when loading a save state.
// Anything could have changed, so invalidate everything.
void invalidate_all_pages()
{
- u_int page,n;
+ u_int page;
for(page=0;page<4096;page++)
invalidate_page(page);
for(page=0;page<1048576;page++)
restore_candidate[(page&2047)>>3]|=1<<(page&7);
restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
}
- #ifdef __arm__
- __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
- #endif
#ifdef USE_MINI_HT
memset(mini_ht,-1,sizeof(mini_ht));
#endif
- #ifndef DISABLE_TLB
- // TLB
- for(page=0;page<0x100000;page++) {
- if(tlb_LUT_r[page]) {
- memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
- if(!tlb_LUT_w[page]||!invalid_code[page])
- memory_map[page]|=0x40000000; // Write protect
- }
- else memory_map[page]=-1;
- if(page==0x80000) page=0xC0000;
- }
- tlb_hacks();
- #endif
}
// Add an entry to jump_out after making a link
void add_link(u_int vaddr,void *src)
{
u_int page=get_page(vaddr);
- inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
+ inv_debug("add_link: %p -> %x (%d)\n",src,vaddr,page);
+ int *ptr=(int *)(src+4);
+ assert((*ptr&0x0fff0000)==0x059f0000);
+ (void)ptr;
ll_add(jump_out+page,vaddr,src);
- //int ptr=get_pointer(src);
- //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
+ //void *ptr=get_pointer(src);
+ //inv_debug("add_link: Pointer is to %p\n",ptr);
}
// If a code block was found to be unmodified (bit was set in
while(head!=NULL) {
if(!invalid_code[head->vaddr>>12]) {
// Don't restore blocks which are about to expire from the cache
- if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
+ if (doesnt_expire_soon(head->addr)) {
u_int start,end;
- if(verify_dirty((int)head->addr)) {
- //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
+ if(verify_dirty(head->addr)) {
+ //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr);
u_int i;
u_int inv=0;
- get_bounds((int)head->addr,&start,&end);
+ get_bounds(head->addr,&start,&end);
if(start-(u_int)rdram<RAM_SIZE) {
for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
inv|=invalid_code[i];
}
}
- if((signed int)head->vaddr>=(signed int)0xC0000000) {
- u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
- //printf("addr=%x start=%x end=%x\n",addr,start,end);
- if(addr<start||addr>=end) inv=1;
- }
else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
inv=1;
}
if(!inv) {
- void * clean_addr=(void *)get_clean_addr((int)head->addr);
- if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
+ void *clean_addr = get_clean_addr(head->addr);
+ if (doesnt_expire_soon(clean_addr)) {
u_int ppage=page;
-#ifndef DISABLE_TLB
- if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
-#endif
- inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
+ inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr);
//printf("page=%x, addr=%x\n",page,head->vaddr);
//assert(head->vaddr>>12==(page|0x80000));
- ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
- int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
- if(!head->reg32) {
- if(ht_bin[0]==head->vaddr) {
- ht_bin[1]=(int)clean_addr; // Replace existing entry
- }
- if(ht_bin[2]==head->vaddr) {
- ht_bin[3]=(int)clean_addr; // Replace existing entry
- }
- }
+ ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
+ struct ht_entry *ht_bin = hash_table_get(head->vaddr);
+ if (ht_bin->vaddr[0] == head->vaddr)
+ ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
+ if (ht_bin->vaddr[1] == head->vaddr)
+ ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
}
}
}
void shiftimm_alloc(struct regstat *current,int i)
{
- clear_const(current,rs1[i]);
- clear_const(current,rt1[i]);
if(opcode2[i]<=0x3) // SLL/SRL/SRA
{
if(rt1[i]) {
alloc_reg(current,i,rt1[i]);
current->is32|=1LL<<rt1[i];
dirty_reg(current,rt1[i]);
+ if(is_const(current,rs1[i])) {
+ int v=get_const(current,rs1[i]);
+ if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
+ if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
+ if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
+ }
+ else clear_const(current,rt1[i]);
}
}
+ else
+ {
+ clear_const(current,rs1[i]);
+ clear_const(current,rt1[i]);
+ }
+
if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
{
if(rt1[i]) {
//if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
- if(rt1[i]) {
+ if(rt1[i]&&!((current->u>>rt1[i])&1)) {
alloc_reg(current,i,rt1[i]);
- if(get_reg(current->regmap,rt1[i])<0) {
- // dummy load, but we still need a register to calculate the address
- alloc_reg_temp(current,i,-1);
- minimum_free_regs[i]=1;
- }
+ assert(get_reg(current->regmap,rt1[i])>=0);
if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
{
current->is32&=~(1LL<<rt1[i]);
}
else current->is32|=1LL<<rt1[i];
dirty_reg(current,rt1[i]);
- // If using TLB, need a register for pointer to the mapping table
- if(using_tlb) alloc_reg(current,i,TLREG);
// LWL/LWR need a temporary register for the old value
if(opcode[i]==0x22||opcode[i]==0x26)
{
}
else
{
- // Load to r0 (dummy load)
+ // Load to r0 or unneeded register (dummy load)
// but we still need a register to calculate the address
if(opcode[i]==0x22||opcode[i]==0x26)
{
alloc_reg64(current,i,rs2[i]);
if(rs2[i]) alloc_reg(current,i,FTEMP);
}
- // If using TLB, need a register for pointer to the mapping table
- if(using_tlb) alloc_reg(current,i,TLREG);
#if defined(HOST_IMM8)
// On CPUs without 32-bit immediates we need a pointer to invalid_code
else alloc_reg(current,i,INVCP);
if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
alloc_reg64(current,i,FTEMP);
}
- // If using TLB, need a register for pointer to the mapping table
- if(using_tlb) alloc_reg(current,i,TLREG);
#if defined(HOST_IMM8)
// On CPUs without 32-bit immediates we need a pointer to invalid_code
else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
clear_const(current,rt1[i]);
if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
alloc_reg(current,i,FTEMP);
- // If using TLB, need a register for pointer to the mapping table
- if(using_tlb) alloc_reg(current,i,TLREG);
#if defined(HOST_IMM8)
// On CPUs without 32-bit immediates we need a pointer to invalid_code
- else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
+ if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
alloc_reg(current,i,INVCP);
#endif
// We need a temporary register for address generation
case HLECALL:
case SPAN:
assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
- printf("Disabled speculative precompilation\n");
+ SysPrintf("Disabled speculative precompilation\n");
stop_after_jal=1;
break;
case IMM16:
//else ...
}
-add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
+static void add_stub(enum stub_type type, void *addr, void *retaddr,
+ u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
{
- stubs[stubcount][0]=type;
- stubs[stubcount][1]=addr;
- stubs[stubcount][2]=retaddr;
- stubs[stubcount][3]=a;
- stubs[stubcount][4]=b;
- stubs[stubcount][5]=c;
- stubs[stubcount][6]=d;
- stubs[stubcount][7]=e;
+ assert(a < ARRAY_SIZE(stubs));
+ stubs[stubcount].type = type;
+ stubs[stubcount].addr = addr;
+ stubs[stubcount].retaddr = retaddr;
+ stubs[stubcount].a = a;
+ stubs[stubcount].b = b;
+ stubs[stubcount].c = c;
+ stubs[stubcount].d = d;
+ stubs[stubcount].e = e;
stubcount++;
}
+static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
+ int i, int addr_reg, struct regstat *i_regs, int ccadj, u_int reglist)
+{
+ add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
+}
+
// Write out a single register
void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
{
if((dirty>>hr)&1) {
if(regmap[hr]<64) {
emit_storereg(r,hr);
-#ifndef FORCE32
- if((is32>>regmap[hr])&1) {
- emit_sarimm(hr,31,hr);
- emit_storereg(r|64,hr);
- }
-#endif
}else{
emit_storereg(r|64,hr);
}
int mchecksum()
{
- //if(!tracedebug) return 0;
int i;
int sum=0;
for(i=0;i<2097152;i++) {
for(i=0;i<32;i++)
printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
printf("\n");
-#ifndef DISABLE_COP1
- printf("TRACE: ");
- for(i=0;i<32;i++)
- printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
- printf("\n");
-#endif
}
-void enabletrace()
-{
- tracedebug=1;
-}
-
-void memdebug(int i)
-{
- //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
- //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
- //rlist();
- //if(tracedebug) {
- //if(Count>=-2084597794) {
- if((signed int)Count>=-2084597794&&(signed int)Count<0) {
- //if(0) {
- printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
- //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
- //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
- rlist();
- #ifdef __i386__
- printf("TRACE: %x\n",(&i)[-1]);
- #endif
- #ifdef __arm__
- int j;
- printf("TRACE: %x \n",(&j)[10]);
- printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
- #endif
- //fflush(stdout);
- }
- //printf("TRACE: %x\n",(&i)[-1]);
-}
-
-void tlb_debug(u_int cause, u_int addr, u_int iaddr)
-{
- printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
-}
-
-void alu_assemble(int i,struct regstat *i_regs)
+void alu_assemble(int i,struct regstat *i_regs)
{
if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
if(rt1[i]) {
emit_mov(sh,th);
}
}
- if(opcode[i]==0x0d) //ORI
- if(sl<0) {
- emit_orimm(tl,imm[i],tl);
- }else{
- if(!((i_regs->wasconst>>sl)&1))
- emit_orimm(sl,imm[i],tl);
- else
- emit_movimm(constmap[i][sl]|imm[i],tl);
+ if(opcode[i]==0x0d) { // ORI
+ if(sl<0) {
+ emit_orimm(tl,imm[i],tl);
+ }else{
+ if(!((i_regs->wasconst>>sl)&1))
+ emit_orimm(sl,imm[i],tl);
+ else
+ emit_movimm(constmap[i][sl]|imm[i],tl);
+ }
}
- if(opcode[i]==0x0e) //XORI
- if(sl<0) {
- emit_xorimm(tl,imm[i],tl);
- }else{
- if(!((i_regs->wasconst>>sl)&1))
- emit_xorimm(sl,imm[i],tl);
- else
- emit_movimm(constmap[i][sl]^imm[i],tl);
+ if(opcode[i]==0x0e) { // XORI
+ if(sl<0) {
+ emit_xorimm(tl,imm[i],tl);
+ }else{
+ if(!((i_regs->wasconst>>sl)&1))
+ emit_xorimm(sl,imm[i],tl);
+ else
+ emit_movimm(constmap[i][sl]^imm[i],tl);
+ }
}
}
else {
t=get_reg(i_regs->regmap,rt1[i]);
s=get_reg(i_regs->regmap,rs1[i]);
//assert(t>=0);
- if(t>=0){
+ if(t>=0&&!((i_regs->isconst>>t)&1)){
if(rs1[i]==0)
{
emit_zeroreg(t);
{
int s,th,tl,addr,map=-1;
int offset;
- int jaddr=0;
+ void *jaddr=0;
int memtarget=0,c=0;
+ int fastload_reg_override=0;
u_int hr,reglist=0;
th=get_reg(i_regs->regmap,rt1[i]|64);
tl=get_reg(i_regs->regmap,rt1[i]);
c=(i_regs->wasconst>>s)&1;
if (c) {
memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
- if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
}
}
//printf("load_assemble: c=%d\n",c);
- //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
+ //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
// FIXME: Even if the load is a NOP, we should check for pagefaults...
-#ifdef PCSX
- if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
+ if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
||rt1[i]==0) {
// could be FIFO, must perform the read
// ||dummy read
tl=get_reg(i_regs->regmap,-1);
assert(tl>=0);
}
-#endif
if(offset||s<0||c) addr=tl;
else addr=s;
//if(tl<0) tl=get_reg(i_regs->regmap,-1);
if(tl>=0) {
//printf("load_assemble: c=%d\n",c);
- //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
+ //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
reglist&=~(1<<tl);
if(th>=0) reglist&=~(1<<th);
- if(!using_tlb) {
- if(!c) {
- #ifdef RAM_OFFSET
- map=get_reg(i_regs->regmap,ROREG);
- if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
- #endif
-//#define R29_HACK 1
- #ifdef R29_HACK
- // Strmnnrmn's speed hack
- if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
- #endif
- {
- #ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) {
- emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
- emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
- }
- else
- #endif
- emit_cmpimm(addr,RAM_SIZE);
- jaddr=(int)out;
- #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
- // Hint to branch predictor that the branch is unlikely to be taken
- if(rs1[i]>=28)
- emit_jno_unlikely(0);
- else
- #endif
- emit_jno(0);
- }
+ if(!c) {
+ #ifdef RAM_OFFSET
+ map=get_reg(i_regs->regmap,ROREG);
+ if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
+ #endif
+ #ifdef R29_HACK
+ // Strmnnrmn's speed hack
+ if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
+ #endif
+ {
+ jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
}
- }else{ // using tlb
- int x=0;
- if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
- if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
- map=get_reg(i_regs->regmap,TLREG);
- assert(map>=0);
- map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
- do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
+ }
+ else if(ram_offset&&memtarget) {
+ emit_addimm(addr,ram_offset,HOST_TEMPREG);
+ fastload_reg_override=HOST_TEMPREG;
}
int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
if (opcode[i]==0x20) { // LB
#endif
{
//emit_xorimm(addr,3,tl);
- //gen_tlb_addr_r(tl,map);
- //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
+ //emit_movsbl_indexed(rdram-0x80000000,tl,tl);
int x=0,a=tl;
#ifdef BIG_ENDIAN_MIPS
if(!c) emit_xorimm(addr,3,tl);
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
+
emit_movsbl_indexed_tlb(x,a,map,tl);
}
}
if(jaddr)
- add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
+ add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
}
else
inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
//#ifdef
//emit_movswl_indexed_tlb(x,tl,map,tl);
//else
if(map>=0) {
- gen_tlb_addr_r(a,map);
emit_movswl_indexed(x,a,tl);
}else{
- #ifdef RAM_OFFSET
+ #if 1 //def RAM_OFFSET
emit_movswl_indexed(x,a,tl);
#else
- emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
+ emit_movswl_indexed(rdram-0x80000000+x,a,tl);
#endif
}
}
}
if(jaddr)
- add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
+ add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
}
else
inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
if(!c||memtarget) {
if(!dummy) {
int a=addr;
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
- //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
+ if(fastload_reg_override) a=fastload_reg_override;
+ //emit_readword_indexed(rdram-0x80000000,addr,tl);
#ifdef HOST_IMM_ADDR32
if(c)
emit_readword_tlb(constmap[i][s]+offset,map,tl);
emit_readword_indexed_tlb(0,a,map,tl);
}
if(jaddr)
- add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
+ add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
}
else
inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
#endif
{
//emit_xorimm(addr,3,tl);
- //gen_tlb_addr_r(tl,map);
- //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
+ //emit_movzbl_indexed(rdram-0x80000000,tl,tl);
int x=0,a=tl;
#ifdef BIG_ENDIAN_MIPS
if(!c) emit_xorimm(addr,3,tl);
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
+
emit_movzbl_indexed_tlb(x,a,map,tl);
}
}
if(jaddr)
- add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
+ add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
}
else
inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
//#ifdef
//emit_movzwl_indexed_tlb(x,tl,map,tl);
//#else
if(map>=0) {
- gen_tlb_addr_r(a,map);
emit_movzwl_indexed(x,a,tl);
}else{
- #ifdef RAM_OFFSET
+ #if 1 //def RAM_OFFSET
emit_movzwl_indexed(x,a,tl);
#else
- emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
+ emit_movzwl_indexed(rdram-0x80000000+x,a,tl);
#endif
}
}
}
if(jaddr)
- add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
+ add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
}
else
inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
if(!c||memtarget) {
if(!dummy) {
int a=addr;
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
- //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
+ if(fastload_reg_override) a=fastload_reg_override;
+ //emit_readword_indexed(rdram-0x80000000,addr,tl);
#ifdef HOST_IMM_ADDR32
if(c)
emit_readword_tlb(constmap[i][s]+offset,map,tl);
emit_readword_indexed_tlb(0,a,map,tl);
}
if(jaddr)
- add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
+ add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
}
else {
inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
if(!c||memtarget) {
if(!dummy) {
int a=addr;
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
- //gen_tlb_addr_r(tl,map);
- //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
- //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
+ if(fastload_reg_override) a=fastload_reg_override;
+ //if(th>=0) emit_readword_indexed(rdram-0x80000000,addr,th);
+ //emit_readword_indexed(rdram-0x7FFFFFFC,addr,tl);
#ifdef HOST_IMM_ADDR32
if(c)
emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
emit_readdword_indexed_tlb(0,a,map,th,tl);
}
if(jaddr)
- add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
+ add_stub_r(LOADD_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
}
else
inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
}
}
- //emit_storereg(rt1[i],tl); // DEBUG
- //if(opcode[i]==0x23)
- //if(opcode[i]==0x24)
- //if(opcode[i]==0x23||opcode[i]==0x24)
- /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
- {
- //emit_pusha();
- save_regs(0x100f);
- emit_readword((int)&last_count,ECX);
- #ifdef __i386__
- if(get_reg(i_regs->regmap,CCREG)<0)
- emit_loadreg(CCREG,HOST_CCREG);
- emit_add(HOST_CCREG,ECX,HOST_CCREG);
- emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
- emit_writeword(HOST_CCREG,(int)&Count);
- #endif
- #ifdef __arm__
- if(get_reg(i_regs->regmap,CCREG)<0)
- emit_loadreg(CCREG,0);
- else
- emit_mov(HOST_CCREG,0);
- emit_add(0,ECX,0);
- emit_addimm(0,2*ccadj[i],0);
- emit_writeword(0,(int)&Count);
- #endif
- emit_call((int)memdebug);
- //emit_popa();
- restore_regs(0x100f);
- }/**/
}
#ifndef loadlr_assemble
int s,th,tl,map=-1;
int addr,temp;
int offset;
- int jaddr=0,jaddr2,type;
+ void *jaddr=0;
+ enum stub_type type;
int memtarget=0,c=0;
int agr=AGEN1+(i&1);
+ int faststore_reg_override=0;
u_int hr,reglist=0;
th=get_reg(i_regs->regmap,rs2[i]|64);
tl=get_reg(i_regs->regmap,rs2[i]);
c=(i_regs->wasconst>>s)&1;
if(c) {
memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
- if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
}
}
assert(tl>=0);
if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
if(offset||s<0||c) addr=temp;
else addr=s;
- if(!using_tlb) {
- if(!c) {
- #ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) {
- emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
- emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
- }
- else
- #endif
- #ifdef R29_HACK
- // Strmnnrmn's speed hack
- if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
- #endif
- emit_cmpimm(addr,RAM_SIZE);
- #ifdef DESTRUCTIVE_SHIFT
- if(s==addr) emit_mov(s,temp);
- #endif
- #ifdef R29_HACK
- memtarget=1;
- if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
- #endif
- {
- jaddr=(int)out;
- #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
- // Hint to branch predictor that the branch is unlikely to be taken
- if(rs1[i]>=28)
- emit_jno_unlikely(0);
- else
- #endif
- emit_jno(0);
- }
- }
- }else{ // using tlb
- int x=0;
- if (opcode[i]==0x28) x=3; // SB
- if (opcode[i]==0x29) x=2; // SH
- map=get_reg(i_regs->regmap,TLREG);
- assert(map>=0);
- map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
- do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
+ if(!c) {
+ jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
+ }
+ else if(ram_offset&&memtarget) {
+ emit_addimm(addr,ram_offset,HOST_TEMPREG);
+ faststore_reg_override=HOST_TEMPREG;
}
if (opcode[i]==0x28) { // SB
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
- //gen_tlb_addr_w(temp,map);
- //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
+ if(faststore_reg_override) a=faststore_reg_override;
+ //emit_writebyte_indexed(tl,rdram-0x80000000,temp);
emit_writebyte_indexed_tlb(tl,x,a,map,a);
}
type=STOREB_STUB;
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(faststore_reg_override) a=faststore_reg_override;
//#ifdef
//emit_writehword_indexed_tlb(tl,x,temp,map,temp);
//#else
if(map>=0) {
- gen_tlb_addr_w(a,map);
emit_writehword_indexed(tl,x,a);
}else
- emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
+ //emit_writehword_indexed(tl,rdram-0x80000000+x,a);
+ emit_writehword_indexed(tl,x,a);
}
type=STOREH_STUB;
}
if (opcode[i]==0x2B) { // SW
if(!c||memtarget) {
int a=addr;
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
- //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
+ if(faststore_reg_override) a=faststore_reg_override;
+ //emit_writeword_indexed(tl,rdram-0x80000000,addr);
emit_writeword_indexed_tlb(tl,0,a,map,temp);
}
type=STOREW_STUB;
if (opcode[i]==0x3F) { // SD
if(!c||memtarget) {
int a=addr;
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(faststore_reg_override) a=faststore_reg_override;
if(rs2[i]) {
assert(th>=0);
- //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
- //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
+ //emit_writeword_indexed(th,rdram-0x80000000,addr);
+ //emit_writeword_indexed(tl,rdram-0x7FFFFFFC,addr);
emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
}else{
// Store zero
- //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
- //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
+ //emit_writeword_indexed(tl,rdram-0x80000000,temp);
+ //emit_writeword_indexed(tl,rdram-0x7FFFFFFC,temp);
emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
}
}
type=STORED_STUB;
}
- if(!using_tlb) {
+ if(jaddr) {
+ // PCSX store handlers don't check invcode again
+ reglist|=1<<addr;
+ add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
+ jaddr=0;
+ }
+ if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
if(!c||memtarget) {
#ifdef DESTRUCTIVE_SHIFT
// The x86 shift operation is 'destructive'; it overwrites the
assert(ir>=0);
emit_cmpmem_indexedsr12_reg(ir,addr,1);
#else
- emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
+ emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
#endif
#if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
emit_callne(invalidate_addr_reg[addr]);
#else
- jaddr2=(int)out;
+ void *jaddr2 = out;
emit_jne(0);
- add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
+ add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
#endif
}
}
+ u_int addr_val=constmap[i][s]+offset;
if(jaddr) {
- add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
+ add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
} else if(c&&!memtarget) {
- inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
+ inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
+ }
+ // basic current block modification detection..
+ // not looking back as that should be in mips cache already
+ if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
+ SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
+ assert(i_regs->regmap==regs[i].regmap); // not delay slot
+ if(i_regs->regmap==regs[i].regmap) {
+ load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
+ wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
+ emit_movimm(start+i*4+4,0);
+ emit_writeword(0,&pcaddr);
+ emit_jmp(do_interrupt);
+ }
}
- //if(opcode[i]==0x2B || opcode[i]==0x3F)
- //if(opcode[i]==0x2B || opcode[i]==0x28)
- //if(opcode[i]==0x2B || opcode[i]==0x29)
- //if(opcode[i]==0x2B)
- /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
- {
- //emit_pusha();
- save_regs(0x100f);
- emit_readword((int)&last_count,ECX);
- #ifdef __i386__
- if(get_reg(i_regs->regmap,CCREG)<0)
- emit_loadreg(CCREG,HOST_CCREG);
- emit_add(HOST_CCREG,ECX,HOST_CCREG);
- emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
- emit_writeword(HOST_CCREG,(int)&Count);
- #endif
- #ifdef __arm__
- if(get_reg(i_regs->regmap,CCREG)<0)
- emit_loadreg(CCREG,0);
- else
- emit_mov(HOST_CCREG,0);
- emit_add(0,ECX,0);
- emit_addimm(0,2*ccadj[i],0);
- emit_writeword(0,(int)&Count);
- #endif
- emit_call((int)memdebug);
- //emit_popa();
- restore_regs(0x100f);
- }/**/
}
void storelr_assemble(int i,struct regstat *i_regs)
{
int s,th,tl;
int temp;
- int temp2;
+ int temp2=-1;
int offset;
- int jaddr=0,jaddr2;
- int case1,case2,case3;
- int done0,done1,done2;
+ void *jaddr=0;
+ void *case1, *case2, *case3;
+ void *done0, *done1, *done2;
int memtarget=0,c=0;
int agr=AGEN1+(i&1);
u_int hr,reglist=0;
c=(i_regs->isconst>>s)&1;
if(c) {
memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
- if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
}
}
assert(tl>=0);
if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
}
assert(temp>=0);
- if(!using_tlb) {
- if(!c) {
- emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
- if(!offset&&s!=temp) emit_mov(s,temp);
- jaddr=(int)out;
- emit_jno(0);
- }
- else
- {
- if(!memtarget||!rs1[i]) {
- jaddr=(int)out;
- emit_jmp(0);
- }
- }
- #ifdef RAM_OFFSET
- int map=get_reg(i_regs->regmap,ROREG);
- if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
- gen_tlb_addr_w(temp,map);
- #else
- if((u_int)rdram!=0x80000000)
- emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
- #endif
- }else{ // using tlb
- int map=get_reg(i_regs->regmap,TLREG);
- assert(map>=0);
- map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
- if(!c&&!offset&&s>=0) emit_mov(s,temp);
- do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
- if(!jaddr&&!memtarget) {
- jaddr=(int)out;
+ if(!c) {
+ emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
+ if(!offset&&s!=temp) emit_mov(s,temp);
+ jaddr=out;
+ emit_jno(0);
+ }
+ else
+ {
+ if(!memtarget||!rs1[i]) {
+ jaddr=out;
emit_jmp(0);
}
- gen_tlb_addr_w(temp,map);
}
+ #ifdef RAM_OFFSET
+ int map=get_reg(i_regs->regmap,ROREG);
+ if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
+ #else
+ if((u_int)rdram!=0x80000000)
+ emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
+ #endif
if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
temp2=get_reg(i_regs->regmap,FTEMP);
emit_xorimm(temp,3,temp);
#endif
emit_testimm(temp,2);
- case2=(int)out;
+ case2=out;
emit_jne(0);
emit_testimm(temp,1);
- case1=(int)out;
+ case1=out;
emit_jne(0);
// 0
if (opcode[i]==0x2A) { // SWL
emit_writebyte_indexed(tl,3,temp);
if(rs2[i]) emit_shldimm(th,tl,24,temp2);
}
- done0=(int)out;
+ done0=out;
emit_jmp(0);
// 1
- set_jump_target(case1,(int)out);
+ set_jump_target(case1, out);
if (opcode[i]==0x2A) { // SWL
// Write 3 msb into three least significant bytes
if(rs2[i]) emit_rorimm(tl,8,tl);
// Write two lsb into two most significant bytes
emit_writehword_indexed(tl,1,temp);
}
- done1=(int)out;
+ done1=out;
emit_jmp(0);
// 2
- set_jump_target(case2,(int)out);
+ set_jump_target(case2, out);
emit_testimm(temp,1);
- case3=(int)out;
+ case3=out;
emit_jne(0);
if (opcode[i]==0x2A) { // SWL
// Write two msb into two least significant bytes
emit_writehword_indexed(tl,0,temp);
if(rs2[i]) emit_rorimm(tl,24,tl);
}
- done2=(int)out;
+ done2=out;
emit_jmp(0);
// 3
- set_jump_target(case3,(int)out);
+ set_jump_target(case3, out);
if (opcode[i]==0x2A) { // SWL
// Write msb into least significant byte
if(rs2[i]) emit_rorimm(tl,24,tl);
// Write entire word
emit_writeword_indexed(tl,-3,temp);
}
- set_jump_target(done0,(int)out);
- set_jump_target(done1,(int)out);
- set_jump_target(done2,(int)out);
+ set_jump_target(done0, out);
+ set_jump_target(done1, out);
+ set_jump_target(done2, out);
if (opcode[i]==0x2C) { // SDL
emit_testimm(temp,4);
- done0=(int)out;
+ done0=out;
emit_jne(0);
emit_andimm(temp,~3,temp);
emit_writeword_indexed(temp2,4,temp);
- set_jump_target(done0,(int)out);
+ set_jump_target(done0, out);
}
if (opcode[i]==0x2D) { // SDR
emit_testimm(temp,4);
- done0=(int)out;
+ done0=out;
emit_jeq(0);
emit_andimm(temp,~3,temp);
emit_writeword_indexed(temp2,-4,temp);
- set_jump_target(done0,(int)out);
+ set_jump_target(done0, out);
}
if(!c||!memtarget)
- add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
- if(!using_tlb) {
+ add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj[i],reglist);
+ if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
#ifdef RAM_OFFSET
int map=get_reg(i_regs->regmap,ROREG);
if(map<0) map=HOST_TEMPREG;
assert(ir>=0);
emit_cmpmem_indexedsr12_reg(ir,temp,1);
#else
- emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
+ emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
#endif
#if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
emit_callne(invalidate_addr_reg[temp]);
#else
- jaddr2=(int)out;
+ void *jaddr2 = out;
emit_jne(0);
- add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
+ add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
#endif
}
- /*
- emit_pusha();
- //save_regs(0x100f);
- emit_readword((int)&last_count,ECX);
- if(get_reg(i_regs->regmap,CCREG)<0)
- emit_loadreg(CCREG,HOST_CCREG);
- emit_add(HOST_CCREG,ECX,HOST_CCREG);
- emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
- emit_writeword(HOST_CCREG,(int)&Count);
- emit_call((int)memdebug);
- emit_popa();
- //restore_regs(0x100f);
- /**/
}
void c1ls_assemble(int i,struct regstat *i_regs)
{
-#ifndef DISABLE_COP1
- int s,th,tl;
- int temp,ar;
- int map=-1;
- int offset;
- int c=0;
- int jaddr,jaddr2=0,jaddr3,type;
- int agr=AGEN1+(i&1);
- u_int hr,reglist=0;
- th=get_reg(i_regs->regmap,FTEMP|64);
- tl=get_reg(i_regs->regmap,FTEMP);
- s=get_reg(i_regs->regmap,rs1[i]);
- temp=get_reg(i_regs->regmap,agr);
- if(temp<0) temp=get_reg(i_regs->regmap,-1);
- offset=imm[i];
- assert(tl>=0);
- assert(rs1[i]>0);
- assert(temp>=0);
- for(hr=0;hr<HOST_REGS;hr++) {
- if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
- }
- if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
- if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
- {
- // Loads use a temporary register which we need to save
- reglist|=1<<temp;
- }
- if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
- ar=temp;
- else // LWC1/LDC1
- ar=tl;
- //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
- //else c=(i_regs->wasconst>>s)&1;
- if(s>=0) c=(i_regs->wasconst>>s)&1;
- // Check cop1 unusable
- if(!cop1_usable) {
- signed char rs=get_reg(i_regs->regmap,CSREG);
- assert(rs>=0);
- emit_testimm(rs,0x20000000);
- jaddr=(int)out;
- emit_jeq(0);
- add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
- cop1_usable=1;
- }
- if (opcode[i]==0x39) { // SWC1 (get float address)
- emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
- }
- if (opcode[i]==0x3D) { // SDC1 (get double address)
- emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
- }
- // Generate address + offset
- if(!using_tlb) {
- if(!c)
- emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
- }
- else
- {
- map=get_reg(i_regs->regmap,TLREG);
- assert(map>=0);
- if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
- map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
- }
- if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
- map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
- }
- }
- if (opcode[i]==0x39) { // SWC1 (read float)
- emit_readword_indexed(0,tl,tl);
- }
- if (opcode[i]==0x3D) { // SDC1 (read double)
- emit_readword_indexed(4,tl,th);
- emit_readword_indexed(0,tl,tl);
- }
- if (opcode[i]==0x31) { // LWC1 (get target address)
- emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
- }
- if (opcode[i]==0x35) { // LDC1 (get target address)
- emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
- }
- if(!using_tlb) {
- if(!c) {
- jaddr2=(int)out;
- emit_jno(0);
- }
- else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
- jaddr2=(int)out;
- emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
- }
- #ifdef DESTRUCTIVE_SHIFT
- if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
- if(!offset&&!c&&s>=0) emit_mov(s,ar);
- }
- #endif
- }else{
- if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
- do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
- }
- if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
- do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
- }
- }
- if (opcode[i]==0x31) { // LWC1
- //if(s>=0&&!c&&!offset) emit_mov(s,tl);
- //gen_tlb_addr_r(ar,map);
- //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
- #ifdef HOST_IMM_ADDR32
- if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
- else
- #endif
- emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
- type=LOADW_STUB;
- }
- if (opcode[i]==0x35) { // LDC1
- assert(th>=0);
- //if(s>=0&&!c&&!offset) emit_mov(s,tl);
- //gen_tlb_addr_r(ar,map);
- //emit_readword_indexed((int)rdram-0x80000000,tl,th);
- //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
- #ifdef HOST_IMM_ADDR32
- if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
- else
- #endif
- emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
- type=LOADD_STUB;
- }
- if (opcode[i]==0x39) { // SWC1
- //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
- emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
- type=STOREW_STUB;
- }
- if (opcode[i]==0x3D) { // SDC1
- assert(th>=0);
- //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
- //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
- emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
- type=STORED_STUB;
- }
- if(!using_tlb) {
- if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
- #ifndef DESTRUCTIVE_SHIFT
- temp=offset||c||s<0?ar:s;
- #endif
- #if defined(HOST_IMM8)
- int ir=get_reg(i_regs->regmap,INVCP);
- assert(ir>=0);
- emit_cmpmem_indexedsr12_reg(ir,temp,1);
- #else
- emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
- #endif
- #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
- emit_callne(invalidate_addr_reg[temp]);
- #else
- jaddr3=(int)out;
- emit_jne(0);
- add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
- #endif
- }
- }
- if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
- if (opcode[i]==0x31) { // LWC1 (write float)
- emit_writeword_indexed(tl,0,temp);
- }
- if (opcode[i]==0x35) { // LDC1 (write double)
- emit_writeword_indexed(th,4,temp);
- emit_writeword_indexed(tl,0,temp);
- }
- //if(opcode[i]==0x39)
- /*if(opcode[i]==0x39||opcode[i]==0x31)
- {
- emit_pusha();
- emit_readword((int)&last_count,ECX);
- if(get_reg(i_regs->regmap,CCREG)<0)
- emit_loadreg(CCREG,HOST_CCREG);
- emit_add(HOST_CCREG,ECX,HOST_CCREG);
- emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
- emit_writeword(HOST_CCREG,(int)&Count);
- emit_call((int)memdebug);
- emit_popa();
- }/**/
-#else
cop1_unusable(i, i_regs);
-#endif
}
void c2ls_assemble(int i,struct regstat *i_regs)
int ar;
int offset;
int memtarget=0,c=0;
- int jaddr2=0,jaddr3,type;
+ void *jaddr2=NULL;
+ enum stub_type type;
int agr=AGEN1+(i&1);
+ int fastio_reg_override=0;
u_int hr,reglist=0;
u_int copr=(source[i]>>16)&0x1f;
s=get_reg(i_regs->regmap,rs1[i]);
offset=imm[i];
assert(rs1[i]>0);
assert(tl>=0);
- assert(!using_tlb);
for(hr=0;hr<HOST_REGS;hr++) {
if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
type=LOADW_STUB;
if(c&&!memtarget) {
- jaddr2=(int)out;
+ jaddr2=out;
emit_jmp(0); // inline_readstub/inline_writestub?
}
else {
if(!c) {
- emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
- jaddr2=(int)out;
- emit_jno(0);
+ jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
+ }
+ else if(ram_offset&&memtarget) {
+ emit_addimm(ar,ram_offset,HOST_TEMPREG);
+ fastio_reg_override=HOST_TEMPREG;
}
if (opcode[i]==0x32) { // LWC2
#ifdef HOST_IMM_ADDR32
if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
else
#endif
- emit_readword_indexed(0,ar,tl);
+ int a=ar;
+ if(fastio_reg_override) a=fastio_reg_override;
+ emit_readword_indexed(0,a,tl);
}
if (opcode[i]==0x3a) { // SWC2
#ifdef DESTRUCTIVE_SHIFT
if(!offset&&!c&&s>=0) emit_mov(s,ar);
#endif
- emit_writeword_indexed(tl,0,ar);
+ int a=ar;
+ if(fastio_reg_override) a=fastio_reg_override;
+ emit_writeword_indexed(tl,0,a);
}
}
if(jaddr2)
- add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
- if (opcode[i]==0x3a) { // SWC2
+ add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj[i],reglist);
+ if(opcode[i]==0x3a) // SWC2
+ if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
#if defined(HOST_IMM8)
int ir=get_reg(i_regs->regmap,INVCP);
assert(ir>=0);
emit_cmpmem_indexedsr12_reg(ir,ar,1);
#else
- emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
+ emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
#endif
#if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
emit_callne(invalidate_addr_reg[ar]);
#else
- jaddr3=(int)out;
+ void *jaddr3 = out;
emit_jne(0);
- add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
+ add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
#endif
}
if (opcode[i]==0x32) { // LWC2
signed char ccreg=get_reg(i_regs->regmap,CCREG);
assert(ccreg==HOST_CCREG);
assert(!is_delayslot);
+ (void)ccreg;
emit_movimm(start+i*4,EAX); // Get PC
- emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
- emit_jmp((int)jump_syscall_hle); // XXX
+ emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
+ emit_jmp(jump_syscall_hle); // XXX
}
void hlecall_assemble(int i,struct regstat *i_regs)
{
+ extern void psxNULL();
signed char ccreg=get_reg(i_regs->regmap,CCREG);
assert(ccreg==HOST_CCREG);
assert(!is_delayslot);
+ (void)ccreg;
emit_movimm(start+i*4+4,0); // Get PC
- emit_movimm((int)psxHLEt[source[i]&7],1);
- emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
- emit_jmp((int)jump_hlecall);
+ uint32_t hleCode = source[i] & 0x03ffffff;
+ if (hleCode >= ARRAY_SIZE(psxHLEt))
+ emit_movimm((uintptr_t)psxNULL,1);
+ else
+ emit_movimm((uintptr_t)psxHLEt[hleCode],1);
+ emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
+ emit_jmp(jump_hlecall);
}
void intcall_assemble(int i,struct regstat *i_regs)
signed char ccreg=get_reg(i_regs->regmap,CCREG);
assert(ccreg==HOST_CCREG);
assert(!is_delayslot);
+ (void)ccreg;
emit_movimm(start+i*4,0); // Get PC
- emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
- emit_jmp((int)jump_intcall);
+ emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
+ emit_jmp(jump_intcall);
}
void ds_assemble(int i,struct regstat *i_regs)
{
+ speculate_register_values(i);
is_delayslot=1;
switch(itype[i]) {
case ALU:
case CJUMP:
case SJUMP:
case FJUMP:
- printf("Jump in the delay slot. This is probably a bug.\n");
+ SysPrintf("Jump in the delay slot. This is probably a bug.\n");
}
is_delayslot=0;
}
if(addr&1) return 0; // Indirect (register) jump
if(addr>=start && addr<start+slen*4-4)
{
- int t=(addr-start)>>2;
+ //int t=(addr-start)>>2;
// Delay slots are not valid branch targets
//if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
// 64 -> 32 bit transition requires a recompile
else printf("optimizable: yes\n");
}*/
//if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
-#ifndef FORCE32
- if(requires_32bit[t]&~i_is32) return 0;
- else
-#endif
- return 1;
+ return 1;
}
return 0;
}
void address_generation(int i,struct regstat *i_regs,signed char entry[])
{
if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
- int ra;
+ int ra=-1;
int agr=AGEN1+(i&1);
- int mgr=MGEN1+(i&1);
if(itype[i]==LOAD) {
ra=get_reg(i_regs->regmap,rt1[i]);
- if(ra<0) ra=get_reg(i_regs->regmap,-1);
+ if(ra<0) ra=get_reg(i_regs->regmap,-1);
assert(ra>=0);
}
if(itype[i]==LOADLR) {
}
}
int rs=get_reg(i_regs->regmap,rs1[i]);
- int rm=get_reg(i_regs->regmap,TLREG);
if(ra>=0) {
int offset=imm[i];
int c=(i_regs->wasconst>>rs)&1;
if(rs1[i]==0) {
// Using r0 as a base address
- /*if(rm>=0) {
- if(!entry||entry[rm]!=mgr) {
- generate_map_const(offset,rm);
- } // else did it in the previous cycle
- }*/
if(!entry||entry[ra]!=agr) {
if (opcode[i]==0x22||opcode[i]==0x26) {
emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
// printf("poor load scheduling!\n");
}
else if(c) {
- if(rm>=0) {
- if(!entry||entry[rm]!=mgr) {
- if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
- // Stores to memory go thru the mapper to detect self-modifying
- // code, loads don't.
- if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
- (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
- generate_map_const(constmap[i][rs]+offset,rm);
- }else{
- if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
- generate_map_const(constmap[i][rs]+offset,rm);
- }
- }
- }
if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
if(!entry||entry[ra]!=agr) {
if (opcode[i]==0x22||opcode[i]==0x26) {
emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
}else{
#ifdef HOST_IMM_ADDR32
- if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
- (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
+ if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32)) // LWC1/LDC1/LWC2/LDC2
#endif
emit_movimm(constmap[i][rs]+offset,ra);
+ regs[i].loadedconst|=1<<ra;
}
} // else did it in the previous cycle
} // else load_consts already did it
// Preload constants for next instruction
if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
int agr,ra;
- #ifndef HOST_IMM_ADDR32
- // Mapper entry
- agr=MGEN1+((i+1)&1);
- ra=get_reg(i_regs->regmap,agr);
- if(ra>=0) {
- int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
- int offset=imm[i+1];
- int c=(regs[i+1].wasconst>>rs)&1;
- if(c) {
- if(itype[i+1]==STORE||itype[i+1]==STORELR
- ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
- // Stores to memory go thru the mapper to detect self-modifying
- // code, loads don't.
- if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
- (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
- generate_map_const(constmap[i+1][rs]+offset,ra);
- }else{
- if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
- generate_map_const(constmap[i+1][rs]+offset,ra);
- }
- }
- /*else if(rs1[i]==0) {
- generate_map_const(offset,ra);
- }*/
- }
- #endif
// Actual address
agr=AGEN1+((i+1)&1);
ra=get_reg(i_regs->regmap,agr);
emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
}else{
#ifdef HOST_IMM_ADDR32
- if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
- (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
+ if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32)) // LWC1/LDC1/LWC2/LDC2
#endif
emit_movimm(constmap[i+1][rs]+offset,ra);
+ regs[i+1].loadedconst|=1<<ra;
}
}
else if(rs1[i+1]==0) {
}
}
-int get_final_value(int hr, int i, int *value)
+static int get_final_value(int hr, int i, int *value)
{
int reg=regs[i].regmap[hr];
while(i<slen-1) {
// Load in delay slot, out-of-order execution
if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
{
- #ifdef HOST_IMM_ADDR32
- if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
- #endif
// Precompute load address
*value=constmap[i][hr]+imm[i+2];
return 1;
}
if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
{
- #ifdef HOST_IMM_ADDR32
- if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
- #endif
// Precompute load address
*value=constmap[i][hr]+imm[i+1];
- //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
+ //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
return 1;
}
}
}
*value=constmap[i][hr];
- //printf("c=%x\n",(int)constmap[i][hr]);
+ //printf("c=%lx\n",(long)constmap[i][hr]);
if(i==slen-1) return 1;
if(reg<64) {
return !((unneeded_reg[i+1]>>reg)&1);
// Load registers with known constants
void load_consts(signed char pre[],signed char regmap[],int is32,int i)
{
- int hr;
+ int hr,hr2;
+ // propagate loaded constant flags
+ if(i==0||bt[i])
+ regs[i].loadedconst=0;
+ else {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
+ &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
+ {
+ regs[i].loadedconst|=1<<hr;
+ }
+ }
+ }
// Load 32-bit regs
for(hr=0;hr<HOST_REGS;hr++) {
if(hr!=EXCLUDE_REG&®map[hr]>=0) {
//if(entry[hr]!=regmap[hr]) {
- if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
+ if(!((regs[i].loadedconst>>hr)&1)) {
if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
- int value;
+ int value,similar=0;
if(get_final_value(hr,i,&value)) {
- if(value==0) {
+ // see if some other register has similar value
+ for(hr2=0;hr2<HOST_REGS;hr2++) {
+ if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
+ if(is_similar_value(value,constmap[i][hr2])) {
+ similar=1;
+ break;
+ }
+ }
+ }
+ if(similar) {
+ int value2;
+ if(get_final_value(hr2,i,&value2)) // is this needed?
+ emit_movimm_from(value2,hr2,value,hr);
+ else
+ emit_movimm(value,hr);
+ }
+ else if(value==0) {
emit_zeroreg(hr);
}
else {
emit_movimm(value,hr);
}
}
+ regs[i].loadedconst|=1<<hr;
}
}
}
if((i_dirty>>hr)&1) {
if(i_regmap[hr]<64) {
emit_storereg(i_regmap[hr],hr);
-#ifndef FORCE32
- if( ((i_is32>>i_regmap[hr])&1) ) {
- #ifdef DESTRUCTIVE_WRITEBACK
- emit_sarimm(hr,31,hr);
- emit_storereg(i_regmap[hr]|64,hr);
- #else
- emit_sarimm(hr,31,HOST_TEMPREG);
- emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
- #endif
- }
-#endif
}else{
if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
emit_storereg(i_regmap[hr],hr);
if((i_dirty>>hr)&1) {
if(i_regmap[hr]<64) {
emit_storereg(i_regmap[hr],hr);
-#ifndef FORCE32
- if( ((i_is32>>i_regmap[hr])&1) ) {
- #ifdef DESTRUCTIVE_WRITEBACK
- emit_sarimm(hr,31,hr);
- emit_storereg(i_regmap[hr]|64,hr);
- #else
- emit_sarimm(hr,31,HOST_TEMPREG);
- emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
- #endif
- }
-#endif
}else{
if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
emit_storereg(i_regmap[hr],hr);
emit_zeroreg(hr);
}
else
- if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
+ if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
{
emit_loadreg(i_regmap[hr],hr);
}
emit_zeroreg(hr);
}
else
- if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
+ if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
{
emit_loadreg(i_regmap[hr],hr);
}
void load_regs_entry(int t)
{
int hr;
- if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
- else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
+ if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
+ else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
emit_storereg(CCREG,HOST_CCREG);
}
// Load 32-bit regs
for(hr=0;hr<HOST_REGS;hr++) {
- if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
+ if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
if(regs[t].regmap_entry[hr]==0) {
emit_zeroreg(hr);
}
}
// Load 64-bit regs
for(hr=0;hr<HOST_REGS;hr++) {
- if(regs[t].regmap_entry[hr]>=64) {
+ if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
assert(regs[t].regmap_entry[hr]!=64);
if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
}
// Load 32-bit regs
for(hr=0;hr<HOST_REGS;hr++) {
- if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
+ if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
#ifdef DESTRUCTIVE_WRITEBACK
if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
#else
}
//Load 64-bit regs
for(hr=0;hr<HOST_REGS;hr++) {
- if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64) {
+ if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
assert(regs[t].regmap_entry[hr]!=64);
if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
{
if(i_regmap[hr]!=regs[t].regmap_entry[hr])
{
- if(regs[t].regmap_entry[hr]!=-1)
+ if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
{
return 0;
}
- else
+ else
if((i_dirty>>hr)&1)
{
- if(i_regmap[hr]<64)
+ if(i_regmap[hr]<TEMPREG)
{
if(!((unneeded_reg[t]>>i_regmap[hr])&1))
return 0;
}
- else
+ else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
{
if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
return 0;
}
}
//if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
-#ifndef FORCE32
- if(requires_32bit[t]&~i_is32) return 0;
-#endif
// Delay slots are not valid branch targets
//if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
// Delay slots require additional processing, so do not match
return 1;
}
+#ifdef DRC_DBG
+static void drc_dbg_emit_do_cmp(int i)
+{
+ extern void do_insn_cmp();
+ extern int cycle;
+ u_int hr,reglist=0;
+
+ for(hr=0;hr<HOST_REGS;hr++)
+ if(regs[i].regmap[hr]>=0) reglist|=1<<hr;
+ save_regs(reglist);
+ emit_movimm(start+i*4,0);
+ emit_writeword(0,&pcaddr);
+ emit_call(do_insn_cmp);
+ //emit_readword(&cycle,0);
+ //emit_addimm(0,2,0);
+ //emit_writeword(0,&cycle);
+ restore_regs(reglist);
+}
+#else
+#define drc_dbg_emit_do_cmp(x)
+#endif
+
// Used when a branch jumps into the delay slot of another branch
void ds_assemble_entry(int i)
{
int t=(ba[i]-start)>>2;
- if(!instr_addr[t]) instr_addr[t]=(u_int)out;
+ if (!instr_addr[t])
+ instr_addr[t] = out;
assem_debug("Assemble delay slot at %x\n",ba[i]);
assem_debug("<->\n");
+ drc_dbg_emit_do_cmp(t);
if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
case CJUMP:
case SJUMP:
case FJUMP:
- printf("Jump in the delay slot. This is probably a bug.\n");
+ SysPrintf("Jump in the delay slot. This is probably a bug.\n");
}
store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
else
assem_debug("branch: external\n");
assert(internal_branch(regs[t].is32,ba[i]+4));
- add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
+ add_to_linker(out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
emit_jmp(0);
}
void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
{
int count;
- int jaddr;
- int idle=0;
+ void *jaddr;
+ void *idle=NULL;
+ int t=0;
if(itype[i]==RJUMP)
{
*adj=0;
//if(ba[i]>=start && ba[i]<(start+slen*4))
if(internal_branch(branch_regs[i].is32,ba[i]))
{
- int t=(ba[i]-start)>>2;
+ t=(ba[i]-start)>>2;
if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
else *adj=ccadj[t];
}
if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
// Idle loop
if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
- idle=(int)out;
+ idle=out;
//emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
emit_andimm(HOST_CCREG,3,HOST_CCREG);
- jaddr=(int)out;
+ jaddr=out;
emit_jmp(0);
}
else if(*adj==0||invert) {
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
- jaddr=(int)out;
+ int cycles=CLOCK_ADJUST(count+2);
+ // faster loop HACK
+ if (t&&*adj) {
+ int rel=t-i;
+ if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
+ cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
+ }
+ emit_addimm_and_set_flags(cycles,HOST_CCREG);
+ jaddr=out;
emit_jns(0);
}
else
{
- emit_cmpimm(HOST_CCREG,-2*(count+2));
- jaddr=(int)out;
+ emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
+ jaddr=out;
emit_jns(0);
}
- add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
+ add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
}
-void do_ccstub(int n)
+static void do_ccstub(int n)
{
literal_pool(256);
- assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
- set_jump_target(stubs[n][1],(int)out);
- int i=stubs[n][4];
- if(stubs[n][6]==NULLDS) {
+ assem_debug("do_ccstub %x\n",start+stubs[n].b*4);
+ set_jump_target(stubs[n].addr, out);
+ int i=stubs[n].b;
+ if(stubs[n].d==NULLDS) {
// Delay slot instruction is nullified ("likely" branch)
wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
}
- else if(stubs[n][6]!=TAKEN) {
+ else if(stubs[n].d!=TAKEN) {
wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
}
else {
if(internal_branch(branch_regs[i].is32,ba[i]))
wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
}
- if(stubs[n][5]!=-1)
+ if(stubs[n].c!=-1)
{
// Save PC as return address
- emit_movimm(stubs[n][5],EAX);
- emit_writeword(EAX,(int)&pcaddr);
+ emit_movimm(stubs[n].c,EAX);
+ emit_writeword(EAX,&pcaddr);
}
else
{
if(rs1[i]) {
if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
emit_loadreg(rs1[i],s1l);
- }
+ }
else {
if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
emit_loadreg(rs2[i],s1l);
emit_loadreg(rs2[i],s2l);
#endif
int hr=0;
- int addr,alt,ntaddr;
+ int addr=-1,alt=-1,ntaddr=-1;
while(hr<HOST_REGS)
{
if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
emit_cmovne_reg(alt,addr);
}
}
- emit_writeword(addr,(int)&pcaddr);
+ emit_writeword(addr,&pcaddr);
}
else
if(itype[i]==RJUMP)
if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
r=get_reg(branch_regs[i].regmap,RTEMP);
}
- emit_writeword(r,(int)&pcaddr);
+ emit_writeword(r,&pcaddr);
}
- else {printf("Unknown branch type in do_ccstub\n");exit(1);}
+ else {SysPrintf("Unknown branch type in do_ccstub\n");exit(1);}
}
// Update cycle count
assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
- if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
- emit_call((int)cc_interrupt);
- if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
- if(stubs[n][6]==TAKEN) {
+ if(stubs[n].a) emit_addimm(HOST_CCREG,CLOCK_ADJUST((signed int)stubs[n].a),HOST_CCREG);
+ emit_call(cc_interrupt);
+ if(stubs[n].a) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((signed int)stubs[n].a),HOST_CCREG);
+ if(stubs[n].d==TAKEN) {
if(internal_branch(branch_regs[i].is32,ba[i]))
load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
else if(itype[i]==RJUMP) {
if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
- emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
+ emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
else
emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
}
- }else if(stubs[n][6]==NOTTAKEN) {
+ }else if(stubs[n].d==NOTTAKEN) {
if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
else load_all_regs(branch_regs[i].regmap);
- }else if(stubs[n][6]==NULLDS) {
+ }else if(stubs[n].d==NULLDS) {
// Delay slot instruction is nullified ("likely" branch)
if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
else load_all_regs(regs[i].regmap);
}else{
load_all_regs(branch_regs[i].regmap);
}
- emit_jmp(stubs[n][2]); // return address
-
- /* This works but uses a lot of memory...
- emit_readword((int)&last_count,ECX);
- emit_add(HOST_CCREG,ECX,EAX);
- emit_writeword(EAX,(int)&Count);
- emit_call((int)gen_interupt);
- emit_readword((int)&Count,HOST_CCREG);
- emit_readword((int)&next_interupt,EAX);
- emit_readword((int)&pending_exception,EBX);
- emit_writeword(EAX,(int)&last_count);
- emit_sub(HOST_CCREG,EAX,HOST_CCREG);
- emit_test(EBX,EBX);
- int jne_instr=(int)out;
- emit_jne(0);
- if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
- load_all_regs(branch_regs[i].regmap);
- emit_jmp(stubs[n][2]); // return address
- set_jump_target(jne_instr,(int)out);
- emit_readword((int)&pcaddr,EAX);
- // Call get_addr_ht instead of doing the hash table here.
- // This code is executed infrequently and takes up a lot of space
- // so smaller is better.
- emit_storereg(CCREG,HOST_CCREG);
- emit_pushreg(EAX);
- emit_call((int)get_addr_ht);
- emit_loadreg(CCREG,HOST_CCREG);
- emit_addimm(ESP,4,ESP);
- emit_jmpreg(EAX);*/
+ emit_jmp(stubs[n].retaddr);
}
-add_to_linker(int addr,int target,int ext)
+static void add_to_linker(void *addr, u_int target, int ext)
{
- link_addr[linkcount][0]=addr;
- link_addr[linkcount][1]=target;
- link_addr[linkcount][2]=ext;
+ assert(linkcount < ARRAY_SIZE(link_addr));
+ link_addr[linkcount].addr = addr;
+ link_addr[linkcount].target = target;
+ link_addr[linkcount].ext = ext;
linkcount++;
}
-void ujump_assemble(int i,struct regstat *i_regs)
+static void ujump_assemble_write_ra(int i)
{
- signed char *i_regmap=i_regs->regmap;
- if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
- address_generation(i+1,i_regs,regs[i].regmap_entry);
- #ifdef REG_PREFETCH
- int temp=get_reg(branch_regs[i].regmap,PTEMP);
- if(rt1[i]==31&&temp>=0)
- {
- int return_address=start+i*4+8;
- if(get_reg(branch_regs[i].regmap,31)>0)
- if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
- }
- #endif
- if(rt1[i]==31) {
- int rt;
- unsigned int return_address;
- rt=get_reg(branch_regs[i].regmap,31);
- assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
- //assert(rt>=0);
- return_address=start+i*4+8;
- if(rt>=0) {
- #ifdef USE_MINI_HT
- if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
- int temp=-1; // note: must be ds-safe
- #ifdef HOST_TEMPREG
- temp=HOST_TEMPREG;
- #endif
- if(temp>=0) do_miniht_insert(return_address,rt,temp);
- else emit_movimm(return_address,rt);
- }
- else
+ int rt;
+ unsigned int return_address;
+ rt=get_reg(branch_regs[i].regmap,31);
+ assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
+ //assert(rt>=0);
+ return_address=start+i*4+8;
+ if(rt>=0) {
+ #ifdef USE_MINI_HT
+ if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
+ int temp=-1; // note: must be ds-safe
+ #ifdef HOST_TEMPREG
+ temp=HOST_TEMPREG;
#endif
+ if(temp>=0) do_miniht_insert(return_address,rt,temp);
+ else emit_movimm(return_address,rt);
+ }
+ else
+ #endif
+ {
+ #ifdef REG_PREFETCH
+ if(temp>=0)
{
- #ifdef REG_PREFETCH
- if(temp>=0)
- {
- if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
- }
- #endif
- emit_movimm(return_address,rt); // PC into link register
- #ifdef IMM_PREFETCH
- emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
- #endif
+ if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
}
+ #endif
+ emit_movimm(return_address,rt); // PC into link register
+ #ifdef IMM_PREFETCH
+ emit_prefetch(hash_table_get(return_address));
+ #endif
}
}
+}
+
+void ujump_assemble(int i,struct regstat *i_regs)
+{
+ int ra_done=0;
+ if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
+ address_generation(i+1,i_regs,regs[i].regmap_entry);
+ #ifdef REG_PREFETCH
+ int temp=get_reg(branch_regs[i].regmap,PTEMP);
+ if(rt1[i]==31&&temp>=0)
+ {
+ signed char *i_regmap=i_regs->regmap;
+ int return_address=start+i*4+8;
+ if(get_reg(branch_regs[i].regmap,31)>0)
+ if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
+ }
+ #endif
+ if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
+ ujump_assemble_write_ra(i); // writeback ra for DS
+ ra_done=1;
+ }
ds_assemble(i+1,i_regs);
uint64_t bc_unneeded=branch_regs[i].u;
uint64_t bc_unneeded_upper=branch_regs[i].uu;
wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
bc_unneeded,bc_unneeded_upper);
load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
+ if(!ra_done&&rt1[i]==31)
+ ujump_assemble_write_ra(i);
int cc,adj;
cc=get_reg(branch_regs[i].regmap,CCREG);
assert(cc==HOST_CCREG);
if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
#endif
do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
- if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
if(internal_branch(branch_regs[i].is32,ba[i]))
assem_debug("branch: internal\n");
ds_assemble_entry(i);
}
else {
- add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
+ add_to_linker(out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
emit_jmp(0);
}
}
+static void rjump_assemble_write_ra(int i)
+{
+ int rt,return_address;
+ assert(rt1[i+1]!=rt1[i]);
+ assert(rt2[i+1]!=rt1[i]);
+ rt=get_reg(branch_regs[i].regmap,rt1[i]);
+ assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
+ assert(rt>=0);
+ return_address=start+i*4+8;
+ #ifdef REG_PREFETCH
+ if(temp>=0)
+ {
+ if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
+ }
+ #endif
+ emit_movimm(return_address,rt); // PC into link register
+ #ifdef IMM_PREFETCH
+ emit_prefetch(hash_table_get(return_address));
+ #endif
+}
+
void rjump_assemble(int i,struct regstat *i_regs)
{
- signed char *i_regmap=i_regs->regmap;
int temp;
- int rs,cc,adj;
+ int rs,cc;
+ int ra_done=0;
rs=get_reg(branch_regs[i].regmap,rs1[i]);
assert(rs>=0);
if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
}
address_generation(i+1,i_regs,regs[i].regmap_entry);
#ifdef REG_PREFETCH
- if(rt1[i]==31)
+ if(rt1[i]==31)
{
if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
+ signed char *i_regmap=i_regs->regmap;
int return_address=start+i*4+8;
- if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
+ if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
}
}
#endif
if(rh>=0) do_preload_rhash(rh);
}
#endif
+ if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
+ rjump_assemble_write_ra(i);
+ ra_done=1;
+ }
ds_assemble(i+1,i_regs);
uint64_t bc_unneeded=branch_regs[i].u;
uint64_t bc_unneeded_upper=branch_regs[i].uu;
wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
bc_unneeded,bc_unneeded_upper);
load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
- if(rt1[i]!=0) {
- int rt,return_address;
- assert(rt1[i+1]!=rt1[i]);
- assert(rt2[i+1]!=rt1[i]);
- rt=get_reg(branch_regs[i].regmap,rt1[i]);
- assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
- assert(rt>=0);
- return_address=start+i*4+8;
- #ifdef REG_PREFETCH
- if(temp>=0)
- {
- if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
- }
- #endif
- emit_movimm(return_address,rt); // PC into link register
- #ifdef IMM_PREFETCH
- emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
- #endif
- }
+ if(!ra_done&&rt1[i]!=0)
+ rjump_assemble_write_ra(i);
cc=get_reg(branch_regs[i].regmap,CCREG);
assert(cc==HOST_CCREG);
+ (void)cc;
#ifdef USE_MINI_HT
int rh=get_reg(branch_regs[i].regmap,RHASH);
int ht=get_reg(branch_regs[i].regmap,RHTBL);
//do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
//if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
//assert(adj==0);
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
- add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
- emit_jns(0);
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
+ add_stub(CC_STUB,out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
+ if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
+ // special case for RFE
+ emit_jmp(0);
+ else
+ emit_jns(0);
//load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
#ifdef USE_MINI_HT
if(rs1[i]==31) {
else
#endif
{
- //if(rs!=EAX) emit_mov(rs,EAX);
- //emit_jmp((int)jump_vaddr_eax);
emit_jmp(jump_vaddr_reg[rs]);
}
- /* Check hash table
- temp=!rs;
- emit_mov(rs,temp);
- emit_shrimm(rs,16,rs);
- emit_xor(temp,rs,rs);
- emit_movzwl_reg(rs,rs);
- emit_shlimm(rs,4,rs);
- emit_cmpmem_indexed((int)hash_table,rs,temp);
- emit_jne((int)out+14);
- emit_readword_indexed((int)hash_table+4,rs,rs);
- emit_jmpreg(rs);
- emit_cmpmem_indexed((int)hash_table+8,rs,temp);
- emit_addimm_no_flags(8,rs);
- emit_jeq((int)out-17);
- // No hit on hash table, call compiler
- emit_pushreg(temp);
-//DEBUG >
-#ifdef DEBUG_CYCLE_COUNT
- emit_readword((int)&last_count,ECX);
- emit_add(HOST_CCREG,ECX,HOST_CCREG);
- emit_readword((int)&next_interupt,ECX);
- emit_writeword(HOST_CCREG,(int)&Count);
- emit_sub(HOST_CCREG,ECX,HOST_CCREG);
- emit_writeword(ECX,(int)&last_count);
-#endif
-//DEBUG <
- emit_storereg(CCREG,HOST_CCREG);
- emit_call((int)get_addr);
- emit_loadreg(CCREG,HOST_CCREG);
- emit_addimm(ESP,4,ESP);
- emit_jmpreg(EAX);*/
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
#endif
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
if(i>(ba[i]-start)>>2) invert=1;
#endif
-
+
if(ooo[i]) {
s1l=get_reg(branch_regs[i].regmap,rs1[i]);
s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
cc=get_reg(branch_regs[i].regmap,CCREG);
assert(cc==HOST_CCREG);
- if(unconditional)
+ if(unconditional)
store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
//do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
//assem_debug("cycle count (adj)\n");
if(unconditional) {
do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
- if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
if(internal)
assem_debug("branch: internal\n");
ds_assemble_entry(i);
}
else {
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_jmp(0);
}
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
}
}
else if(nop) {
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
- int jaddr=(int)out;
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
+ void *jaddr=out;
emit_jns(0);
- add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
+ add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
}
else {
- int taken=0,nottaken=0,nottaken1=0;
+ void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
- if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
if(!only32)
{
assert(s1h>=0);
{
if(s2h>=0) emit_cmp(s1h,s2h);
else emit_test(s1h,s1h);
- nottaken1=(int)out;
- emit_jne(1);
+ nottaken1=out;
+ emit_jne((void *)1l);
}
if(opcode[i]==5) // BNE
{
if(s2h>=0) emit_cmp(s1h,s2h);
else emit_test(s1h,s1h);
- if(invert) taken=(int)out;
- else add_to_linker((int)out,ba[i],internal);
+ if(invert) taken=out;
+ else add_to_linker(out,ba[i],internal);
emit_jne(0);
}
if(opcode[i]==6) // BLEZ
{
emit_test(s1h,s1h);
- if(invert) taken=(int)out;
- else add_to_linker((int)out,ba[i],internal);
+ if(invert) taken=out;
+ else add_to_linker(out,ba[i],internal);
emit_js(0);
- nottaken1=(int)out;
- emit_jne(1);
+ nottaken1=out;
+ emit_jne((void *)1l);
}
if(opcode[i]==7) // BGTZ
{
emit_test(s1h,s1h);
- nottaken1=(int)out;
+ nottaken1=out;
emit_js(1);
- if(invert) taken=(int)out;
- else add_to_linker((int)out,ba[i],internal);
+ if(invert) taken=out;
+ else add_to_linker(out,ba[i],internal);
emit_jne(0);
}
} // if(!only32)
-
+
//printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
assert(s1l>=0);
if(opcode[i]==4) // BEQ
if(s2l>=0) emit_cmp(s1l,s2l);
else emit_test(s1l,s1l);
if(invert){
- nottaken=(int)out;
- emit_jne(1);
+ nottaken=out;
+ emit_jne((void *)1l);
}else{
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_jeq(0);
}
}
if(s2l>=0) emit_cmp(s1l,s2l);
else emit_test(s1l,s1l);
if(invert){
- nottaken=(int)out;
+ nottaken=out;
emit_jeq(1);
}else{
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_jne(0);
}
}
{
emit_cmpimm(s1l,1);
if(invert){
- nottaken=(int)out;
+ nottaken=out;
emit_jge(1);
}else{
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_jl(0);
}
}
{
emit_cmpimm(s1l,1);
if(invert){
- nottaken=(int)out;
+ nottaken=out;
emit_jl(1);
}else{
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_jge(0);
}
}
if(invert) {
- if(taken) set_jump_target(taken,(int)out);
+ if(taken) set_jump_target(taken, out);
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
if(adj) {
- emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
- add_to_linker((int)out,ba[i],internal);
+ emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
+ add_to_linker(out,ba[i],internal);
}else{
emit_addnop(13);
- add_to_linker((int)out,ba[i],internal*2);
+ add_to_linker(out,ba[i],internal*2);
}
emit_jmp(0);
}else
#endif
{
- if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
+ if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
if(internal)
ds_assemble_entry(i);
}
else {
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_jmp(0);
}
}
- set_jump_target(nottaken,(int)out);
+ set_jump_target(nottaken, out);
}
- if(nottaken1) set_jump_target(nottaken1,(int)out);
+ if(nottaken1) set_jump_target(nottaken1, out);
if(adj) {
- if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
+ if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
}
} // (!unconditional)
} // if(ooo)
//if(likely[i]) printf("IOL\n");
//else
//printf("IOE\n");
- int taken=0,nottaken=0,nottaken1=0;
+ void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
if(!unconditional&&!nop) {
if(!only32)
{
{
if(s2h>=0) emit_cmp(s1h,s2h);
else emit_test(s1h,s1h);
- nottaken1=(int)out;
- emit_jne(2);
+ nottaken1=out;
+ emit_jne((void *)2l);
}
if((opcode[i]&0x2f)==5) // BNE
{
if(s2h>=0) emit_cmp(s1h,s2h);
else emit_test(s1h,s1h);
- taken=(int)out;
- emit_jne(1);
+ taken=out;
+ emit_jne((void *)1l);
}
if((opcode[i]&0x2f)==6) // BLEZ
{
emit_test(s1h,s1h);
- taken=(int)out;
+ taken=out;
emit_js(1);
- nottaken1=(int)out;
- emit_jne(2);
+ nottaken1=out;
+ emit_jne((void *)2l);
}
if((opcode[i]&0x2f)==7) // BGTZ
{
emit_test(s1h,s1h);
- nottaken1=(int)out;
+ nottaken1=out;
emit_js(2);
- taken=(int)out;
- emit_jne(1);
+ taken=out;
+ emit_jne((void *)1l);
}
} // if(!only32)
-
+
//printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
assert(s1l>=0);
if((opcode[i]&0x2f)==4) // BEQ
{
if(s2l>=0) emit_cmp(s1l,s2l);
else emit_test(s1l,s1l);
- nottaken=(int)out;
- emit_jne(2);
+ nottaken=out;
+ emit_jne((void *)2l);
}
if((opcode[i]&0x2f)==5) // BNE
{
if(s2l>=0) emit_cmp(s1l,s2l);
else emit_test(s1l,s1l);
- nottaken=(int)out;
+ nottaken=out;
emit_jeq(2);
}
if((opcode[i]&0x2f)==6) // BLEZ
{
emit_cmpimm(s1l,1);
- nottaken=(int)out;
+ nottaken=out;
emit_jge(2);
}
if((opcode[i]&0x2f)==7) // BGTZ
{
emit_cmpimm(s1l,1);
- nottaken=(int)out;
+ nottaken=out;
emit_jl(2);
}
} // if(!unconditional)
ds_unneeded_upper|=1;
// branch taken
if(!nop) {
- if(taken) set_jump_target(taken,(int)out);
+ if(taken) set_jump_target(taken, out);
assem_debug("1:\n");
wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
ds_unneeded,ds_unneeded_upper);
store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
assem_debug("cycle count (adj)\n");
- if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
if(internal)
assem_debug("branch: internal\n");
ds_assemble_entry(i);
}
else {
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_jmp(0);
}
}
// branch not taken
cop1_usable=prev_cop1_usable;
if(!unconditional) {
- if(nottaken1) set_jump_target(nottaken1,(int)out);
- set_jump_target(nottaken,(int)out);
+ if(nottaken1) set_jump_target(nottaken1, out);
+ set_jump_target(nottaken, out);
assem_debug("2:\n");
if(!likely[i]) {
wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
if(cc==-1&&!likely[i]) {
// Cycle count isn't in a register, temporarily load it then write it out
emit_loadreg(CCREG,HOST_CCREG);
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
- int jaddr=(int)out;
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
+ void *jaddr=out;
emit_jns(0);
- add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
+ add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
emit_storereg(CCREG,HOST_CCREG);
}
else{
cc=get_reg(i_regmap,CCREG);
assert(cc==HOST_CCREG);
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
- int jaddr=(int)out;
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
+ void *jaddr=out;
emit_jns(0);
- add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
+ add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
}
}
}
return_address=start+i*4+8;
emit_movimm(return_address,rt); // PC into link register
#ifdef IMM_PREFETCH
- if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
+ if(!nevertaken) emit_prefetch(hash_table_get(return_address));
#endif
}
}
cc=get_reg(branch_regs[i].regmap,CCREG);
assert(cc==HOST_CCREG);
- if(unconditional)
+ if(unconditional)
store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
//do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
assem_debug("cycle count (adj)\n");
if(unconditional) {
do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
- if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
if(internal)
assem_debug("branch: internal\n");
ds_assemble_entry(i);
}
else {
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_jmp(0);
}
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
}
}
else if(nevertaken) {
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
- int jaddr=(int)out;
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
+ void *jaddr=out;
emit_jns(0);
- add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
+ add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
}
else {
- int nottaken=0;
+ void *nottaken = NULL;
do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
- if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
if(!only32)
{
assert(s1h>=0);
{
emit_test(s1h,s1h);
if(invert){
- nottaken=(int)out;
+ nottaken=out;
emit_jns(1);
}else{
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_js(0);
}
}
{
emit_test(s1h,s1h);
if(invert){
- nottaken=(int)out;
+ nottaken=out;
emit_js(1);
}else{
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_jns(0);
}
}
{
emit_test(s1l,s1l);
if(invert){
- nottaken=(int)out;
+ nottaken=out;
emit_jns(1);
}else{
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_js(0);
}
}
{
emit_test(s1l,s1l);
if(invert){
- nottaken=(int)out;
+ nottaken=out;
emit_js(1);
}else{
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_jns(0);
}
}
} // if(!only32)
-
+
if(invert) {
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
if(adj) {
- emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
- add_to_linker((int)out,ba[i],internal);
+ emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
+ add_to_linker(out,ba[i],internal);
}else{
emit_addnop(13);
- add_to_linker((int)out,ba[i],internal*2);
+ add_to_linker(out,ba[i],internal*2);
}
emit_jmp(0);
}else
#endif
{
- if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
+ if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
if(internal)
ds_assemble_entry(i);
}
else {
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_jmp(0);
}
}
- set_jump_target(nottaken,(int)out);
+ set_jump_target(nottaken, out);
}
if(adj) {
- if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
+ if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
}
} // (!unconditional)
} // if(ooo)
{
// In-order execution (branch first)
//printf("IOE\n");
- int nottaken=0;
+ void *nottaken = NULL;
if(rt1[i]==31) {
int rt,return_address;
rt=get_reg(branch_regs[i].regmap,31);
return_address=start+i*4+8;
emit_movimm(return_address,rt); // PC into link register
#ifdef IMM_PREFETCH
- emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
+ emit_prefetch(hash_table_get(return_address));
#endif
}
}
if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
{
emit_test(s1h,s1h);
- nottaken=(int)out;
+ nottaken=out;
emit_jns(1);
}
if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
{
emit_test(s1h,s1h);
- nottaken=(int)out;
+ nottaken=out;
emit_js(1);
}
} // if(!only32)
if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
{
emit_test(s1l,s1l);
- nottaken=(int)out;
+ nottaken=out;
emit_jns(1);
}
if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
{
emit_test(s1l,s1l);
- nottaken=(int)out;
+ nottaken=out;
emit_js(1);
}
}
store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
assem_debug("cycle count (adj)\n");
- if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
if(internal)
assem_debug("branch: internal\n");
ds_assemble_entry(i);
}
else {
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_jmp(0);
}
}
// branch not taken
cop1_usable=prev_cop1_usable;
if(!unconditional) {
- set_jump_target(nottaken,(int)out);
+ set_jump_target(nottaken, out);
assem_debug("1:\n");
if(!likely[i]) {
wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
if(cc==-1&&!likely[i]) {
// Cycle count isn't in a register, temporarily load it then write it out
emit_loadreg(CCREG,HOST_CCREG);
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
- int jaddr=(int)out;
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
+ void *jaddr=out;
emit_jns(0);
- add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
+ add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
emit_storereg(CCREG,HOST_CCREG);
}
else{
cc=get_reg(i_regmap,CCREG);
assert(cc==HOST_CCREG);
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
- int jaddr=(int)out;
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
+ void *jaddr=out;
emit_jns(0);
- add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
+ add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
}
}
}
match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
assem_debug("fmatch=%d\n",match);
int fs,cs;
- int eaddr;
+ void *eaddr;
int invert=0;
int internal=internal_branch(branch_regs[i].is32,ba[i]);
if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
cs=get_reg(i_regmap,CSREG);
assert(cs>=0);
emit_testimm(cs,0x20000000);
- eaddr=(int)out;
+ eaddr=out;
emit_jeq(0);
- add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
+ add_stub_r(FP_STUB,eaddr,out,i,cs,i_regs,0,0);
cop1_usable=1;
}
do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
assem_debug("cycle count (adj)\n");
if(1) {
- int nottaken=0;
- if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ void *nottaken = NULL;
+ if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
if(1) {
assert(fs>=0);
emit_testimm(fs,0x800000);
if(source[i]&0x10000) // BC1T
{
if(invert){
- nottaken=(int)out;
+ nottaken=out;
emit_jeq(1);
}else{
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_jne(0);
}
}
else // BC1F
if(invert){
- nottaken=(int)out;
- emit_jne(1);
+ nottaken=out;
+ emit_jne((void *)1l);
}else{
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_jeq(0);
}
{
}
} // if(!only32)
-
+
if(invert) {
- if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
+ if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
else if(match) emit_addnop(13);
#endif
ds_assemble_entry(i);
}
else {
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_jmp(0);
}
- set_jump_target(nottaken,(int)out);
+ set_jump_target(nottaken, out);
}
if(adj) {
- if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
+ if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
}
} // (!unconditional)
} // if(ooo)
{
// In-order execution (branch first)
//printf("IOE\n");
- int nottaken=0;
+ void *nottaken = NULL;
if(1) {
//printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
if(1) {
emit_testimm(fs,0x800000);
if(source[i]&0x10000) // BC1T
{
- nottaken=(int)out;
+ nottaken=out;
emit_jeq(1);
}
else // BC1F
{
- nottaken=(int)out;
- emit_jne(1);
+ nottaken=out;
+ emit_jne((void *)1l);
}
}
} // if(!unconditional)
store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
assem_debug("cycle count (adj)\n");
- if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
if(internal)
assem_debug("branch: internal\n");
ds_assemble_entry(i);
}
else {
- add_to_linker((int)out,ba[i],internal);
+ add_to_linker(out,ba[i],internal);
emit_jmp(0);
}
// branch not taken
if(1) { // <- FIXME (don't need this)
- set_jump_target(nottaken,(int)out);
+ set_jump_target(nottaken, out);
assem_debug("1:\n");
if(!likely[i]) {
wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
if(cc==-1&&!likely[i]) {
// Cycle count isn't in a register, temporarily load it then write it out
emit_loadreg(CCREG,HOST_CCREG);
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
- int jaddr=(int)out;
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
+ void *jaddr=out;
emit_jns(0);
- add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
+ add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
emit_storereg(CCREG,HOST_CCREG);
}
else{
cc=get_reg(i_regmap,CCREG);
assert(cc==HOST_CCREG);
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
- int jaddr=(int)out;
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
+ void *jaddr=out;
emit_jns(0);
- add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
+ add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
}
}
}
int s1h=get_reg(i_regs->regmap,rs1[i]|64);
int s2l=get_reg(i_regs->regmap,rs2[i]);
int s2h=get_reg(i_regs->regmap,rs2[i]|64);
- void *nt_branch=NULL;
- int taken=0;
- int nottaken=0;
+ void *taken = NULL;
+ void *nottaken = NULL;
int unconditional=0;
if(rs1[i]==0)
{
s1h=s2h=-1;
}
int hr=0;
- int addr,alt,ntaddr;
+ int addr=-1,alt=-1,ntaddr=-1;
if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
else {
while(hr<HOST_REGS)
if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
}
- emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
+ emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
if(opcode[i]==2) // J
{
unconditional=1;
if(s1h>=0) {
if(s2h>=0) emit_cmp(s1h,s2h);
else emit_test(s1h,s1h);
- nottaken=(int)out;
+ nottaken=out;
emit_jne(0);
}
if(s2l>=0) emit_cmp(s1l,s2l);
else emit_test(s1l,s1l);
- if(nottaken) set_jump_target(nottaken,(int)out);
- nottaken=(int)out;
+ if(nottaken) set_jump_target(nottaken, out);
+ nottaken=out;
emit_jne(0);
}
if((opcode[i]&0x3f)==0x15) // BNEL
if(s1h>=0) {
if(s2h>=0) emit_cmp(s1h,s2h);
else emit_test(s1h,s1h);
- taken=(int)out;
+ taken=out;
emit_jne(0);
}
if(s2l>=0) emit_cmp(s1l,s2l);
else emit_test(s1l,s1l);
- nottaken=(int)out;
+ nottaken=out;
emit_jeq(0);
- if(taken) set_jump_target(taken,(int)out);
+ if(taken) set_jump_target(taken, out);
}
if((opcode[i]&0x3f)==6) // BLEZ
{
if((source[i]&0x30000)==0x20000) // BC1FL
{
emit_testimm(s1l,0x800000);
- nottaken=(int)out;
+ nottaken=out;
emit_jne(0);
}
if((source[i]&0x30000)==0x30000) // BC1TL
{
emit_testimm(s1l,0x800000);
- nottaken=(int)out;
+ nottaken=out;
emit_jeq(0);
}
}
int target_addr=start+i*4+5;
void *stub=out;
void *compiled_target_addr=check_addr(target_addr);
- emit_extjump_ds((int)branch_addr,target_addr);
+ emit_extjump_ds(branch_addr, target_addr);
if(compiled_target_addr) {
- set_jump_target((int)branch_addr,(int)compiled_target_addr);
+ set_jump_target(branch_addr, compiled_target_addr);
add_link(target_addr,stub);
}
- else set_jump_target((int)branch_addr,(int)stub);
+ else set_jump_target(branch_addr, stub);
if(likely[i]) {
// Not-taken path
- set_jump_target((int)nottaken,(int)out);
+ set_jump_target(nottaken, out);
wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
void *branch_addr=out;
emit_jmp(0);
int target_addr=start+i*4+8;
void *stub=out;
void *compiled_target_addr=check_addr(target_addr);
- emit_extjump_ds((int)branch_addr,target_addr);
+ emit_extjump_ds(branch_addr, target_addr);
if(compiled_target_addr) {
- set_jump_target((int)branch_addr,(int)compiled_target_addr);
+ set_jump_target(branch_addr, compiled_target_addr);
add_link(target_addr,stub);
}
- else set_jump_target((int)branch_addr,(int)stub);
+ else set_jump_target(branch_addr, stub);
}
}
if(regs[0].regmap[HOST_CCREG]!=CCREG)
wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
if(regs[0].regmap[HOST_BTREG]!=BTREG)
- emit_writeword(HOST_BTREG,(int)&branch_target);
+ emit_writeword(HOST_BTREG,&branch_target);
load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
address_generation(0,®s[0],regs[0].regmap_entry);
if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
case CJUMP:
case SJUMP:
case FJUMP:
- printf("Jump in the delay slot. This is probably a bug.\n");
+ SysPrintf("Jump in the delay slot. This is probably a bug.\n");
}
int btaddr=get_reg(regs[0].regmap,BTREG);
if(btaddr<0) {
btaddr=get_reg(regs[0].regmap,-1);
- emit_readword((int)&branch_target,btaddr);
+ emit_readword(&branch_target,btaddr);
}
assert(btaddr!=HOST_CCREG);
if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
#else
emit_cmpimm(btaddr,start+4);
#endif
- int branch=(int)out;
+ void *branch = out;
emit_jeq(0);
store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
emit_jmp(jump_vaddr_reg[btaddr]);
- set_jump_target(branch,(int)out);
+ set_jump_target(branch, out);
store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
}
void unneeded_registers(int istart,int iend,int r)
{
int i;
- uint64_t u,uu,b,bu;
- uint64_t temp_u,temp_uu;
+ uint64_t u,uu,gte_u,b,bu,gte_bu;
+ uint64_t temp_u,temp_uu,temp_gte_u=0;
uint64_t tdep;
+ uint64_t gte_u_unknown=0;
+ if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
+ gte_u_unknown=~0ll;
if(iend==slen-1) {
u=1;uu=1;
+ gte_u=gte_u_unknown;
}else{
u=unneeded_reg[iend+1];
uu=unneeded_reg_upper[iend+1];
u=1;uu=1;
+ gte_u=gte_unneeded[iend+1];
}
+
for (i=iend;i>=istart;i--)
{
//printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
{
// If subroutine call, flag return address as a possible branch target
if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
-
+
if(ba[i]<start || ba[i]>=(start+slen*4))
{
// Branch out of this block, flush all regs
u=1;
uu=1;
- /* Hexagon hack
+ gte_u=gte_u_unknown;
+ /* Hexagon hack
if(itype[i]==UJUMP&&rt1[i]==31)
{
uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
u|=1;uu|=1;
+ gte_u|=gte_rt[i+1];
+ gte_u&=~gte_rs[i+1];
// If branch is "likely" (and conditional)
// then we skip the delay slot on the fall-thru path
if(likely[i]) {
if(i<slen-1) {
u&=unneeded_reg[i+2];
uu&=unneeded_reg_upper[i+2];
+ gte_u&=gte_unneeded[i+2];
}
else
{
u=1;
uu=1;
+ gte_u=gte_u_unknown;
}
}
}
{
// Unconditional branch
temp_u=1;temp_uu=1;
+ temp_gte_u=0;
} else {
// Conditional branch (not taken case)
temp_u=unneeded_reg[i+2];
temp_uu=unneeded_reg_upper[i+2];
+ temp_gte_u&=gte_unneeded[i+2];
}
// Merge in delay slot
tdep=(~temp_uu>>rt1[i+1])&1;
temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
temp_u|=1;temp_uu|=1;
+ temp_gte_u|=gte_rt[i+1];
+ temp_gte_u&=~gte_rs[i+1];
// If branch is "likely" (and conditional)
// then we skip the delay slot on the fall-thru path
if(likely[i]) {
if(i<slen-1) {
temp_u&=unneeded_reg[i+2];
temp_uu&=unneeded_reg_upper[i+2];
+ temp_gte_u&=gte_unneeded[i+2];
}
else
{
temp_u=1;
temp_uu=1;
+ temp_gte_u=gte_u_unknown;
}
}
tdep=(~temp_uu>>rt1[i])&1;
temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
temp_u|=1;temp_uu|=1;
+ temp_gte_u|=gte_rt[i];
+ temp_gte_u&=~gte_rs[i];
unneeded_reg[i]=temp_u;
unneeded_reg_upper[i]=temp_uu;
+ gte_unneeded[i]=temp_gte_u;
// Only go three levels deep. This recursion can take an
// excessive amount of time if there are a lot of nested loops.
if(r<2) {
}else{
unneeded_reg[(ba[i]-start)>>2]=1;
unneeded_reg_upper[(ba[i]-start)>>2]=1;
+ gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
}
} /*else*/ if(1) {
if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
// Unconditional branch
u=unneeded_reg[(ba[i]-start)>>2];
uu=unneeded_reg_upper[(ba[i]-start)>>2];
+ gte_u=gte_unneeded[(ba[i]-start)>>2];
branch_unneeded_reg[i]=u;
branch_unneeded_reg_upper[i]=uu;
//u=1;
uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
u|=1;uu|=1;
+ gte_u|=gte_rt[i+1];
+ gte_u&=~gte_rs[i+1];
} else {
// Conditional branch
b=unneeded_reg[(ba[i]-start)>>2];
bu=unneeded_reg_upper[(ba[i]-start)>>2];
+ gte_bu=gte_unneeded[(ba[i]-start)>>2];
branch_unneeded_reg[i]=b;
branch_unneeded_reg_upper[i]=bu;
//b=1;
bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
b|=1;bu|=1;
+ gte_bu|=gte_rt[i+1];
+ gte_bu&=~gte_rs[i+1];
// If branch is "likely" then we skip the
// delay slot on the fall-thru path
if(likely[i]) {
u=b;
uu=bu;
+ gte_u=gte_bu;
if(i<slen-1) {
u&=unneeded_reg[i+2];
uu&=unneeded_reg_upper[i+2];
+ gte_u&=gte_unneeded[i+2];
//u=1;
//uu=1;
}
} else {
u&=b;
uu&=bu;
+ gte_u&=gte_bu;
//u=1;
//uu=1;
}
u|=1LL<<rt2[i];
uu|=1LL<<rt1[i];
uu|=1LL<<rt2[i];
+ gte_u|=gte_rt[i];
// Accessed registers are needed
u&=~(1LL<<rs1[i]);
u&=~(1LL<<rs2[i]);
uu&=~(1LL<<us1[i]);
uu&=~(1LL<<us2[i]);
+ gte_u&=~gte_rs[i];
+ if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
+ gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
// Source-target dependencies
uu&=~(tdep<<dep1[i]);
uu&=~(tdep<<dep2[i]);
// Save it
unneeded_reg[i]=u;
unneeded_reg_upper[i]=uu;
+ gte_unneeded[i]=gte_u;
/*
printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
printf("U:");
}
printf("\n");*/
}
-#ifdef FORCE32
for (i=iend;i>=istart;i--)
{
unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
}
-#endif
-}
-
-// Identify registers which are likely to contain 32-bit values
-// This is used to predict whether any branches will jump to a
-// location with 64-bit values in registers.
-static void provisional_32bit()
-{
- int i,j;
- uint64_t is32=1;
- uint64_t lastbranch=1;
-
- for(i=0;i<slen;i++)
- {
- if(i>0) {
- if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
- if(i>1) is32=lastbranch;
- else is32=1;
- }
- }
- if(i>1)
- {
- if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
- if(likely[i-2]) {
- if(i>2) is32=lastbranch;
- else is32=1;
- }
- }
- if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
- {
- if(rs1[i-2]==0||rs2[i-2]==0)
- {
- if(rs1[i-2]) {
- is32|=1LL<<rs1[i-2];
- }
- if(rs2[i-2]) {
- is32|=1LL<<rs2[i-2];
- }
- }
- }
- }
- // If something jumps here with 64-bit values
- // then promote those registers to 64 bits
- if(bt[i])
- {
- uint64_t temp_is32=is32;
- for(j=i-1;j>=0;j--)
- {
- if(ba[j]==start+i*4)
- //temp_is32&=branch_regs[j].is32;
- temp_is32&=p32[j];
- }
- for(j=i;j<slen;j++)
- {
- if(ba[j]==start+i*4)
- temp_is32=1;
- }
- is32=temp_is32;
- }
- int type=itype[i];
- int op=opcode[i];
- int op2=opcode2[i];
- int rt=rt1[i];
- int s1=rs1[i];
- int s2=rs2[i];
- if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
- // Branches don't write registers, consider the delay slot instead.
- type=itype[i+1];
- op=opcode[i+1];
- op2=opcode2[i+1];
- rt=rt1[i+1];
- s1=rs1[i+1];
- s2=rs2[i+1];
- lastbranch=is32;
- }
- switch(type) {
- case LOAD:
- if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
- opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
- is32&=~(1LL<<rt);
- else
- is32|=1LL<<rt;
- break;
- case STORE:
- case STORELR:
- break;
- case LOADLR:
- if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
- if(op==0x22) is32|=1LL<<rt; // LWL
- break;
- case IMM16:
- if (op==0x08||op==0x09|| // ADDI/ADDIU
- op==0x0a||op==0x0b|| // SLTI/SLTIU
- op==0x0c|| // ANDI
- op==0x0f) // LUI
- {
- is32|=1LL<<rt;
- }
- if(op==0x18||op==0x19) { // DADDI/DADDIU
- is32&=~(1LL<<rt);
- //if(imm[i]==0)
- // is32|=((is32>>s1)&1LL)<<rt;
- }
- if(op==0x0d||op==0x0e) { // ORI/XORI
- uint64_t sr=((is32>>s1)&1LL);
- is32&=~(1LL<<rt);
- is32|=sr<<rt;
- }
- break;
- case UJUMP:
- break;
- case RJUMP:
- break;
- case CJUMP:
- break;
- case SJUMP:
- break;
- case FJUMP:
- break;
- case ALU:
- if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
- is32|=1LL<<rt;
- }
- if(op2==0x2a||op2==0x2b) { // SLT/SLTU
- is32|=1LL<<rt;
- }
- else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
- uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
- is32&=~(1LL<<rt);
- is32|=sr<<rt;
- }
- else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
- if(s1==0&&s2==0) {
- is32|=1LL<<rt;
- }
- else if(s2==0) {
- uint64_t sr=((is32>>s1)&1LL);
- is32&=~(1LL<<rt);
- is32|=sr<<rt;
- }
- else if(s1==0) {
- uint64_t sr=((is32>>s2)&1LL);
- is32&=~(1LL<<rt);
- is32|=sr<<rt;
- }
- else {
- is32&=~(1LL<<rt);
- }
- }
- else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
- if(s1==0&&s2==0) {
- is32|=1LL<<rt;
- }
- else if(s2==0) {
- uint64_t sr=((is32>>s1)&1LL);
- is32&=~(1LL<<rt);
- is32|=sr<<rt;
- }
- else {
- is32&=~(1LL<<rt);
- }
- }
- break;
- case MULTDIV:
- if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
- is32&=~((1LL<<HIREG)|(1LL<<LOREG));
- }
- else {
- is32|=(1LL<<HIREG)|(1LL<<LOREG);
- }
- break;
- case MOV:
- {
- uint64_t sr=((is32>>s1)&1LL);
- is32&=~(1LL<<rt);
- is32|=sr<<rt;
- }
- break;
- case SHIFT:
- if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
- else is32|=1LL<<rt; // SLLV/SRLV/SRAV
- break;
- case SHIFTIMM:
- is32|=1LL<<rt;
- // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
- if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
- break;
- case COP0:
- if(op2==0) is32|=1LL<<rt; // MFC0
- break;
- case COP1:
- case COP2:
- if(op2==0) is32|=1LL<<rt; // MFC1
- if(op2==1) is32&=~(1LL<<rt); // DMFC1
- if(op2==2) is32|=1LL<<rt; // CFC1
- break;
- case C1LS:
- case C2LS:
- break;
- case FLOAT:
- case FCONV:
- break;
- case FCOMP:
- break;
- case C2OP:
- case SYSCALL:
- case HLECALL:
- break;
- default:
- break;
- }
- is32|=1;
- p32[i]=is32;
-
- if(i>0)
- {
- if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
- {
- if(rt1[i-1]==31) // JAL/JALR
- {
- // Subroutine call will return here, don't alloc any registers
- is32=1;
- }
- else if(i+1<slen)
- {
- // Internal branch will jump here, match registers to caller
- is32=0x3FFFFFFFFLL;
- }
- }
- }
- }
-}
-
-// Identify registers which may be assumed to contain 32-bit values
-// and where optimizations will rely on this.
-// This is used to determine whether backward branches can safely
-// jump to a location with 64-bit values in registers.
-static void provisional_r32()
-{
- u_int r32=0;
- int i;
-
- for (i=slen-1;i>=0;i--)
- {
- int hr;
- if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
- {
- if(ba[i]<start || ba[i]>=(start+slen*4))
- {
- // Branch out of this block, don't need anything
- r32=0;
- }
- else
- {
- // Internal branch
- // Need whatever matches the target
- // (and doesn't get overwritten by the delay slot instruction)
- r32=0;
- int t=(ba[i]-start)>>2;
- if(ba[i]>start+i*4) {
- // Forward branch
- //if(!(requires_32bit[t]&~regs[i].was32))
- // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
- if(!(pr32[t]&~regs[i].was32))
- r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
- }else{
- // Backward branch
- if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
- r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
- }
- }
- // Conditional branch may need registers for following instructions
- if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
- {
- if(i<slen-2) {
- //r32|=requires_32bit[i+2];
- r32|=pr32[i+2];
- r32&=regs[i].was32;
- // Mark this address as a branch target since it may be called
- // upon return from interrupt
- //bt[i+2]=1;
- }
- }
- // Merge in delay slot
- if(!likely[i]) {
- // These are overwritten unless the branch is "likely"
- // and the delay slot is nullified if not taken
- r32&=~(1LL<<rt1[i+1]);
- r32&=~(1LL<<rt2[i+1]);
- }
- // Assume these are needed (delay slot)
- if(us1[i+1]>0)
- {
- if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
- }
- if(us2[i+1]>0)
- {
- if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
- }
- if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
- {
- if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
- }
- if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
- {
- if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
- }
- }
- else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
- {
- // SYSCALL instruction (software interrupt)
- r32=0;
- }
- else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
- {
- // ERET instruction (return from interrupt)
- r32=0;
- }
- // Check 32 bits
- r32&=~(1LL<<rt1[i]);
- r32&=~(1LL<<rt2[i]);
- if(us1[i]>0)
- {
- if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
- }
- if(us2[i]>0)
- {
- if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
- }
- if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
- {
- if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
- }
- if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
- {
- if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
- }
- //requires_32bit[i]=r32;
- pr32[i]=r32;
-
- // Dirty registers which are 32-bit, require 32-bit input
- // as they will be written as 32-bit values
- for(hr=0;hr<HOST_REGS;hr++)
- {
- if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
- if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
- if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
- pr32[i]|=1LL<<regs[i].regmap_entry[hr];
- //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
- }
- }
- }
- }
}
// Write back dirty registers as soon as we will no longer modify them,
will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
}
+ if(branch_regs[i].regmap[r]>=0) {
+ will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
+ wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
+ }
}
}
//}
//if(ba[i]>start+i*4) { // Disable recursion (for debugging)
for(r=0;r<HOST_REGS;r++) {
if(r!=EXCLUDE_REG) {
- if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
+ signed char target_reg=branch_regs[i].regmap[r];
+ if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
}
- else
- {
- will_dirty_i&=~(1<<r);
+ else if(target_reg>=0) {
+ will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
+ wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
}
// Treat delay slot as part of branch too
/*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
}
}
}
- // Merge in delay slot
+ // Merge in delay slot (won't dirty)
for(r=0;r<HOST_REGS;r++) {
if(r!=EXCLUDE_REG) {
if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
if(i>istart) {
- if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
+ if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
{
// Don't store a register immediately after writing it,
// may prevent dual-issue.
if(r!=EXCLUDE_REG) {
if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
- }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
+ }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
}
}
}
if(r!=EXCLUDE_REG) {
if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
- }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
+ }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
}
}
}
regs[i].wasdirty|=will_dirty_i&(1<<r);
}
}
- else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
+ else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
// Register moved to a different register
will_dirty_i&=~(1<<r);
wont_dirty_i&=~(1<<r);
wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
} else {
wont_dirty_i|=1<<r;
- /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
+ /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
}
}
}
}
}
+#ifdef DISASM
/* disassembly */
void disassemble_inst(int i)
{
printf (" %x: %s\n",start+i*4,insn[i]);
}
}
+#else
+static void disassemble_inst(int i) {}
+#endif // DISASM
+
+#define DRC_TEST_VAL 0x74657374
+
+static int new_dynarec_test(void)
+{
+ int (*testfunc)(void) = (void *)out;
+ void *beginning;
+ int ret;
+
+ beginning = start_block();
+ emit_movimm(DRC_TEST_VAL,0); // test
+ emit_jmpreg(14);
+ literal_pool(0);
+ end_block(beginning);
+ SysPrintf("testing if we can run recompiled code..\n");
+ ret = testfunc();
+ if (ret == DRC_TEST_VAL)
+ SysPrintf("test passed.\n");
+ else
+ SysPrintf("test failed: %08x\n", ret);
+ out = translation_cache;
+ return ret == DRC_TEST_VAL;
+}
// clear the state completely, instead of just marking
// things invalid like invalidate_all_pages() does
void new_dynarec_clear_full()
{
int n;
- out=(u_char *)BASE_ADDR;
+ out = translation_cache;
memset(invalid_code,1,sizeof(invalid_code));
memset(hash_table,0xff,sizeof(hash_table));
memset(mini_ht,-1,sizeof(mini_ht));
pending_exception=0;
literalcount=0;
stop_after_jal=0;
+ inv_code_start=inv_code_end=~0;
// TLB
-#ifndef DISABLE_TLB
- using_tlb=0;
-#endif
- sp_in_mirror=0;
- for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
- memory_map[n]=-1;
- for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
- memory_map[n]=((u_int)rdram-0x80000000)>>2;
- for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
- memory_map[n]=-1;
for(n=0;n<4096;n++) ll_clear(jump_in+n);
for(n=0;n<4096;n++) ll_clear(jump_out+n);
for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
void new_dynarec_init()
{
- printf("Init new dynarec\n");
- out=(u_char *)BASE_ADDR;
- if (mmap (out, 1<<TARGET_SIZE_2,
+ SysPrintf("Init new dynarec\n");
+
+ // allocate/prepare a buffer for translation cache
+ // see assem_arm.h for some explanation
+#if defined(BASE_ADDR_FIXED)
+ if (mmap(translation_cache, 1 << TARGET_SIZE_2,
+ PROT_READ | PROT_WRITE | PROT_EXEC,
+ MAP_PRIVATE | MAP_ANONYMOUS,
+ -1, 0) != translation_cache) {
+ SysPrintf("mmap() failed: %s\n", strerror(errno));
+ SysPrintf("disable BASE_ADDR_FIXED and recompile\n");
+ abort();
+ }
+#elif defined(BASE_ADDR_DYNAMIC)
+ #ifdef VITA
+ sceBlock = sceKernelAllocMemBlockForVM("code", 1 << TARGET_SIZE_2);
+ if (sceBlock < 0)
+ SysPrintf("sceKernelAllocMemBlockForVM failed\n");
+ int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&translation_cache);
+ if (ret < 0)
+ SysPrintf("sceKernelGetMemBlockBase failed\n");
+ #else
+ translation_cache = mmap (NULL, 1 << TARGET_SIZE_2,
PROT_READ | PROT_WRITE | PROT_EXEC,
- MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
- -1, 0) <= 0) {printf("mmap() failed\n");}
-#ifdef MUPEN64
- rdword=&readmem_dword;
- fake_pc.f.r.rs=&readmem_dword;
- fake_pc.f.r.rt=&readmem_dword;
- fake_pc.f.r.rd=&readmem_dword;
+ MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+ if (translation_cache == MAP_FAILED) {
+ SysPrintf("mmap() failed: %s\n", strerror(errno));
+ abort();
+ }
+ #endif
+#else
+ #ifndef NO_WRITE_EXEC
+ // not all systems allow execute in data segment by default
+ if (mprotect(translation_cache, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
+ SysPrintf("mprotect() failed: %s\n", strerror(errno));
+ #endif
#endif
- int n;
+ out = translation_cache;
+ cycle_multiplier=200;
new_dynarec_clear_full();
#ifdef HOST_IMM8
// Copy this into local area so we don't have to put it in every literal pool
invc_ptr=invalid_code;
#endif
-#ifdef MUPEN64
- for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
- writemem[n] = write_nomem_new;
- writememb[n] = write_nomemb_new;
- writememh[n] = write_nomemh_new;
-#ifndef FORCE32
- writememd[n] = write_nomemd_new;
-#endif
- readmem[n] = read_nomem_new;
- readmemb[n] = read_nomemb_new;
- readmemh[n] = read_nomemh_new;
-#ifndef FORCE32
- readmemd[n] = read_nomemd_new;
-#endif
- }
- for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
- writemem[n] = write_rdram_new;
- writememb[n] = write_rdramb_new;
- writememh[n] = write_rdramh_new;
-#ifndef FORCE32
- writememd[n] = write_rdramd_new;
-#endif
- }
- for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
- writemem[n] = write_nomem_new;
- writememb[n] = write_nomemb_new;
- writememh[n] = write_nomemh_new;
-#ifndef FORCE32
- writememd[n] = write_nomemd_new;
-#endif
- readmem[n] = read_nomem_new;
- readmemb[n] = read_nomemb_new;
- readmemh[n] = read_nomemh_new;
-#ifndef FORCE32
- readmemd[n] = read_nomemd_new;
-#endif
- }
-#endif
- tlb_hacks();
arch_init();
+ new_dynarec_test();
+#ifndef RAM_FIXED
+ ram_offset=(u_int)rdram-0x80000000;
+#endif
+ if (ram_offset!=0)
+ SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
}
void new_dynarec_cleanup()
{
int n;
- if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
+#if defined(BASE_ADDR_FIXED) || defined(BASE_ADDR_DYNAMIC)
+ #ifdef VITA
+ sceKernelFreeMemBlock(sceBlock);
+ sceBlock = -1;
+ #else
+ if (munmap(translation_cache, 1<<TARGET_SIZE_2) < 0)
+ SysPrintf("munmap() failed\n");
+ #endif
+#endif
for(n=0;n<4096;n++) ll_clear(jump_in+n);
for(n=0;n<4096;n++) ll_clear(jump_out+n);
for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
#ifdef ROM_COPY
- if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
+ if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
#endif
}
+static u_int *get_source_start(u_int addr, u_int *limit)
+{
+ if (addr < 0x00200000 ||
+ (0xa0000000 <= addr && addr < 0xa0200000)) {
+ // used for BIOS calls mostly?
+ *limit = (addr&0xa0000000)|0x00200000;
+ return (u_int *)((u_int)rdram + (addr&0x1fffff));
+ }
+ else if (!Config.HLE && (
+ /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
+ (0xbfc00000 <= addr && addr < 0xbfc80000))) {
+ // BIOS
+ *limit = (addr & 0xfff00000) | 0x80000;
+ return (u_int *)((u_int)psxR + (addr&0x7ffff));
+ }
+ else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
+ *limit = (addr & 0x80600000) + 0x00200000;
+ return (u_int *)((u_int)rdram + (addr&0x1fffff));
+ }
+ return NULL;
+}
+
+static u_int scan_for_ret(u_int addr)
+{
+ u_int limit = 0;
+ u_int *mem;
+
+ mem = get_source_start(addr, &limit);
+ if (mem == NULL)
+ return addr;
+
+ if (limit > addr + 0x1000)
+ limit = addr + 0x1000;
+ for (; addr < limit; addr += 4, mem++) {
+ if (*mem == 0x03e00008) // jr $ra
+ return addr + 8;
+ }
+ return addr;
+}
+
+struct savestate_block {
+ uint32_t addr;
+ uint32_t regflags;
+};
+
+static int addr_cmp(const void *p1_, const void *p2_)
+{
+ const struct savestate_block *p1 = p1_, *p2 = p2_;
+ return p1->addr - p2->addr;
+}
+
+int new_dynarec_save_blocks(void *save, int size)
+{
+ struct savestate_block *blocks = save;
+ int maxcount = size / sizeof(blocks[0]);
+ struct savestate_block tmp_blocks[1024];
+ struct ll_entry *head;
+ int p, s, d, o, bcnt;
+ u_int addr;
+
+ o = 0;
+ for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
+ bcnt = 0;
+ for (head = jump_in[p]; head != NULL; head = head->next) {
+ tmp_blocks[bcnt].addr = head->vaddr;
+ tmp_blocks[bcnt].regflags = head->reg_sv_flags;
+ bcnt++;
+ }
+ if (bcnt < 1)
+ continue;
+ qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
+
+ addr = tmp_blocks[0].addr;
+ for (s = d = 0; s < bcnt; s++) {
+ if (tmp_blocks[s].addr < addr)
+ continue;
+ if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
+ tmp_blocks[d++] = tmp_blocks[s];
+ addr = scan_for_ret(tmp_blocks[s].addr);
+ }
+
+ if (o + d > maxcount)
+ d = maxcount - o;
+ memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
+ o += d;
+ }
+
+ return o * sizeof(blocks[0]);
+}
+
+void new_dynarec_load_blocks(const void *save, int size)
+{
+ const struct savestate_block *blocks = save;
+ int count = size / sizeof(blocks[0]);
+ u_int regs_save[32];
+ uint32_t f;
+ int i, b;
+
+ get_addr(psxRegs.pc);
+
+ // change GPRs for speculation to at least partially work..
+ memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
+ for (i = 1; i < 32; i++)
+ psxRegs.GPR.r[i] = 0x80000000;
+
+ for (b = 0; b < count; b++) {
+ for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
+ if (f & 1)
+ psxRegs.GPR.r[i] = 0x1f800000;
+ }
+
+ get_addr(blocks[b].addr);
+
+ for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
+ if (f & 1)
+ psxRegs.GPR.r[i] = 0x80000000;
+ }
+ }
+
+ memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
+}
+
int new_recompile_block(int addr)
{
-/*
- if(addr==0x800cd050) {
- int block;
- for(block=0x80000;block<0x80800;block++) invalidate_block(block);
- int n;
- for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
- }
-*/
- //if(Count==365117028) tracedebug=1;
- assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
- //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
+ u_int pagelimit = 0;
+ u_int state_rflags = 0;
+ int i;
+
+ assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
//printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
- //if(debug)
+ //if(debug)
//printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
//printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
- /*if(Count>=312978186) {
- rlist();
- }*/
- //rlist();
+
+ // this is just for speculation
+ for (i = 1; i < 32; i++) {
+ if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
+ state_rflags |= 1 << i;
+ }
+
start = (u_int)addr&~3;
//assert(((u_int)addr&1)==0);
-#ifdef PCSX
- if(!sp_in_mirror&&(signed int)(psxRegs.GPR.n.sp&0xffe00000)>0x80200000&&
- 0x10000<=psxRegs.GPR.n.sp&&(psxRegs.GPR.n.sp&~0xe0e00000)<RAM_SIZE) {
- printf("SP hack enabled (%08x), @%08x\n", psxRegs.GPR.n.sp, psxRegs.pc);
- sp_in_mirror=1;
- }
+ new_dynarec_did_compile=1;
if (Config.HLE && start == 0x80001000) // hlecall
{
// XXX: is this enough? Maybe check hleSoftCall?
- u_int beginning=(u_int)out;
+ void *beginning=start_block();
u_int page=get_page(start);
+
invalid_code[start>>12]=0;
emit_movimm(start,0);
- emit_writeword(0,(int)&pcaddr);
- emit_jmp((int)new_dyna_leave);
-#ifdef __arm__
- __clear_cache((void *)beginning,out);
-#endif
- ll_add(jump_in+page,start,(void *)beginning);
+ emit_writeword(0,&pcaddr);
+ emit_jmp(new_dyna_leave);
+ literal_pool(0);
+ end_block(beginning);
+ ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
return 0;
}
- else if ((u_int)addr < 0x00200000 ||
- (0xa0000000 <= addr && addr < 0xa0200000)) {
- // used for BIOS calls mostly?
- source = (u_int *)((u_int)rdram+(start&0x1fffff));
- pagelimit = (addr&0xa0000000)|0x00200000;
- }
- else if (!Config.HLE && (
-/* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
- (0xbfc00000 <= addr && addr < 0xbfc80000))) {
- // BIOS
- source = (u_int *)((u_int)psxR+(start&0x7ffff));
- pagelimit = (addr&0xfff00000)|0x80000;
- }
- else
-#endif
-#ifdef MUPEN64
- if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
- source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
- pagelimit = 0xa4001000;
- }
- else
-#endif
- if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
- source = (u_int *)((u_int)rdram+start-0x80000000);
- pagelimit = 0x80000000+RAM_SIZE;
- }
-#ifndef DISABLE_TLB
- else if ((signed int)addr >= (signed int)0xC0000000) {
- //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
- //if(tlb_LUT_r[start>>12])
- //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
- if((signed int)memory_map[start>>12]>=0) {
- source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
- pagelimit=(start+4096)&0xFFFFF000;
- int map=memory_map[start>>12];
- int i;
- for(i=0;i<5;i++) {
- //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
- if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
- }
- assem_debug("pagelimit=%x\n",pagelimit);
- assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
- }
- else {
- assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
- //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
- return -1; // Caller will invoke exception handler
- }
- //printf("source= %x\n",(int)source);
- }
-#endif
- else {
- printf("Compile at bogus memory address: %x \n", (int)addr);
+
+ source = get_source_start(start, &pagelimit);
+ if (source == NULL) {
+ SysPrintf("Compile at bogus memory address: %08x\n", addr);
exit(1);
}
/* Pass 9: linker */
/* Pass 10: garbage collection / free memory */
- int i,j;
+ int j;
int done=0;
unsigned int type,op,op2;
//printf("addr = %x source = %x %x\n", addr,source,source[0]);
-
+
/* Pass 1 disassembly */
for(i=0;!done;i++) {
case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
-#ifndef FORCE32
+#if 0
case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
-#ifdef PCSX
case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
-#else
- case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
-#endif
+ //case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
}
}
break;
break;
}
break;
-#ifndef FORCE32
+#if 0
case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
+#if 0
case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
+#endif
case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
-#ifndef FORCE32
+#if 0
case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
#endif
case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
case 0x30: strcpy(insn[i],"LL"); type=NI; break;
case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
-#ifndef FORCE32
+#if 0
case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
#endif
case 0x38: strcpy(insn[i],"SC"); type=NI; break;
case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
-#ifndef FORCE32
+#if 0
case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
#endif
-#ifdef PCSX
case 0x12: strcpy(insn[i],"COP2"); type=NI;
- // note: COP MIPS-1 encoding differs from MIPS32
op2=(source[i]>>21)&0x1f;
- if (source[i]&0x3f) {
+ //if (op2 & 0x10) {
+ if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
if (gte_handlers[source[i]&0x3f]!=NULL) {
- snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
+ if (gte_regnames[source[i]&0x3f]!=NULL)
+ strcpy(insn[i],gte_regnames[source[i]&0x3f]);
+ else
+ snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
type=C2OP;
}
}
case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
-#endif
default: strcpy(insn[i],"???"); type=NI;
- printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
+ SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
break;
}
itype[i]=type;
us2[i]=0;
dep1[i]=0;
dep2[i]=0;
+ gte_rs[i]=gte_rt[i]=0;
switch(type) {
case LOAD:
rs1[i]=(source[i]>>21)&0x1f;
if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
break;
case COP1:
- case COP2:
rs1[i]=0;
rs2[i]=0;
rt1[i]=0;
if(op2==5) us1[i]=rs1[i]; // DMTC1
rs2[i]=CSREG;
break;
+ case COP2:
+ rs1[i]=0;
+ rs2[i]=0;
+ rt1[i]=0;
+ rt2[i]=0;
+ if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
+ if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
+ rs2[i]=CSREG;
+ int gr=(source[i]>>11)&0x1F;
+ switch(op2)
+ {
+ case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
+ case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
+ case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
+ case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
+ }
+ break;
case C1LS:
rs1[i]=(source[i]>>21)&0x1F;
rs2[i]=CSREG;
rt1[i]=0;
rt2[i]=0;
imm[i]=(short)source[i];
+ if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
+ else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
+ break;
+ case C2OP:
+ rs1[i]=0;
+ rs2[i]=0;
+ rt1[i]=0;
+ rt2[i]=0;
+ gte_rs[i]=gte_reg_reads[source[i]&0x3f];
+ gte_rt[i]=gte_reg_writes[source[i]&0x3f];
+ gte_rt[i]|=1ll<<63; // every op changes flags
+ if((source[i]&0x3f)==GTE_MVMVA) {
+ int v = (source[i] >> 15) & 3;
+ gte_rs[i]&=~0xe3fll;
+ if(v==3) gte_rs[i]|=0xe00ll;
+ else gte_rs[i]|=3ll<<(v*2);
+ }
break;
case FLOAT:
case FCONV:
else if(type==CJUMP||type==SJUMP||type==FJUMP)
ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
else ba[i]=-1;
-#ifdef PCSX
if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
int do_in_intrp=0;
// branch in delay slot?
if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
// don't handle first branch and call interpreter if it's hit
- printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
+ SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
do_in_intrp=1;
}
// basic load delay detection
int t=(ba[i-1]-start)/4;
if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
// jump target wants DS result - potential load delay effect
- printf("load delay @%08x (%08x)\n", addr + i*4, addr);
+ SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
do_in_intrp=1;
bt[t+1]=1; // expected return from interpreter
}
else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
!(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
// v0 overwrite like this is a sign of trouble, bail out
- printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
+ SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
do_in_intrp=1;
}
}
i--; // don't compile the DS
}
}
-#endif
/* Is this the end of the block? */
if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
// Does the block continue due to a branch?
for(j=i-1;j>=0;j--)
{
+ if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
if(ba[j]==start+i*4+4) done=j=0;
if(ba[j]==start+i*4+8) done=j=0;
}
// Stop if we're compiling junk
if(itype[i]==NI&&opcode[i]==0x11) {
done=stop_after_jal=1;
- printf("Disabled speculative precompilation\n");
+ SysPrintf("Disabled speculative precompilation\n");
}
}
slen=i;
/* Pass 2 - Register dependencies and branch targets */
unneeded_registers(0,slen-1,0);
-
+
/* Pass 3 - Register allocation */
struct regstat current; // Current register allocations/status
dirty_reg(¤t,CCREG);
current.isconst=0;
current.wasconst=0;
+ current.waswritten=0;
int ds=0;
int cc=0;
- int hr;
+ int hr=-1;
-#ifndef FORCE32
- provisional_32bit();
-#endif
if((u_int)addr&1) {
// First instruction is delay slot
cc=-1;
unneeded_reg_upper[0]=1;
current.regmap[HOST_BTREG]=BTREG;
}
-
+
for(i=0;i<slen;i++)
{
if(bt[i])
if(current.regmap[hr]==0) current.regmap[hr]=-1;
}
current.isconst=0;
+ current.waswritten=0;
}
if(i>1)
{
if(hr>=0) current.regmap[hr]=-1;
}
if(rs2[i-2]) {
- current.is32|=1LL<<rs2[i-2];
- int hr=get_reg(current.regmap,rs2[i-2]|64);
- if(hr>=0) current.regmap[hr]=-1;
- }
- }
- }
- }
-#ifndef FORCE32
- // If something jumps here with 64-bit values
- // then promote those registers to 64 bits
- if(bt[i])
- {
- uint64_t temp_is32=current.is32;
- for(j=i-1;j>=0;j--)
- {
- if(ba[j]==start+i*4)
- temp_is32&=branch_regs[j].is32;
- }
- for(j=i;j<slen;j++)
- {
- if(ba[j]==start+i*4)
- //temp_is32=1;
- temp_is32&=p32[j];
- }
- if(temp_is32!=current.is32) {
- //printf("dumping 32-bit regs (%x)\n",start+i*4);
- #ifdef DESTRUCTIVE_WRITEBACK
- for(hr=0;hr<HOST_REGS;hr++)
- {
- int r=current.regmap[hr];
- if(r>0&&r<64)
- {
- if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
- temp_is32|=1LL<<r;
- //printf("restore %d\n",r);
- }
+ current.is32|=1LL<<rs2[i-2];
+ int hr=get_reg(current.regmap,rs2[i-2]|64);
+ if(hr>=0) current.regmap[hr]=-1;
}
}
- #endif
- current.is32=temp_is32;
}
}
-#else
current.is32=-1LL;
-#endif
memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
regs[i].wasconst=current.isconst;
regs[i].was32=current.is32;
regs[i].wasdirty=current.dirty;
- #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
- // To change a dirty register from 32 to 64 bits, we must write
- // it out during the previous cycle (for branches, 2 cycles)
- if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
- {
- uint64_t temp_is32=current.is32;
- for(j=i-1;j>=0;j--)
- {
- if(ba[j]==start+i*4+4)
- temp_is32&=branch_regs[j].is32;
- }
- for(j=i;j<slen;j++)
- {
- if(ba[j]==start+i*4+4)
- //temp_is32=1;
- temp_is32&=p32[j];
- }
- if(temp_is32!=current.is32) {
- //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
- for(hr=0;hr<HOST_REGS;hr++)
- {
- int r=current.regmap[hr];
- if(r>0)
- {
- if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
- if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
- {
- if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
- {
- //printf("dump %d/r%d\n",hr,r);
- current.regmap[hr]=-1;
- if(get_reg(current.regmap,r|64)>=0)
- current.regmap[get_reg(current.regmap,r|64)]=-1;
- }
- }
- }
- }
- }
- }
- }
- else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
- {
- uint64_t temp_is32=current.is32;
- for(j=i-1;j>=0;j--)
- {
- if(ba[j]==start+i*4+8)
- temp_is32&=branch_regs[j].is32;
- }
- for(j=i;j<slen;j++)
- {
- if(ba[j]==start+i*4+8)
- //temp_is32=1;
- temp_is32&=p32[j];
- }
- if(temp_is32!=current.is32) {
- //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
- for(hr=0;hr<HOST_REGS;hr++)
- {
- int r=current.regmap[hr];
- if(r>0)
- {
- if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
- if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
- {
- //printf("dump %d/r%d\n",hr,r);
- current.regmap[hr]=-1;
- if(get_reg(current.regmap,r|64)>=0)
- current.regmap[get_reg(current.regmap,r|64)]=-1;
- }
- }
- }
- }
- }
- }
- #endif
+ regs[i].loadedconst=0;
if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
if(i+1<slen) {
current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
current.u|=1;
current.uu|=1;
- } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
+ } else { SysPrintf("oops, branch at end of block with no delay slot\n");exit(1); }
}
is_ds[i]=ds;
if(ds) {
}
} else {
// First instruction expects CCREG to be allocated
- if(i==0&&hr==HOST_CCREG)
+ if(i==0&&hr==HOST_CCREG)
regs[i].regmap_entry[hr]=CCREG;
else
regs[i].regmap_entry[hr]=-1;
clear_const(¤t,rt1[i]);
alloc_cc(¤t,i);
dirty_reg(¤t,CCREG);
- ooo[i]=1;
- delayslot_alloc(¤t,i+1);
if (rt1[i]==31) {
alloc_reg(¤t,i,31);
dirty_reg(¤t,31);
#endif
//current.is32|=1LL<<rt1[i];
}
+ ooo[i]=1;
+ delayslot_alloc(¤t,i+1);
//current.isconst=0; // DEBUG
ds=1;
//printf("i=%d, isconst=%x\n",i,current.isconst);
pagespan_alloc(¤t,i);
break;
}
-
+
// Drop the upper half of registers that have become 32-bit
current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
// Create entry (branch target) regmap
for(hr=0;hr<HOST_REGS;hr++)
{
- int r,or,er;
+ int r,or;
r=current.regmap[hr];
if(r>=0) {
if(r!=regmap_pre[i][hr]) {
}
} else {
// Branches expect CCREG to be allocated at the target
- if(regmap_pre[i][hr]==CCREG)
+ if(regmap_pre[i][hr]==CCREG)
regs[i].regmap_entry[hr]=CCREG;
else
regs[i].regmap_entry[hr]=-1;
}
memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
}
+
+ if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
+ current.waswritten|=1<<rs1[i-1];
+ current.waswritten&=~(1<<rt1[i]);
+ current.waswritten&=~(1<<rt2[i]);
+ if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
+ current.waswritten&=~(1<<rs1[i]);
+
/* Branch post-alloc */
if(i>0)
{
branch_regs[i-1].is32|=1LL<<31;
}
memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
- memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
+ memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
break;
case RJUMP:
memcpy(&branch_regs[i-1],¤t,sizeof(current));
}
#endif
memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
- memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
+ memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
break;
case CJUMP:
if((opcode[i-1]&0x3E)==4) // BEQ/BNE
branch_regs[i-1].isconst=0;
branch_regs[i-1].wasconst=0;
memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
- memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
+ memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
}
else
if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
branch_regs[i-1].isconst=0;
branch_regs[i-1].wasconst=0;
memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
- memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
+ memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
}
else
// Alloc the delay slot in case the branch is taken
branch_regs[i-1].isconst=0;
branch_regs[i-1].wasconst=0;
memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
- memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
+ memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
}
else
// Alloc the delay slot in case the branch is taken
{
cc=0;
}
-#ifdef PCSX
- else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
+#if !defined(DRC_DBG)
+ else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2)
+ {
+ // GTE runs in parallel until accessed, divide by 2 for a rough guess
+ cc+=gte_cycletab[source[i]&0x3f]/2;
+ }
+ else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues
{
cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
}
+ else if(i>1&&itype[i]==STORE&&itype[i-1]==STORE&&itype[i-2]==STORE&&!bt[i])
+ {
+ cc+=4;
+ }
else if(itype[i]==C2LS)
{
cc+=4;
regs[i].is32=current.is32;
regs[i].dirty=current.dirty;
regs[i].isconst=current.isconst;
- memcpy(constmap[i],current.constmap,sizeof(current.constmap));
+ memcpy(constmap[i],current_constmap,sizeof(current_constmap));
}
for(hr=0;hr<HOST_REGS;hr++) {
if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
}
}
if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
+ regs[i].waswritten=current.waswritten;
}
-
+
/* Pass 4 - Cull unused host registers */
-
+
uint64_t nr=0;
-
+
for (i=slen-1;i>=0;i--)
{
int hr;
}
}
// Don't need stuff which is overwritten
- if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
- if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
+ //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
+ //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
// Merge in delay slot
for(hr=0;hr<HOST_REGS;hr++)
{
}
// Save it
needed_reg[i]=nr;
-
+
// Deallocate unneeded registers
for(hr=0;hr<HOST_REGS;hr++)
{
if(likely[i]) {
regs[i].regmap[hr]=-1;
regs[i].isconst&=~(1<<hr);
- if(i<slen-2) regmap_pre[i+2][hr]=-1;
+ if(i<slen-2) {
+ regmap_pre[i+2][hr]=-1;
+ regs[i+2].wasconst&=~(1<<hr);
+ }
}
}
}
d1=dep1[i+1];
d2=dep2[i+1];
}
- if(using_tlb) {
- if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
- itype[i+1]==STORE || itype[i+1]==STORELR ||
- itype[i+1]==C1LS || itype[i+1]==C2LS)
- map=TLREG;
- } else
if(itype[i+1]==STORE || itype[i+1]==STORELR ||
(opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
map=INVCP;
{
if(!likely[i]&&i<slen-2) {
regmap_pre[i+2][hr]=-1;
+ regs[i+2].wasconst&=~(1<<hr);
}
}
}
d1=dep1[i];
d2=dep2[i];
}
- if(using_tlb) {
- if(itype[i]==LOAD || itype[i]==LOADLR ||
- itype[i]==STORE || itype[i]==STORELR ||
- itype[i]==C1LS || itype[i]==C2LS)
- map=TLREG;
- } else if(itype[i]==STORE || itype[i]==STORELR ||
+ if(itype[i]==STORE || itype[i]==STORELR ||
(opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
map=INVCP;
}
if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
{
- printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
+ SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
}
regmap_pre[i+1][hr]=-1;
if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
+ regs[i+1].wasconst&=~(1<<hr);
}
regs[i].regmap[hr]=-1;
regs[i].isconst&=~(1<<hr);
}
}
}
-
+
/* Pass 5 - Pre-allocate registers */
-
+
// If a register is allocated during a loop, try to allocate it for the
// entire loop, if possible. This avoids loading/storing registers
// inside of the loop.
{
if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
{
- if(ba[i]>=start && ba[i]<(start+i*4))
+ if(ba[i]>=start && ba[i]<(start+i*4))
if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
{
int t=(ba[i]-start)>>2;
if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
- if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
+ if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
for(hr=0;hr<HOST_REGS;hr++)
{
if(regs[i].regmap[hr]>64) {
}
}
if(ooo[i]) {
- if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
+ if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
f_regmap[hr]=branch_regs[i].regmap[hr];
}else{
- if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
+ if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
f_regmap[hr]=branch_regs[i].regmap[hr];
}
// Avoid dirty->clean transition
// a mov, which is of negligible benefit. So such cases are
// skipped below.
if(f_regmap[hr]>0) {
- if(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0) {
+ if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
int r=f_regmap[hr];
for(j=t;j<=i;j++)
{
break;
}
// call/ret fast path assumes no registers allocated
- if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
+ if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
break;
}
if(r>63) {
if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
{
if(ooo[j]) {
- if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
+ if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
break;
}else{
- if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
+ if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
break;
}
if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
}
}
}else{
- int count=0;
+ // Non branch or undetermined branch target
for(hr=0;hr<HOST_REGS;hr++)
{
if(hr!=EXCLUDE_REG) {
f_regmap[hr]=regs[i].regmap[hr];
}
}
- else if(regs[i].regmap[hr]<0) count++;
}
}
// Try to restore cycle count at branch targets
regs[k].isconst&=~(1<<HOST_CCREG);
k++;
}
- regs[j].regmap_entry[HOST_CCREG]=CCREG;
+ regs[j].regmap_entry[HOST_CCREG]=CCREG;
}
// Work backwards from the branch target
if(j>i&&f_regmap[HOST_CCREG]==CCREG)
}
}
}
-
+
+ // Cache memory offset or tlb map pointer if a register is available
+ #ifndef HOST_IMM_ADDR32
+ #ifndef RAM_OFFSET
+ if(0)
+ #endif
+ {
+ int earliest_available[HOST_REGS];
+ int loop_start[HOST_REGS];
+ int score[HOST_REGS];
+ int end[HOST_REGS];
+ int reg=ROREG;
+
+ // Init
+ for(hr=0;hr<HOST_REGS;hr++) {
+ score[hr]=0;earliest_available[hr]=0;
+ loop_start[hr]=MAXBLOCK;
+ }
+ for(i=0;i<slen-1;i++)
+ {
+ // Can't do anything if no registers are available
+ if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ score[hr]=0;earliest_available[hr]=i+1;
+ loop_start[hr]=MAXBLOCK;
+ }
+ }
+ if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
+ if(!ooo[i]) {
+ if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ score[hr]=0;earliest_available[hr]=i+1;
+ loop_start[hr]=MAXBLOCK;
+ }
+ }
+ }else{
+ if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ score[hr]=0;earliest_available[hr]=i+1;
+ loop_start[hr]=MAXBLOCK;
+ }
+ }
+ }
+ }
+ // Mark unavailable registers
+ for(hr=0;hr<HOST_REGS;hr++) {
+ if(regs[i].regmap[hr]>=0) {
+ score[hr]=0;earliest_available[hr]=i+1;
+ loop_start[hr]=MAXBLOCK;
+ }
+ if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
+ if(branch_regs[i].regmap[hr]>=0) {
+ score[hr]=0;earliest_available[hr]=i+2;
+ loop_start[hr]=MAXBLOCK;
+ }
+ }
+ }
+ // No register allocations after unconditional jumps
+ if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
+ {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ score[hr]=0;earliest_available[hr]=i+2;
+ loop_start[hr]=MAXBLOCK;
+ }
+ i++; // Skip delay slot too
+ //printf("skip delay slot: %x\n",start+i*4);
+ }
+ else
+ // Possible match
+ if(itype[i]==LOAD||itype[i]==LOADLR||
+ itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ if(hr!=EXCLUDE_REG) {
+ end[hr]=i-1;
+ for(j=i;j<slen-1;j++) {
+ if(regs[j].regmap[hr]>=0) break;
+ if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
+ if(branch_regs[j].regmap[hr]>=0) break;
+ if(ooo[j]) {
+ if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
+ }else{
+ if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
+ }
+ }
+ else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
+ if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
+ int t=(ba[j]-start)>>2;
+ if(t<j&&t>=earliest_available[hr]) {
+ if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
+ // Score a point for hoisting loop invariant
+ if(t<loop_start[hr]) loop_start[hr]=t;
+ //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
+ score[hr]++;
+ end[hr]=j;
+ }
+ }
+ else if(t<j) {
+ if(regs[t].regmap[hr]==reg) {
+ // Score a point if the branch target matches this register
+ score[hr]++;
+ end[hr]=j;
+ }
+ }
+ if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
+ itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
+ score[hr]++;
+ end[hr]=j;
+ }
+ }
+ if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
+ {
+ // Stop on unconditional branch
+ break;
+ }
+ else
+ if(itype[j]==LOAD||itype[j]==LOADLR||
+ itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
+ score[hr]++;
+ end[hr]=j;
+ }
+ }
+ }
+ }
+ // Find highest score and allocate that register
+ int maxscore=0;
+ for(hr=0;hr<HOST_REGS;hr++) {
+ if(hr!=EXCLUDE_REG) {
+ if(score[hr]>score[maxscore]) {
+ maxscore=hr;
+ //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
+ }
+ }
+ }
+ if(score[maxscore]>1)
+ {
+ if(i<loop_start[maxscore]) loop_start[maxscore]=i;
+ for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
+ //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
+ assert(regs[j].regmap[maxscore]<0);
+ if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
+ regs[j].regmap[maxscore]=reg;
+ regs[j].dirty&=~(1<<maxscore);
+ regs[j].wasconst&=~(1<<maxscore);
+ regs[j].isconst&=~(1<<maxscore);
+ if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
+ branch_regs[j].regmap[maxscore]=reg;
+ branch_regs[j].wasdirty&=~(1<<maxscore);
+ branch_regs[j].dirty&=~(1<<maxscore);
+ branch_regs[j].wasconst&=~(1<<maxscore);
+ branch_regs[j].isconst&=~(1<<maxscore);
+ if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
+ regmap_pre[j+2][maxscore]=reg;
+ regs[j+2].wasdirty&=~(1<<maxscore);
+ }
+ // loop optimization (loop_preload)
+ int t=(ba[j]-start)>>2;
+ if(t==loop_start[maxscore]) {
+ if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
+ regs[t].regmap_entry[maxscore]=reg;
+ }
+ }
+ else
+ {
+ if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
+ regmap_pre[j+1][maxscore]=reg;
+ regs[j+1].wasdirty&=~(1<<maxscore);
+ }
+ }
+ }
+ i=j-1;
+ if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
+ for(hr=0;hr<HOST_REGS;hr++) {
+ score[hr]=0;earliest_available[hr]=i+i;
+ loop_start[hr]=MAXBLOCK;
+ }
+ }
+ }
+ }
+ }
+ #endif
+
// This allocates registers (if possible) one instruction prior
// to use, which can avoid a load-use penalty on certain CPUs.
for(i=0;i<slen-1;i++)
}
}
}
+ // Preload target address for load instruction (non-constant)
if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
{
}
}
}
+ // Load source into target register
if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
{
}
}
}
- #ifndef HOST_IMM_ADDR32
- if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
- hr=get_reg(regs[i+1].regmap,TLREG);
- if(hr>=0) {
- int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
- if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
- int nr;
- if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
- {
- regs[i].regmap[hr]=MGEN1+((i+1)&1);
- regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
- regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
- regs[i].isconst&=~(1<<hr);
- regs[i].isconst|=regs[i+1].isconst&(1<<hr);
- constmap[i][hr]=constmap[i+1][hr];
- regs[i+1].wasdirty&=~(1<<hr);
- regs[i].dirty&=~(1<<hr);
- }
- else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
- {
- // move it to another register
- regs[i+1].regmap[hr]=-1;
- regmap_pre[i+2][hr]=-1;
- regs[i+1].regmap[nr]=TLREG;
- regmap_pre[i+2][nr]=TLREG;
- regs[i].regmap[nr]=MGEN1+((i+1)&1);
- regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
- regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
- regs[i].isconst&=~(1<<nr);
- regs[i+1].isconst&=~(1<<nr);
- regs[i].dirty&=~(1<<nr);
- regs[i+1].wasdirty&=~(1<<nr);
- regs[i+1].dirty&=~(1<<nr);
- regs[i+2].wasdirty&=~(1<<nr);
- }
- }
- }
- }
- #endif
+ // Address for store instruction (non-constant)
if(itype[i+1]==STORE||itype[i+1]==STORELR
||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
}
}
if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
- if(itype[i+1]==LOAD)
+ if(itype[i+1]==LOAD)
hr=get_reg(regs[i+1].regmap,rt1[i+1]);
if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
hr=get_reg(regs[i+1].regmap,FTEMP);
}
}
}
-
+
/* Pass 6 - Optimize clean/dirty state */
clean_registers(0,slen-1,1);
-
- /* Pass 7 - Identify 32-bit registers */
-#ifndef FORCE32
- provisional_r32();
- u_int r32=0;
-
+ /* Pass 7 - Identify 32-bit registers */
for (i=slen-1;i>=0;i--)
{
- int hr;
- if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
- {
- if(ba[i]<start || ba[i]>=(start+slen*4))
- {
- // Branch out of this block, don't need anything
- r32=0;
- }
- else
- {
- // Internal branch
- // Need whatever matches the target
- // (and doesn't get overwritten by the delay slot instruction)
- r32=0;
- int t=(ba[i]-start)>>2;
- if(ba[i]>start+i*4) {
- // Forward branch
- if(!(requires_32bit[t]&~regs[i].was32))
- r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
- }else{
- // Backward branch
- //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
- // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
- if(!(pr32[t]&~regs[i].was32))
- r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
- }
- }
- // Conditional branch may need registers for following instructions
- if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
- {
- if(i<slen-2) {
- r32|=requires_32bit[i+2];
- r32&=regs[i].was32;
- // Mark this address as a branch target since it may be called
- // upon return from interrupt
- bt[i+2]=1;
- }
- }
- // Merge in delay slot
- if(!likely[i]) {
- // These are overwritten unless the branch is "likely"
- // and the delay slot is nullified if not taken
- r32&=~(1LL<<rt1[i+1]);
- r32&=~(1LL<<rt2[i+1]);
- }
- // Assume these are needed (delay slot)
- if(us1[i+1]>0)
- {
- if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
- }
- if(us2[i+1]>0)
- {
- if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
- }
- if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
- {
- if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
- }
- if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
- {
- if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
- }
- }
- else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
- {
- // SYSCALL instruction (software interrupt)
- r32=0;
- }
- else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
- {
- // ERET instruction (return from interrupt)
- r32=0;
- }
- // Check 32 bits
- r32&=~(1LL<<rt1[i]);
- r32&=~(1LL<<rt2[i]);
- if(us1[i]>0)
- {
- if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
- }
- if(us2[i]>0)
- {
- if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
- }
- if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
- {
- if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
- }
- if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
- {
- if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
- }
- requires_32bit[i]=r32;
-
- // Dirty registers which are 32-bit, require 32-bit input
- // as they will be written as 32-bit values
- for(hr=0;hr<HOST_REGS;hr++)
+ if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
{
- if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
- if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
- if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
- requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
- }
+ // Conditional branch
+ if((source[i]>>16)!=0x1000&&i<slen-2) {
+ // Mark this address as a branch target since it may be called
+ // upon return from interrupt
+ bt[i+2]=1;
}
}
- //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
}
-#endif
if(itype[slen-1]==SPAN) {
bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
}
-
+
+#ifdef DISASM
/* Debug/disassembly */
- if((void*)assem_debug==(void*)printf)
for(i=0;i<slen;i++)
{
printf("U:");
else printf(" r%d",r);
}
}
-#ifndef FORCE32
- printf(" UU:");
- for(r=1;r<=CCREG;r++) {
- if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
- if(r==HIREG) printf(" HI");
- else if(r==LOREG) printf(" LO");
- else printf(" r%d",r);
- }
- }
- printf(" 32:");
- for(r=0;r<=CCREG;r++) {
- //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
- if((regs[i].was32>>r)&1) {
- if(r==CCREG) printf(" CC");
- else if(r==HIREG) printf(" HI");
- else if(r==LOREG) printf(" LO");
- else printf(" r%d",r);
- }
- }
-#endif
printf("\n");
#if defined(__i386__) || defined(__x86_64__)
printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
if((needed_reg[i]>>5)&1) printf("ebp ");
if((needed_reg[i]>>6)&1) printf("esi ");
if((needed_reg[i]>>7)&1) printf("edi ");
- printf("r:");
- for(r=0;r<=CCREG;r++) {
- //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
- if((requires_32bit[i]>>r)&1) {
- if(r==CCREG) printf(" CC");
- else if(r==HIREG) printf(" HI");
- else if(r==LOREG) printf(" LO");
- else printf(" r%d",r);
- }
- }
printf("\n");
- /*printf("pr:");
- for(r=0;r<=CCREG;r++) {
- //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
- if((pr32[i]>>r)&1) {
- if(r==CCREG) printf(" CC");
- else if(r==HIREG) printf(" HI");
- else if(r==LOREG) printf(" LO");
- else printf(" r%d",r);
- }
- }
- if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
- printf("\n");*/
#if defined(__i386__) || defined(__x86_64__)
printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
printf("dirty: ");
if(regs[i].isconst) {
printf("constants: ");
#if defined(__i386__) || defined(__x86_64__)
- if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
- if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
- if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
- if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
- if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
- if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
- if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
+ if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]);
+ if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]);
+ if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]);
+ if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]);
+ if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]);
+ if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
+ if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
#endif
#ifdef __arm__
- if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
- if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
- if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
- if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
- if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
- if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
- if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
- if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
- if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
- if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
- if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
- if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
+ int r;
+ for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
+ if ((regs[i].isconst >> r) & 1)
+ printf(" r%d=%x", r, (u_int)constmap[i][r]);
#endif
printf("\n");
}
-#ifndef FORCE32
- printf(" 32:");
- for(r=0;r<=CCREG;r++) {
- if((regs[i].is32>>r)&1) {
- if(r==CCREG) printf(" CC");
- else if(r==HIREG) printf(" HI");
- else if(r==LOREG) printf(" LO");
- else printf(" r%d",r);
- }
- }
- printf("\n");
-#endif
- /*printf(" p32:");
- for(r=0;r<=CCREG;r++) {
- if((p32[i]>>r)&1) {
- if(r==CCREG) printf(" CC");
- else if(r==HIREG) printf(" HI");
- else if(r==LOREG) printf(" LO");
- else printf(" r%d",r);
- }
- }
- if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
- else printf("\n");*/
if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
#if defined(__i386__) || defined(__x86_64__)
printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
if((branch_regs[i].dirty>>10)&1) printf("r10 ");
if((branch_regs[i].dirty>>12)&1) printf("r12 ");
#endif
-#ifndef FORCE32
- printf(" 32:");
- for(r=0;r<=CCREG;r++) {
- if((branch_regs[i].is32>>r)&1) {
- if(r==CCREG) printf(" CC");
- else if(r==HIREG) printf(" HI");
- else if(r==LOREG) printf(" LO");
- else printf(" r%d",r);
- }
- }
- printf("\n");
-#endif
}
}
+#endif // DISASM
/* Pass 8 - Assembly */
linkcount=0;stubcount=0;
cop1_usable=0;
uint64_t is32_pre=0;
u_int dirty_pre=0;
- u_int beginning=(u_int)out;
+ void *beginning=start_block();
if((u_int)addr&1) {
ds=1;
pagespan_ds();
}
- u_int instr_addr0_override=0;
+ void *instr_addr0_override = NULL;
-#ifdef PCSX
if (start == 0x80030000) {
// nasty hack for fastbios thing
- instr_addr0_override=(u_int)out;
+ // override block entry to this code
+ instr_addr0_override = out;
emit_movimm(start,0);
- emit_readword((int)&pcaddr,1);
- emit_writeword(0,(int)&pcaddr);
+ // abuse io address var as a flag that we
+ // have already returned here once
+ emit_readword(&address,1);
+ emit_writeword(0,&pcaddr);
+ emit_writeword(0,&address);
emit_cmp(0,1);
- emit_jne((int)new_dyna_leave);
+ emit_jne(new_dyna_leave);
}
-#endif
for(i=0;i<slen;i++)
{
//if(ds) printf("ds: ");
- if((void*)assem_debug==(void*)printf) disassemble_inst(i);
+ disassemble_inst(i);
if(ds) {
ds=0; // Skip delay slot
if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
- instr_addr[i]=0;
+ instr_addr[i] = NULL;
} else {
+ speculate_register_values(i);
#ifndef DESTRUCTIVE_WRITEBACK
if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
{
- wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
- unneeded_reg[i],unneeded_reg_upper[i]);
wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
unneeded_reg[i],unneeded_reg_upper[i]);
}
- is32_pre=regs[i].is32;
- dirty_pre=regs[i].dirty;
+ if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
+ is32_pre=branch_regs[i].is32;
+ dirty_pre=branch_regs[i].dirty;
+ }else{
+ is32_pre=regs[i].is32;
+ dirty_pre=regs[i].dirty;
+ }
#endif
// write back
if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
loop_preload(regmap_pre[i],regs[i].regmap_entry);
}
// branch target entry point
- instr_addr[i]=(u_int)out;
+ instr_addr[i] = out;
assem_debug("<->\n");
+ drc_dbg_emit_do_cmp(i);
+
// load regs
if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
emit_loadreg(CCREG,HOST_CCREG);
- emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
+ emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
}
else if(!likely[i-2])
{
store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
}
- add_to_linker((int)out,start+i*4,0);
+ add_to_linker(out,start+i*4,0);
emit_jmp(0);
}
}
store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
emit_loadreg(CCREG,HOST_CCREG);
- emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
- add_to_linker((int)out,start+i*4,0);
+ emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
+ add_to_linker(out,start+i*4,0);
emit_jmp(0);
}
// Stubs
for(i=0;i<stubcount;i++)
{
- switch(stubs[i][0])
+ switch(stubs[i].type)
{
case LOADB_STUB:
case LOADH_STUB:
/* Pass 9 - Linker */
for(i=0;i<linkcount;i++)
{
- assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
+ assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
literal_pool(64);
- if(!link_addr[i][2])
+ if (!link_addr[i].ext)
{
- void *stub=out;
- void *addr=check_addr(link_addr[i][1]);
- emit_extjump(link_addr[i][0],link_addr[i][1]);
- if(addr) {
- set_jump_target(link_addr[i][0],(int)addr);
- add_link(link_addr[i][1],stub);
+ void *stub = out;
+ void *addr = check_addr(link_addr[i].target);
+ emit_extjump(link_addr[i].addr, link_addr[i].target);
+ if (addr) {
+ set_jump_target(link_addr[i].addr, addr);
+ add_link(link_addr[i].target,stub);
}
- else set_jump_target(link_addr[i][0],(int)stub);
+ else
+ set_jump_target(link_addr[i].addr, stub);
}
else
{
// Internal branch
- int target=(link_addr[i][1]-start)>>2;
+ int target=(link_addr[i].target-start)>>2;
assert(target>=0&&target<slen);
assert(instr_addr[target]);
//#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
- //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
+ //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
//#else
- set_jump_target(link_addr[i][0],instr_addr[target]);
+ set_jump_target(link_addr[i].addr, instr_addr[target]);
//#endif
}
}
u_int page=get_page(vaddr);
u_int vpage=get_vpage(vaddr);
literal_pool(256);
- //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
-#ifndef FORCE32
- if(!requires_32bit[i])
-#else
- if(1)
-#endif
{
- assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
+ assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
assem_debug("jump_in: %x\n",start+i*4);
- ll_add(jump_dirty+vpage,vaddr,(void *)out);
- int entry_point=do_dirty_stub(i);
- ll_add(jump_in+page,vaddr,(void *)entry_point);
+ ll_add(jump_dirty+vpage,vaddr,out);
+ void *entry_point = do_dirty_stub(i);
+ ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
// If there was an existing entry in the hash table,
// replace it with the new address.
// Don't add new entries. We'll insert the
// ones that actually get used in check_addr().
- int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
- if(ht_bin[0]==vaddr) {
- ht_bin[1]=entry_point;
- }
- if(ht_bin[2]==vaddr) {
- ht_bin[3]=entry_point;
- }
- }
- else
- {
- u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
- assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
- assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
- //int entry_point=(int)out;
- ////assem_debug("entry_point: %x\n",entry_point);
- //load_regs_entry(i);
- //if(entry_point==(int)out)
- // entry_point=instr_addr[i];
- //else
- // emit_jmp(instr_addr[i]);
- //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
- ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
- int entry_point=do_dirty_stub(i);
- ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
+ struct ht_entry *ht_bin = hash_table_get(vaddr);
+ if (ht_bin->vaddr[0] == vaddr)
+ ht_bin->tcaddr[0] = entry_point;
+ if (ht_bin->vaddr[1] == vaddr)
+ ht_bin->tcaddr[1] = entry_point;
}
}
}
// Align code
if(((u_int)out)&7) emit_addnop(13);
#endif
- assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
- //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
+ assert((u_int)out-(u_int)beginning<MAX_OUTPUT_BLOCK_SIZE);
+ //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
memcpy(copy,source,slen*4);
copy+=slen*4;
-
- #ifdef __arm__
- __clear_cache((void *)beginning,out);
- #endif
-
+
+ end_block(beginning);
+
// If we're within 256K of the end of the buffer,
// start over from the beginning. (Is 256K enough?)
- if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
-
+ if (out > translation_cache+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE)
+ out = translation_cache;
+
// Trap writes to any of the pages we compiled
for(i=start>>12;i<=(start+slen*4)>>12;i++) {
invalid_code[i]=0;
-#ifndef DISABLE_TLB
- memory_map[i]|=0x40000000;
- if((signed int)start>=(signed int)0xC0000000) {
- assert(using_tlb);
- j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
- invalid_code[j]=0;
- memory_map[j]|=0x40000000;
- //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
- }
-#endif
}
-#ifdef PCSX
- // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
+ inv_code_start=inv_code_end=~0;
+
+ // for PCSX we need to mark all mirrors too
if(get_page(start)<(RAM_SIZE>>12))
for(i=start>>12;i<=(start+slen*4)>>12;i++)
- invalid_code[((u_int)0x80000000>>12)|i]=0;
-#endif
-
+ invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
+ invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
+ invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
+
/* Pass 10 - Free memory by expiring oldest blocks */
-
- int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
+
+ int end=(((out-translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535;
while(expirep!=end)
{
int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
- int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
+ uintptr_t base=(uintptr_t)translation_cache+((expirep>>13)<<shift); // Base address of this block
inv_debug("EXP: Phase %d\n",expirep);
switch((expirep>>11)&3)
{
case 2:
// Clear hash table
for(i=0;i<32;i++) {
- int *ht_bin=hash_table[((expirep&2047)<<5)+i];
- if((ht_bin[3]>>shift)==(base>>shift) ||
- ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
- inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
- ht_bin[2]=ht_bin[3]=-1;
- }
- if((ht_bin[1]>>shift)==(base>>shift) ||
- ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
- inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
- ht_bin[0]=ht_bin[2];
- ht_bin[1]=ht_bin[3];
- ht_bin[2]=ht_bin[3]=-1;
+ struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
+ if (((uintptr_t)ht_bin->tcaddr[1]>>shift) == (base>>shift) ||
+ (((uintptr_t)ht_bin->tcaddr[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
+ inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
+ ht_bin->vaddr[1] = -1;
+ ht_bin->tcaddr[1] = NULL;
+ }
+ if (((uintptr_t)ht_bin->tcaddr[0]>>shift) == (base>>shift) ||
+ (((uintptr_t)ht_bin->tcaddr[0]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
+ inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
+ ht_bin->vaddr[0] = ht_bin->vaddr[1];
+ ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
+ ht_bin->vaddr[1] = -1;
+ ht_bin->tcaddr[1] = NULL;
}
}
break;
case 3:
// Clear jump_out
#ifdef __arm__
- if((expirep&2047)==0)
+ if((expirep&2047)==0)
do_clear_cache();
#endif
ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
notaz.gp2x.de / pcsx_rearmed.git / blobdiff