#include <stdlib.h>
#include <stdint.h> //include for uint64_t
#include <assert.h>
+#include <errno.h>
+#include <sys/mman.h>
#include "emu_if.h" //emulator interface
-#include <sys/mman.h>
+//#define DISASM
+//#define assem_debug printf
+//#define inv_debug printf
+#define assem_debug(...)
+#define inv_debug(...)
#ifdef __i386__
#include "assem_x86.h"
#include "assem_arm.h"
#endif
+#ifdef __BLACKBERRY_QNX__
+#undef __clear_cache
+#define __clear_cache(start,end) msync(start, (size_t)((void*)end - (void*)start), MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
+#elif defined(__MACH__)
+#include <libkern/OSCacheControl.h>
+#define __clear_cache mach_clear_cache
+static void __clear_cache(void *start, void *end) {
+ size_t len = (char *)end - (char *)start;
+ sys_dcache_flush(start, len);
+ sys_icache_invalidate(start, len);
+}
+#endif
+
#define MAXBLOCK 4096
#define MAX_OUTPUT_BLOCK_SIZE 262144
-#define CLOCK_DIVIDER 2
struct regstat
{
uint64_t uu;
u_int wasconst;
u_int isconst;
- uint64_t constmap[HOST_REGS];
+ u_int loadedconst; // host regs that have constants loaded
+ u_int waswritten; // MIPS regs that were used as store base before
};
+// note: asm depends on this layout
struct ll_entry
{
u_int vaddr;
- u_int reg32;
+ u_int reg_sv_flags;
void *addr;
struct ll_entry *next;
};
u_char dep1[MAXBLOCK];
u_char dep2[MAXBLOCK];
u_char lt1[MAXBLOCK];
+ static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
+ static uint64_t gte_rt[MAXBLOCK];
+ static uint64_t gte_unneeded[MAXBLOCK];
+ static u_int smrv[32]; // speculated MIPS register values
+ static u_int smrv_strong; // mask or regs that are likely to have correct values
+ static u_int smrv_weak; // same, but somewhat less likely
+ static u_int smrv_strong_next; // same, but after current insn executes
+ static u_int smrv_weak_next;
int imm[MAXBLOCK];
u_int ba[MAXBLOCK];
char likely[MAXBLOCK];
uint64_t p32[MAXBLOCK];
uint64_t pr32[MAXBLOCK];
signed char regmap_pre[MAXBLOCK][HOST_REGS];
- signed char regmap[MAXBLOCK][HOST_REGS];
- signed char regmap_entry[MAXBLOCK][HOST_REGS];
- uint64_t constmap[MAXBLOCK][HOST_REGS];
- struct regstat regs[MAXBLOCK];
- struct regstat branch_regs[MAXBLOCK];
+ static uint64_t current_constmap[HOST_REGS];
+ static uint64_t constmap[MAXBLOCK][HOST_REGS];
+ static struct regstat regs[MAXBLOCK];
+ static struct regstat branch_regs[MAXBLOCK];
signed char minimum_free_regs[MAXBLOCK];
u_int needed_reg[MAXBLOCK];
uint64_t requires_32bit[MAXBLOCK];
int is_delayslot;
int cop1_usable;
u_char *out;
- struct ll_entry *jump_in[4096];
+ struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
struct ll_entry *jump_out[4096];
struct ll_entry *jump_dirty[4096];
u_int hash_table[65536][4] __attribute__((aligned(16)));
#else
static const u_int using_tlb=0;
#endif
- static u_int sp_in_mirror;
+ int new_dynarec_did_compile;
+ int new_dynarec_hacks;
u_int stop_after_jal;
+#ifndef RAM_FIXED
+ static u_int ram_offset;
+#else
+ static const u_int ram_offset=0;
+#endif
extern u_char restore_candidate[512];
extern int cycle_count;
//#define DEBUG_CYCLE_COUNT 1
-void nullf() {}
-//#define assem_debug printf
-//#define inv_debug printf
-#define assem_debug nullf
-#define inv_debug nullf
+#define NO_CYCLE_PENALTY_THR 12
+
+int cycle_multiplier; // 100 for 1.0
+
+static int CLOCK_ADJUST(int x)
+{
+ int s=(x>>31)|1;
+ return (x * cycle_multiplier + s * 50) / 100;
+}
static void tlb_hacks()
{
return page;
}
+#ifndef PCSX
static u_int get_vpage(u_int vaddr)
{
u_int vpage=(vaddr^0x80000000)>>12;
if(vpage>2048) vpage=2048+(vpage&2047);
return vpage;
}
+#else
+// no virtual mem in PCSX
+static u_int get_vpage(u_int vaddr)
+{
+ return get_page(vaddr);
+}
+#endif
// Get address from virtual address
// This is called from the recompiled JR/JALR instructions
//printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
head=jump_in[page];
while(head!=NULL) {
- if(head->vaddr==vaddr&&head->reg32==0) {
+ if(head->vaddr==vaddr) {
//printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
ht_bin[3]=ht_bin[1];
}
head=jump_dirty[vpage];
while(head!=NULL) {
- if(head->vaddr==vaddr&&head->reg32==0) {
+ if(head->vaddr==vaddr) {
//printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
// Don't restore blocks which are about to expire from the cache
if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
if(verify_dirty(head->addr)) {
//printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
invalid_code[vaddr>>12]=0;
+ inv_code_start=inv_code_end=~0;
+#ifndef DISABLE_TLB
memory_map[vaddr>>12]|=0x40000000;
+#endif
if(vpage<2048) {
#ifndef DISABLE_TLB
if(tlb_LUT_r[vaddr>>12]) {
return get_addr(vaddr);
}
-void *get_addr_32(u_int vaddr,u_int flags)
-{
-#ifdef FORCE32
- return get_addr(vaddr);
-#else
- //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
- int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
- if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
- if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
- u_int page=get_page(vaddr);
- u_int vpage=get_vpage(vaddr);
- struct ll_entry *head;
- head=jump_in[page];
- while(head!=NULL) {
- if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
- //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
- if(head->reg32==0) {
- int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
- if(ht_bin[0]==-1) {
- ht_bin[1]=(int)head->addr;
- ht_bin[0]=vaddr;
- }else if(ht_bin[2]==-1) {
- ht_bin[3]=(int)head->addr;
- ht_bin[2]=vaddr;
- }
- //ht_bin[3]=ht_bin[1];
- //ht_bin[2]=ht_bin[0];
- //ht_bin[1]=(int)head->addr;
- //ht_bin[0]=vaddr;
- }
- return head->addr;
- }
- head=head->next;
- }
- head=jump_dirty[vpage];
- while(head!=NULL) {
- if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
- //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
- // Don't restore blocks which are about to expire from the cache
- if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
- if(verify_dirty(head->addr)) {
- //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
- invalid_code[vaddr>>12]=0;
- memory_map[vaddr>>12]|=0x40000000;
- if(vpage<2048) {
-#ifndef DISABLE_TLB
- if(tlb_LUT_r[vaddr>>12]) {
- invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
- memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
- }
-#endif
- restore_candidate[vpage>>3]|=1<<(vpage&7);
- }
- else restore_candidate[page>>3]|=1<<(page&7);
- if(head->reg32==0) {
- int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
- if(ht_bin[0]==-1) {
- ht_bin[1]=(int)head->addr;
- ht_bin[0]=vaddr;
- }else if(ht_bin[2]==-1) {
- ht_bin[3]=(int)head->addr;
- ht_bin[2]=vaddr;
- }
- //ht_bin[3]=ht_bin[1];
- //ht_bin[2]=ht_bin[0];
- //ht_bin[1]=(int)head->addr;
- //ht_bin[0]=vaddr;
- }
- return head->addr;
- }
- }
- head=head->next;
- }
- //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
- int r=new_recompile_block(vaddr);
- if(r==0) return get_addr(vaddr);
- // Execute in unmapped page, generate pagefault execption
- Status|=2;
- Cause=(vaddr<<31)|0x8;
- EPC=(vaddr&1)?vaddr-5:vaddr;
- BadVAddr=(vaddr&~1);
- Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
- EntryHi=BadVAddr&0xFFFFE000;
- return get_addr_ht(0x80000000);
-#endif
-}
-
void clear_all_regs(signed char regmap[])
{
int hr;
for (hr=0;hr<HOST_REGS;hr++) {
if(cur->regmap[hr]==reg) {
cur->isconst|=1<<hr;
- cur->constmap[hr]=value;
+ current_constmap[hr]=value;
}
else if((cur->regmap[hr]^64)==reg) {
cur->isconst|=1<<hr;
- cur->constmap[hr]=value>>32;
+ current_constmap[hr]=value>>32;
}
}
}
int is_const(struct regstat *cur,signed char reg)
{
int hr;
+ if(reg<0) return 0;
if(!reg) return 1;
for (hr=0;hr<HOST_REGS;hr++) {
if((cur->regmap[hr]&63)==reg) {
if(!reg) return 0;
for (hr=0;hr<HOST_REGS;hr++) {
if(cur->regmap[hr]==reg) {
- return cur->constmap[hr];
+ return current_constmap[hr];
}
}
- printf("Unknown constant in r%d\n",reg);
+ SysPrintf("Unknown constant in r%d\n",reg);
exit(1);
}
}
}
-
+#ifndef FORCE32
void div64(int64_t dividend,int64_t divisor)
{
lo=dividend/divisor;
else original=loaded;
return original;
}
+#endif
#ifdef __i386__
#include "assem_x86.c"
new_entry=malloc(sizeof(struct ll_entry));
assert(new_entry!=NULL);
new_entry->vaddr=vaddr;
- new_entry->reg32=0;
+ new_entry->reg_sv_flags=0;
new_entry->addr=addr;
new_entry->next=*head;
*head=new_entry;
}
-// Add virtual address mapping for 32-bit compiled block
-void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
+void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
{
ll_add(head,vaddr,addr);
-#ifndef FORCE32
- (*head)->reg32=reg32;
-#endif
+ (*head)->reg_sv_flags=reg_sv_flags;
}
// Check if an address is already compiled
struct ll_entry *head;
head=jump_in[page];
while(head!=NULL) {
- if(head->vaddr==vaddr&&head->reg32==0) {
+ if(head->vaddr==vaddr) {
if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
// Update existing entry with current address
if(ht_bin[0]==vaddr) {
head=next;
}
}
-void invalidate_block(u_int block)
+
+static void invalidate_block_range(u_int block, u_int first, u_int last)
{
u_int page=get_page(block<<12);
- u_int vpage=get_vpage(block<<12);
- inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
- //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
- u_int first,last;
- first=last=page;
- struct ll_entry *head;
- head=jump_dirty[vpage];
- //printf("page=%d vpage=%d\n",page,vpage);
- while(head!=NULL) {
- u_int start,end;
- if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
- get_bounds((int)head->addr,&start,&end);
- //printf("start: %x end: %x\n",start,end);
- if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
- if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
- if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
- if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
- }
- }
-#ifndef DISABLE_TLB
- if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
- if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
- if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
- if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
- }
- }
-#endif
- }
- head=head->next;
- }
//printf("first=%d last=%d\n",first,last);
invalidate_page(page);
assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
// Don't trap writes
invalid_code[block]=1;
-#ifdef PCSX
- invalid_code[((u_int)0x80000000>>12)|page]=1;
-#endif
#ifndef DISABLE_TLB
// If there is a valid TLB entry for this page, remove write protect
if(tlb_LUT_w[block]) {
memset(mini_ht,-1,sizeof(mini_ht));
#endif
}
+
+void invalidate_block(u_int block)
+{
+ u_int page=get_page(block<<12);
+ u_int vpage=get_vpage(block<<12);
+ inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
+ //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
+ u_int first,last;
+ first=last=page;
+ struct ll_entry *head;
+ head=jump_dirty[vpage];
+ //printf("page=%d vpage=%d\n",page,vpage);
+ while(head!=NULL) {
+ u_int start,end;
+ if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
+ get_bounds((int)head->addr,&start,&end);
+ //printf("start: %x end: %x\n",start,end);
+ if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
+ if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
+ if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
+ if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
+ }
+ }
+#ifndef DISABLE_TLB
+ if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
+ if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
+ if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
+ if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
+ }
+ }
+#endif
+ }
+ head=head->next;
+ }
+ invalidate_block_range(block,first,last);
+}
+
void invalidate_addr(u_int addr)
{
+#ifdef PCSX
+ //static int rhits;
+ // this check is done by the caller
+ //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
+ u_int page=get_vpage(addr);
+ if(page<2048) { // RAM
+ struct ll_entry *head;
+ u_int addr_min=~0, addr_max=0;
+ u_int mask=RAM_SIZE-1;
+ u_int addr_main=0x80000000|(addr&mask);
+ int pg1;
+ inv_code_start=addr_main&~0xfff;
+ inv_code_end=addr_main|0xfff;
+ pg1=page;
+ if (pg1>0) {
+ // must check previous page too because of spans..
+ pg1--;
+ inv_code_start-=0x1000;
+ }
+ for(;pg1<=page;pg1++) {
+ for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
+ u_int start,end;
+ get_bounds((int)head->addr,&start,&end);
+ if(ram_offset) {
+ start-=ram_offset;
+ end-=ram_offset;
+ }
+ if(start<=addr_main&&addr_main<end) {
+ if(start<addr_min) addr_min=start;
+ if(end>addr_max) addr_max=end;
+ }
+ else if(addr_main<start) {
+ if(start<inv_code_end)
+ inv_code_end=start-1;
+ }
+ else {
+ if(end>inv_code_start)
+ inv_code_start=end;
+ }
+ }
+ }
+ if (addr_min!=~0) {
+ inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
+ inv_code_start=inv_code_end=~0;
+ invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
+ return;
+ }
+ else {
+ inv_code_start=(addr&~mask)|(inv_code_start&mask);
+ inv_code_end=(addr&~mask)|(inv_code_end&mask);
+ inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
+ return;
+ }
+ }
+#endif
invalidate_block(addr>>12);
}
+
// This is called when loading a save state.
// Anything could have changed, so invalidate everything.
void invalidate_all_pages()
{
u_int page=get_page(vaddr);
inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
+ int *ptr=(int *)(src+4);
+ assert((*ptr&0x0fff0000)==0x059f0000);
ll_add(jump_out+page,vaddr,src);
//int ptr=get_pointer(src);
//inv_debug("add_link: Pointer is to %x\n",(int)ptr);
inv|=invalid_code[i];
}
}
+#ifndef DISABLE_TLB
if((signed int)head->vaddr>=(signed int)0xC0000000) {
u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
//printf("addr=%x start=%x end=%x\n",addr,start,end);
if(addr<start||addr>=end) inv=1;
}
+#endif
else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
inv=1;
}
inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
//printf("page=%x, addr=%x\n",page,head->vaddr);
//assert(head->vaddr>>12==(page|0x80000));
- ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
+ ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
- if(!head->reg32) {
- if(ht_bin[0]==head->vaddr) {
- ht_bin[1]=(int)clean_addr; // Replace existing entry
- }
- if(ht_bin[2]==head->vaddr) {
- ht_bin[3]=(int)clean_addr; // Replace existing entry
- }
+ if(ht_bin[0]==head->vaddr) {
+ ht_bin[1]=(int)clean_addr; // Replace existing entry
+ }
+ if(ht_bin[2]==head->vaddr) {
+ ht_bin[3]=(int)clean_addr; // Replace existing entry
}
}
}
void shiftimm_alloc(struct regstat *current,int i)
{
- clear_const(current,rs1[i]);
- clear_const(current,rt1[i]);
if(opcode2[i]<=0x3) // SLL/SRL/SRA
{
if(rt1[i]) {
alloc_reg(current,i,rt1[i]);
current->is32|=1LL<<rt1[i];
dirty_reg(current,rt1[i]);
+ if(is_const(current,rs1[i])) {
+ int v=get_const(current,rs1[i]);
+ if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
+ if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
+ if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
+ }
+ else clear_const(current,rt1[i]);
}
}
+ else
+ {
+ clear_const(current,rs1[i]);
+ clear_const(current,rt1[i]);
+ }
+
if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
{
if(rt1[i]) {
//if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
- if(rt1[i]) {
+ if(rt1[i]&&!((current->u>>rt1[i])&1)) {
alloc_reg(current,i,rt1[i]);
- if(get_reg(current->regmap,rt1[i])<0) {
- // dummy load, but we still need a register to calculate the address
- alloc_reg_temp(current,i,-1);
- minimum_free_regs[i]=1;
- }
+ assert(get_reg(current->regmap,rt1[i])>=0);
if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
{
current->is32&=~(1LL<<rt1[i]);
}
else
{
- // Load to r0 (dummy load)
+ // Load to r0 or unneeded register (dummy load)
// but we still need a register to calculate the address
if(opcode[i]==0x22||opcode[i]==0x26)
{
alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
}
+ // If using TLB, need a register for pointer to the mapping table
+ if(using_tlb) alloc_reg(current,i,TLREG);
alloc_reg_temp(current,i,-1);
minimum_free_regs[i]=1;
if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
case HLECALL:
case SPAN:
assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
- printf("Disabled speculative precompilation\n");
+ SysPrintf("Disabled speculative precompilation\n");
stop_after_jal=1;
break;
case IMM16:
t=get_reg(i_regs->regmap,rt1[i]);
s=get_reg(i_regs->regmap,rs1[i]);
//assert(t>=0);
- if(t>=0){
+ if(t>=0&&!((i_regs->isconst>>t)&1)){
if(rs1[i]==0)
{
emit_zeroreg(t);
int offset;
int jaddr=0;
int memtarget=0,c=0;
+ int fastload_reg_override=0;
u_int hr,reglist=0;
th=get_reg(i_regs->regmap,rt1[i]|64);
tl=get_reg(i_regs->regmap,rt1[i]);
if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
#endif
{
- #ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) {
- emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
- emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
- }
- else
- #endif
- emit_cmpimm(addr,RAM_SIZE);
- jaddr=(int)out;
- #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
- // Hint to branch predictor that the branch is unlikely to be taken
- if(rs1[i]>=28)
- emit_jno_unlikely(0);
- else
- #endif
- emit_jno(0);
+ jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
}
}
+ else if(ram_offset&&memtarget) {
+ emit_addimm(addr,ram_offset,HOST_TEMPREG);
+ fastload_reg_override=HOST_TEMPREG;
+ }
}else{ // using tlb
int x=0;
if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
map=get_reg(i_regs->regmap,TLREG);
assert(map>=0);
+ reglist&=~(1<<map);
map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
}
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
+
emit_movsbl_indexed_tlb(x,a,map,tl);
}
}
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
//#ifdef
//emit_movswl_indexed_tlb(x,tl,map,tl);
//else
gen_tlb_addr_r(a,map);
emit_movswl_indexed(x,a,tl);
}else{
- #ifdef RAM_OFFSET
+ #if 1 //def RAM_OFFSET
emit_movswl_indexed(x,a,tl);
#else
emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
if(!c||memtarget) {
if(!dummy) {
int a=addr;
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
//emit_readword_indexed((int)rdram-0x80000000,addr,tl);
#ifdef HOST_IMM_ADDR32
if(c)
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
+
emit_movzbl_indexed_tlb(x,a,map,tl);
}
}
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
//#ifdef
//emit_movzwl_indexed_tlb(x,tl,map,tl);
//#else
gen_tlb_addr_r(a,map);
emit_movzwl_indexed(x,a,tl);
}else{
- #ifdef RAM_OFFSET
+ #if 1 //def RAM_OFFSET
emit_movzwl_indexed(x,a,tl);
#else
emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
if(!c||memtarget) {
if(!dummy) {
int a=addr;
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
//emit_readword_indexed((int)rdram-0x80000000,addr,tl);
#ifdef HOST_IMM_ADDR32
if(c)
if(!c||memtarget) {
if(!dummy) {
int a=addr;
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(fastload_reg_override) a=fastload_reg_override;
//gen_tlb_addr_r(tl,map);
//if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
//emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
int jaddr=0,jaddr2,type;
int memtarget=0,c=0;
int agr=AGEN1+(i&1);
+ int faststore_reg_override=0;
u_int hr,reglist=0;
th=get_reg(i_regs->regmap,rs2[i]|64);
tl=get_reg(i_regs->regmap,rs2[i]);
else addr=s;
if(!using_tlb) {
if(!c) {
- #ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) {
- emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
- emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
- }
- else
- #endif
+ #ifndef PCSX
#ifdef R29_HACK
// Strmnnrmn's speed hack
if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
#endif
emit_jno(0);
}
+ #else
+ jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
+ #endif
+ }
+ else if(ram_offset&&memtarget) {
+ emit_addimm(addr,ram_offset,HOST_TEMPREG);
+ faststore_reg_override=HOST_TEMPREG;
}
}else{ // using tlb
int x=0;
if (opcode[i]==0x29) x=2; // SH
map=get_reg(i_regs->regmap,TLREG);
assert(map>=0);
+ reglist&=~(1<<map);
map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
}
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(faststore_reg_override) a=faststore_reg_override;
//gen_tlb_addr_w(temp,map);
//emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
emit_writebyte_indexed_tlb(tl,x,a,map,a);
#else
if(!c) a=addr;
#endif
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(faststore_reg_override) a=faststore_reg_override;
//#ifdef
//emit_writehword_indexed_tlb(tl,x,temp,map,temp);
//#else
gen_tlb_addr_w(a,map);
emit_writehword_indexed(tl,x,a);
}else
- emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
+ //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
+ emit_writehword_indexed(tl,x,a);
}
type=STOREH_STUB;
}
if (opcode[i]==0x2B) { // SW
if(!c||memtarget) {
int a=addr;
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(faststore_reg_override) a=faststore_reg_override;
//emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
emit_writeword_indexed_tlb(tl,0,a,map,temp);
}
if (opcode[i]==0x3F) { // SD
if(!c||memtarget) {
int a=addr;
-#ifdef PCSX
- if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
-#endif
+ if(faststore_reg_override) a=faststore_reg_override;
if(rs2[i]) {
assert(th>=0);
//emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
}
type=STORED_STUB;
}
- if(!using_tlb) {
+#ifdef PCSX
+ if(jaddr) {
+ // PCSX store handlers don't check invcode again
+ reglist|=1<<addr;
+ add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
+ jaddr=0;
+ }
+#endif
+ if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
if(!c||memtarget) {
#ifdef DESTRUCTIVE_SHIFT
// The x86 shift operation is 'destructive'; it overwrites the
#endif
}
}
+ u_int addr_val=constmap[i][s]+offset;
if(jaddr) {
add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
} else if(c&&!memtarget) {
- inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
+ inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
+ }
+ // basic current block modification detection..
+ // not looking back as that should be in mips cache already
+ if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
+ SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
+ assert(i_regs->regmap==regs[i].regmap); // not delay slot
+ if(i_regs->regmap==regs[i].regmap) {
+ load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
+ wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
+ emit_movimm(start+i*4+4,0);
+ emit_writeword(0,(int)&pcaddr);
+ emit_jmp((int)do_interrupt);
+ }
}
//if(opcode[i]==0x2B || opcode[i]==0x3F)
//if(opcode[i]==0x2B || opcode[i]==0x28)
//if(opcode[i]==0x2B)
/*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
{
- //emit_pusha();
+ #ifdef __i386__
+ emit_pusha();
+ #endif
+ #ifdef __arm__
save_regs(0x100f);
+ #endif
emit_readword((int)&last_count,ECX);
#ifdef __i386__
if(get_reg(i_regs->regmap,CCREG)<0)
emit_writeword(0,(int)&Count);
#endif
emit_call((int)memdebug);
- //emit_popa();
+ #ifdef __i386__
+ emit_popa();
+ #endif
+ #ifdef __arm__
restore_regs(0x100f);
+ #endif
}/**/
}
}else{ // using tlb
int map=get_reg(i_regs->regmap,TLREG);
assert(map>=0);
+ reglist&=~(1<<map);
map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
if(!c&&!offset&&s>=0) emit_mov(s,temp);
do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
}
if(!c||!memtarget)
add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
- if(!using_tlb) {
+ if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
#ifdef RAM_OFFSET
int map=get_reg(i_regs->regmap,ROREG);
if(map<0) map=HOST_TEMPREG;
{
map=get_reg(i_regs->regmap,TLREG);
assert(map>=0);
+ reglist&=~(1<<map);
if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
}
emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
type=STORED_STUB;
}
- if(!using_tlb) {
+ if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
#ifndef DESTRUCTIVE_SHIFT
temp=offset||c||s<0?ar:s;
int memtarget=0,c=0;
int jaddr2=0,jaddr3,type;
int agr=AGEN1+(i&1);
+ int fastio_reg_override=0;
u_int hr,reglist=0;
u_int copr=(source[i]>>16)&0x1f;
s=get_reg(i_regs->regmap,rs1[i]);
}
else {
if(!c) {
- emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
- jaddr2=(int)out;
- emit_jno(0);
+ jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
+ }
+ else if(ram_offset&&memtarget) {
+ emit_addimm(ar,ram_offset,HOST_TEMPREG);
+ fastio_reg_override=HOST_TEMPREG;
}
if (opcode[i]==0x32) { // LWC2
#ifdef HOST_IMM_ADDR32
if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
else
#endif
- emit_readword_indexed(0,ar,tl);
+ int a=ar;
+ if(fastio_reg_override) a=fastio_reg_override;
+ emit_readword_indexed(0,a,tl);
}
if (opcode[i]==0x3a) { // SWC2
#ifdef DESTRUCTIVE_SHIFT
if(!offset&&!c&&s>=0) emit_mov(s,ar);
#endif
- emit_writeword_indexed(tl,0,ar);
+ int a=ar;
+ if(fastio_reg_override) a=fastio_reg_override;
+ emit_writeword_indexed(tl,0,a);
}
}
if(jaddr2)
add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
- if (opcode[i]==0x3a) { // SWC2
+ if(opcode[i]==0x3a) // SWC2
+ if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
#if defined(HOST_IMM8)
int ir=get_reg(i_regs->regmap,INVCP);
assert(ir>=0);
assert(ccreg==HOST_CCREG);
assert(!is_delayslot);
emit_movimm(start+i*4,EAX); // Get PC
- emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
+ emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
emit_jmp((int)jump_syscall_hle); // XXX
}
assert(!is_delayslot);
emit_movimm(start+i*4+4,0); // Get PC
emit_movimm((int)psxHLEt[source[i]&7],1);
- emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
+ emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
emit_jmp((int)jump_hlecall);
}
assert(ccreg==HOST_CCREG);
assert(!is_delayslot);
emit_movimm(start+i*4,0); // Get PC
- emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
+ emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
emit_jmp((int)jump_intcall);
}
void ds_assemble(int i,struct regstat *i_regs)
{
+ speculate_register_values(i);
is_delayslot=1;
switch(itype[i]) {
case ALU:
case CJUMP:
case SJUMP:
case FJUMP:
- printf("Jump in the delay slot. This is probably a bug.\n");
+ SysPrintf("Jump in the delay slot. This is probably a bug.\n");
}
is_delayslot=0;
}
// printf("poor load scheduling!\n");
}
else if(c) {
+#ifndef DISABLE_TLB
if(rm>=0) {
if(!entry||entry[rm]!=mgr) {
if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
}
}
}
+#endif
if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
if(!entry||entry[ra]!=agr) {
if (opcode[i]==0x22||opcode[i]==0x26) {
(using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
#endif
emit_movimm(constmap[i][rs]+offset,ra);
+ regs[i].loadedconst|=1<<ra;
}
} // else did it in the previous cycle
} // else load_consts already did it
// Preload constants for next instruction
if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
int agr,ra;
- #ifndef HOST_IMM_ADDR32
+ #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
// Mapper entry
agr=MGEN1+((i+1)&1);
ra=get_reg(i_regs->regmap,agr);
(using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
#endif
emit_movimm(constmap[i+1][rs]+offset,ra);
+ regs[i+1].loadedconst|=1<<ra;
}
}
else if(rs1[i+1]==0) {
// Load registers with known constants
void load_consts(signed char pre[],signed char regmap[],int is32,int i)
{
- int hr;
+ int hr,hr2;
+ // propagate loaded constant flags
+ if(i==0||bt[i])
+ regs[i].loadedconst=0;
+ else {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
+ &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
+ {
+ regs[i].loadedconst|=1<<hr;
+ }
+ }
+ }
// Load 32-bit regs
for(hr=0;hr<HOST_REGS;hr++) {
if(hr!=EXCLUDE_REG&®map[hr]>=0) {
//if(entry[hr]!=regmap[hr]) {
- if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
+ if(!((regs[i].loadedconst>>hr)&1)) {
if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
- int value;
+ int value,similar=0;
if(get_final_value(hr,i,&value)) {
- if(value==0) {
+ // see if some other register has similar value
+ for(hr2=0;hr2<HOST_REGS;hr2++) {
+ if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
+ if(is_similar_value(value,constmap[i][hr2])) {
+ similar=1;
+ break;
+ }
+ }
+ }
+ if(similar) {
+ int value2;
+ if(get_final_value(hr2,i,&value2)) // is this needed?
+ emit_movimm_from(value2,hr2,value,hr);
+ else
+ emit_movimm(value,hr);
+ }
+ else if(value==0) {
emit_zeroreg(hr);
}
else {
emit_movimm(value,hr);
}
}
+ regs[i].loadedconst|=1<<hr;
}
}
}
emit_zeroreg(hr);
}
else
- if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
+ if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
{
emit_loadreg(i_regmap[hr],hr);
}
emit_zeroreg(hr);
}
else
- if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
+ if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
{
emit_loadreg(i_regmap[hr],hr);
}
void load_regs_entry(int t)
{
int hr;
- if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
- else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
+ if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
+ else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
emit_storereg(CCREG,HOST_CCREG);
}
// Load 32-bit regs
for(hr=0;hr<HOST_REGS;hr++) {
- if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
+ if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
if(regs[t].regmap_entry[hr]==0) {
emit_zeroreg(hr);
}
}
// Load 64-bit regs
for(hr=0;hr<HOST_REGS;hr++) {
- if(regs[t].regmap_entry[hr]>=64) {
+ if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
assert(regs[t].regmap_entry[hr]!=64);
if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
}
// Load 32-bit regs
for(hr=0;hr<HOST_REGS;hr++) {
- if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
+ if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
#ifdef DESTRUCTIVE_WRITEBACK
if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
#else
}
//Load 64-bit regs
for(hr=0;hr<HOST_REGS;hr++) {
- if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64) {
+ if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
assert(regs[t].regmap_entry[hr]!=64);
if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
{
if(i_regmap[hr]!=regs[t].regmap_entry[hr])
{
- if(regs[t].regmap_entry[hr]!=-1)
+ if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
{
return 0;
}
else
if((i_dirty>>hr)&1)
{
- if(i_regmap[hr]<64)
+ if(i_regmap[hr]<TEMPREG)
{
if(!((unneeded_reg[t]>>i_regmap[hr])&1))
return 0;
}
- else
+ else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
{
if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
return 0;
case CJUMP:
case SJUMP:
case FJUMP:
- printf("Jump in the delay slot. This is probably a bug.\n");
+ SysPrintf("Jump in the delay slot. This is probably a bug.\n");
}
store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
int count;
int jaddr;
int idle=0;
+ int t=0;
if(itype[i]==RJUMP)
{
*adj=0;
//if(ba[i]>=start && ba[i]<(start+slen*4))
if(internal_branch(branch_regs[i].is32,ba[i]))
{
- int t=(ba[i]-start)>>2;
+ t=(ba[i]-start)>>2;
if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
else *adj=ccadj[t];
}
emit_jmp(0);
}
else if(*adj==0||invert) {
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
+ int cycles=CLOCK_ADJUST(count+2);
+ // faster loop HACK
+ if (t&&*adj) {
+ int rel=t-i;
+ if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
+ cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
+ }
+ emit_addimm_and_set_flags(cycles,HOST_CCREG);
jaddr=(int)out;
emit_jns(0);
}
else
{
- emit_cmpimm(HOST_CCREG,-2*(count+2));
+ emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
jaddr=(int)out;
emit_jns(0);
}
}
emit_writeword(r,(int)&pcaddr);
}
- else {printf("Unknown branch type in do_ccstub\n");exit(1);}
+ else {SysPrintf("Unknown branch type in do_ccstub\n");exit(1);}
}
// Update cycle count
assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
- if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
+ if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
emit_call((int)cc_interrupt);
- if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
+ if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
if(stubs[n][6]==TAKEN) {
if(internal_branch(branch_regs[i].is32,ba[i]))
load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
linkcount++;
}
+static void ujump_assemble_write_ra(int i)
+{
+ int rt;
+ unsigned int return_address;
+ rt=get_reg(branch_regs[i].regmap,31);
+ assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
+ //assert(rt>=0);
+ return_address=start+i*4+8;
+ if(rt>=0) {
+ #ifdef USE_MINI_HT
+ if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
+ int temp=-1; // note: must be ds-safe
+ #ifdef HOST_TEMPREG
+ temp=HOST_TEMPREG;
+ #endif
+ if(temp>=0) do_miniht_insert(return_address,rt,temp);
+ else emit_movimm(return_address,rt);
+ }
+ else
+ #endif
+ {
+ #ifdef REG_PREFETCH
+ if(temp>=0)
+ {
+ if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
+ }
+ #endif
+ emit_movimm(return_address,rt); // PC into link register
+ #ifdef IMM_PREFETCH
+ emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
+ #endif
+ }
+ }
+}
+
void ujump_assemble(int i,struct regstat *i_regs)
{
signed char *i_regmap=i_regs->regmap;
+ int ra_done=0;
if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
address_generation(i+1,i_regs,regs[i].regmap_entry);
#ifdef REG_PREFETCH
if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
}
#endif
- if(rt1[i]==31) {
- int rt;
- unsigned int return_address;
- rt=get_reg(branch_regs[i].regmap,31);
- assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
- //assert(rt>=0);
- return_address=start+i*4+8;
- if(rt>=0) {
- #ifdef USE_MINI_HT
- if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
- int temp=-1; // note: must be ds-safe
- #ifdef HOST_TEMPREG
- temp=HOST_TEMPREG;
- #endif
- if(temp>=0) do_miniht_insert(return_address,rt,temp);
- else emit_movimm(return_address,rt);
- }
- else
- #endif
- {
- #ifdef REG_PREFETCH
- if(temp>=0)
- {
- if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
- }
- #endif
- emit_movimm(return_address,rt); // PC into link register
- #ifdef IMM_PREFETCH
- emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
- #endif
- }
- }
+ if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
+ ujump_assemble_write_ra(i); // writeback ra for DS
+ ra_done=1;
}
ds_assemble(i+1,i_regs);
uint64_t bc_unneeded=branch_regs[i].u;
wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
bc_unneeded,bc_unneeded_upper);
load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
+ if(!ra_done&&rt1[i]==31)
+ ujump_assemble_write_ra(i);
int cc,adj;
cc=get_reg(branch_regs[i].regmap,CCREG);
assert(cc==HOST_CCREG);
if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
#endif
do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
- if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
if(internal_branch(branch_regs[i].is32,ba[i]))
assem_debug("branch: internal\n");
}
}
+static void rjump_assemble_write_ra(int i)
+{
+ int rt,return_address;
+ assert(rt1[i+1]!=rt1[i]);
+ assert(rt2[i+1]!=rt1[i]);
+ rt=get_reg(branch_regs[i].regmap,rt1[i]);
+ assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
+ assert(rt>=0);
+ return_address=start+i*4+8;
+ #ifdef REG_PREFETCH
+ if(temp>=0)
+ {
+ if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
+ }
+ #endif
+ emit_movimm(return_address,rt); // PC into link register
+ #ifdef IMM_PREFETCH
+ emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
+ #endif
+}
+
void rjump_assemble(int i,struct regstat *i_regs)
{
signed char *i_regmap=i_regs->regmap;
int temp;
int rs,cc,adj;
+ int ra_done=0;
rs=get_reg(branch_regs[i].regmap,rs1[i]);
assert(rs>=0);
if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
if(rh>=0) do_preload_rhash(rh);
}
#endif
+ if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
+ rjump_assemble_write_ra(i);
+ ra_done=1;
+ }
ds_assemble(i+1,i_regs);
uint64_t bc_unneeded=branch_regs[i].u;
uint64_t bc_unneeded_upper=branch_regs[i].uu;
wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
bc_unneeded,bc_unneeded_upper);
load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
- if(rt1[i]!=0) {
- int rt,return_address;
- assert(rt1[i+1]!=rt1[i]);
- assert(rt2[i+1]!=rt1[i]);
- rt=get_reg(branch_regs[i].regmap,rt1[i]);
- assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
- assert(rt>=0);
- return_address=start+i*4+8;
- #ifdef REG_PREFETCH
- if(temp>=0)
- {
- if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
- }
- #endif
- emit_movimm(return_address,rt); // PC into link register
- #ifdef IMM_PREFETCH
- emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
- #endif
- }
+ if(!ra_done&&rt1[i]!=0)
+ rjump_assemble_write_ra(i);
cc=get_reg(branch_regs[i].regmap,CCREG);
assert(cc==HOST_CCREG);
#ifdef USE_MINI_HT
//do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
//if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
//assert(adj==0);
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
+#ifdef PCSX
+ if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
+ // special case for RFE
+ emit_jmp(0);
+ else
+#endif
emit_jns(0);
//load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
#ifdef USE_MINI_HT
if(unconditional) {
do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
- if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
if(internal)
assem_debug("branch: internal\n");
}
}
else if(nop) {
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
int jaddr=(int)out;
emit_jns(0);
add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
else {
int taken=0,nottaken=0,nottaken1=0;
do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
- if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
if(!only32)
{
assert(s1h>=0);
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
if(adj) {
- emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
+ emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
add_to_linker((int)out,ba[i],internal);
}else{
emit_addnop(13);
}else
#endif
{
- if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
+ if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
if(internal)
if(nottaken1) set_jump_target(nottaken1,(int)out);
if(adj) {
- if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
+ if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
}
} // (!unconditional)
} // if(ooo)
store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
assem_debug("cycle count (adj)\n");
- if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
if(internal)
assem_debug("branch: internal\n");
if(cc==-1&&!likely[i]) {
// Cycle count isn't in a register, temporarily load it then write it out
emit_loadreg(CCREG,HOST_CCREG);
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
int jaddr=(int)out;
emit_jns(0);
add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
else{
cc=get_reg(i_regmap,CCREG);
assert(cc==HOST_CCREG);
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
int jaddr=(int)out;
emit_jns(0);
add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
if(unconditional) {
do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
- if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
if(internal)
assem_debug("branch: internal\n");
}
}
else if(nevertaken) {
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
int jaddr=(int)out;
emit_jns(0);
add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
else {
int nottaken=0;
do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
- if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
if(!only32)
{
assert(s1h>=0);
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
if(adj) {
- emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
+ emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
add_to_linker((int)out,ba[i],internal);
}else{
emit_addnop(13);
}else
#endif
{
- if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
+ if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
if(internal)
}
if(adj) {
- if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
+ if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
}
} // (!unconditional)
} // if(ooo)
store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
assem_debug("cycle count (adj)\n");
- if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
if(internal)
assem_debug("branch: internal\n");
if(cc==-1&&!likely[i]) {
// Cycle count isn't in a register, temporarily load it then write it out
emit_loadreg(CCREG,HOST_CCREG);
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
int jaddr=(int)out;
emit_jns(0);
add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
else{
cc=get_reg(i_regmap,CCREG);
assert(cc==HOST_CCREG);
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
int jaddr=(int)out;
emit_jns(0);
add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
assem_debug("cycle count (adj)\n");
if(1) {
int nottaken=0;
- if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
if(1) {
assert(fs>=0);
emit_testimm(fs,0x800000);
} // if(!only32)
if(invert) {
- if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
+ if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
else if(match) emit_addnop(13);
#endif
}
if(adj) {
- if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
+ if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
}
} // (!unconditional)
} // if(ooo)
store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
assem_debug("cycle count (adj)\n");
- if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
+ if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
if(internal)
assem_debug("branch: internal\n");
if(cc==-1&&!likely[i]) {
// Cycle count isn't in a register, temporarily load it then write it out
emit_loadreg(CCREG,HOST_CCREG);
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
int jaddr=(int)out;
emit_jns(0);
add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
else{
cc=get_reg(i_regmap,CCREG);
assert(cc==HOST_CCREG);
- emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
+ emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
int jaddr=(int)out;
emit_jns(0);
add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
}
- emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
+ emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
if(opcode[i]==2) // J
{
unconditional=1;
case CJUMP:
case SJUMP:
case FJUMP:
- printf("Jump in the delay slot. This is probably a bug.\n");
+ SysPrintf("Jump in the delay slot. This is probably a bug.\n");
}
int btaddr=get_reg(regs[0].regmap,BTREG);
if(btaddr<0) {
void unneeded_registers(int istart,int iend,int r)
{
int i;
- uint64_t u,uu,b,bu;
- uint64_t temp_u,temp_uu;
+ uint64_t u,uu,gte_u,b,bu,gte_bu;
+ uint64_t temp_u,temp_uu,temp_gte_u=0;
uint64_t tdep;
+ uint64_t gte_u_unknown=0;
+ if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
+ gte_u_unknown=~0ll;
if(iend==slen-1) {
u=1;uu=1;
+ gte_u=gte_u_unknown;
}else{
u=unneeded_reg[iend+1];
uu=unneeded_reg_upper[iend+1];
u=1;uu=1;
+ gte_u=gte_unneeded[iend+1];
}
+
for (i=iend;i>=istart;i--)
{
//printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
// Branch out of this block, flush all regs
u=1;
uu=1;
+ gte_u=gte_u_unknown;
/* Hexagon hack
if(itype[i]==UJUMP&&rt1[i]==31)
{
uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
u|=1;uu|=1;
+ gte_u|=gte_rt[i+1];
+ gte_u&=~gte_rs[i+1];
// If branch is "likely" (and conditional)
// then we skip the delay slot on the fall-thru path
if(likely[i]) {
if(i<slen-1) {
u&=unneeded_reg[i+2];
uu&=unneeded_reg_upper[i+2];
+ gte_u&=gte_unneeded[i+2];
}
else
{
u=1;
uu=1;
+ gte_u=gte_u_unknown;
}
}
}
{
// Unconditional branch
temp_u=1;temp_uu=1;
+ temp_gte_u=0;
} else {
// Conditional branch (not taken case)
temp_u=unneeded_reg[i+2];
temp_uu=unneeded_reg_upper[i+2];
+ temp_gte_u&=gte_unneeded[i+2];
}
// Merge in delay slot
tdep=(~temp_uu>>rt1[i+1])&1;
temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
temp_u|=1;temp_uu|=1;
+ temp_gte_u|=gte_rt[i+1];
+ temp_gte_u&=~gte_rs[i+1];
// If branch is "likely" (and conditional)
// then we skip the delay slot on the fall-thru path
if(likely[i]) {
if(i<slen-1) {
temp_u&=unneeded_reg[i+2];
temp_uu&=unneeded_reg_upper[i+2];
+ temp_gte_u&=gte_unneeded[i+2];
}
else
{
temp_u=1;
temp_uu=1;
+ temp_gte_u=gte_u_unknown;
}
}
tdep=(~temp_uu>>rt1[i])&1;
temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
temp_u|=1;temp_uu|=1;
+ temp_gte_u|=gte_rt[i];
+ temp_gte_u&=~gte_rs[i];
unneeded_reg[i]=temp_u;
unneeded_reg_upper[i]=temp_uu;
+ gte_unneeded[i]=temp_gte_u;
// Only go three levels deep. This recursion can take an
// excessive amount of time if there are a lot of nested loops.
if(r<2) {
}else{
unneeded_reg[(ba[i]-start)>>2]=1;
unneeded_reg_upper[(ba[i]-start)>>2]=1;
+ gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
}
} /*else*/ if(1) {
if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
// Unconditional branch
u=unneeded_reg[(ba[i]-start)>>2];
uu=unneeded_reg_upper[(ba[i]-start)>>2];
+ gte_u=gte_unneeded[(ba[i]-start)>>2];
branch_unneeded_reg[i]=u;
branch_unneeded_reg_upper[i]=uu;
//u=1;
uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
u|=1;uu|=1;
+ gte_u|=gte_rt[i+1];
+ gte_u&=~gte_rs[i+1];
} else {
// Conditional branch
b=unneeded_reg[(ba[i]-start)>>2];
bu=unneeded_reg_upper[(ba[i]-start)>>2];
+ gte_bu=gte_unneeded[(ba[i]-start)>>2];
branch_unneeded_reg[i]=b;
branch_unneeded_reg_upper[i]=bu;
//b=1;
bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
b|=1;bu|=1;
+ gte_bu|=gte_rt[i+1];
+ gte_bu&=~gte_rs[i+1];
// If branch is "likely" then we skip the
// delay slot on the fall-thru path
if(likely[i]) {
u=b;
uu=bu;
+ gte_u=gte_bu;
if(i<slen-1) {
u&=unneeded_reg[i+2];
uu&=unneeded_reg_upper[i+2];
+ gte_u&=gte_unneeded[i+2];
//u=1;
//uu=1;
}
} else {
u&=b;
uu&=bu;
+ gte_u&=gte_bu;
//u=1;
//uu=1;
}
u|=1LL<<rt2[i];
uu|=1LL<<rt1[i];
uu|=1LL<<rt2[i];
+ gte_u|=gte_rt[i];
// Accessed registers are needed
u&=~(1LL<<rs1[i]);
u&=~(1LL<<rs2[i]);
uu&=~(1LL<<us1[i]);
uu&=~(1LL<<us2[i]);
+ gte_u&=~gte_rs[i];
+ if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
+ gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
// Source-target dependencies
uu&=~(tdep<<dep1[i]);
uu&=~(tdep<<dep2[i]);
// Save it
unneeded_reg[i]=u;
unneeded_reg_upper[i]=uu;
+ gte_unneeded[i]=gte_u;
/*
printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
printf("U:");
will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
}
+ if(branch_regs[i].regmap[r]>=0) {
+ will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
+ wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
+ }
}
}
//}
//if(ba[i]>start+i*4) { // Disable recursion (for debugging)
for(r=0;r<HOST_REGS;r++) {
if(r!=EXCLUDE_REG) {
- if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
+ signed char target_reg=branch_regs[i].regmap[r];
+ if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
}
- else
- {
- will_dirty_i&=~(1<<r);
+ else if(target_reg>=0) {
+ will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
+ wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
}
// Treat delay slot as part of branch too
/*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
}
}
}
- // Merge in delay slot
+ // Merge in delay slot (won't dirty)
for(r=0;r<HOST_REGS;r++) {
if(r!=EXCLUDE_REG) {
if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
regs[i].wasdirty|=will_dirty_i&(1<<r);
}
}
- else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
+ else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
// Register moved to a different register
will_dirty_i&=~(1<<r);
wont_dirty_i&=~(1<<r);
}
}
+#ifdef DISASM
/* disassembly */
void disassemble_inst(int i)
{
printf (" %x: %s\n",start+i*4,insn[i]);
}
}
+#else
+static void disassemble_inst(int i) {}
+#endif // DISASM
+
+#define DRC_TEST_VAL 0x74657374
+
+static int new_dynarec_test(void)
+{
+ int (*testfunc)(void) = (void *)out;
+ int ret;
+ emit_movimm(DRC_TEST_VAL,0); // test
+ emit_jmpreg(14);
+ literal_pool(0);
+#ifdef __arm__
+ __clear_cache((void *)testfunc, out);
+#endif
+ SysPrintf("testing if we can run recompiled code..\n");
+ ret = testfunc();
+ if (ret == DRC_TEST_VAL)
+ SysPrintf("test passed.\n");
+ else
+ SysPrintf("test failed: %08x\n", ret);
+ out=(u_char *)BASE_ADDR;
+ return ret == DRC_TEST_VAL;
+}
// clear the state completely, instead of just marking
// things invalid like invalidate_all_pages() does
pending_exception=0;
literalcount=0;
stop_after_jal=0;
+ inv_code_start=inv_code_end=~0;
// TLB
#ifndef DISABLE_TLB
using_tlb=0;
-#endif
- sp_in_mirror=0;
for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
memory_map[n]=-1;
for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
memory_map[n]=((u_int)rdram-0x80000000)>>2;
for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
memory_map[n]=-1;
+#endif
for(n=0;n<4096;n++) ll_clear(jump_in+n);
for(n=0;n<4096;n++) ll_clear(jump_out+n);
for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
void new_dynarec_init()
{
- printf("Init new dynarec\n");
+ SysPrintf("Init new dynarec\n");
out=(u_char *)BASE_ADDR;
+#if BASE_ADDR_FIXED
if (mmap (out, 1<<TARGET_SIZE_2,
PROT_READ | PROT_WRITE | PROT_EXEC,
MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
- -1, 0) <= 0) {printf("mmap() failed\n");}
+ -1, 0) <= 0) {
+ SysPrintf("mmap() failed: %s\n", strerror(errno));
+ }
+#else
+ // not all systems allow execute in data segment by default
+ if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
+ SysPrintf("mprotect() failed: %s\n", strerror(errno));
+#endif
#ifdef MUPEN64
rdword=&readmem_dword;
fake_pc.f.r.rs=&readmem_dword;
fake_pc.f.r.rd=&readmem_dword;
#endif
int n;
+ cycle_multiplier=200;
new_dynarec_clear_full();
#ifdef HOST_IMM8
// Copy this into local area so we don't have to put it in every literal pool
#endif
tlb_hacks();
arch_init();
+ new_dynarec_test();
+#ifndef RAM_FIXED
+ ram_offset=(u_int)rdram-0x80000000;
+#endif
+ if (ram_offset!=0)
+ SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
}
void new_dynarec_cleanup()
{
int n;
- if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
+ #if BASE_ADDR_FIXED
+ if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {SysPrintf("munmap() failed\n");}
+ #endif
for(n=0;n<4096;n++) ll_clear(jump_in+n);
for(n=0;n<4096;n++) ll_clear(jump_out+n);
for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
#ifdef ROM_COPY
- if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
+ if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
#endif
}
//rlist();
start = (u_int)addr&~3;
//assert(((u_int)addr&1)==0);
+ new_dynarec_did_compile=1;
#ifdef PCSX
- if(!sp_in_mirror&&(signed int)(psxRegs.GPR.n.sp&0xffe00000)>0x80200000&&
- 0x10000<=psxRegs.GPR.n.sp&&(psxRegs.GPR.n.sp&~0xe0e00000)<RAM_SIZE) {
- printf("SP hack enabled (%08x), @%08x\n", psxRegs.GPR.n.sp, psxRegs.pc);
- sp_in_mirror=1;
- }
if (Config.HLE && start == 0x80001000) // hlecall
{
// XXX: is this enough? Maybe check hleSoftCall?
emit_movimm(start,0);
emit_writeword(0,(int)&pcaddr);
emit_jmp((int)new_dyna_leave);
+ literal_pool(0);
#ifdef __arm__
__clear_cache((void *)beginning,out);
#endif
}
#endif
else {
- printf("Compile at bogus memory address: %x \n", (int)addr);
+ SysPrintf("Compile at bogus memory address: %x \n", (int)addr);
exit(1);
}
case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
+#ifndef FORCE32
case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
+#endif
case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
#endif
#ifdef PCSX
case 0x12: strcpy(insn[i],"COP2"); type=NI;
- // note: COP MIPS-1 encoding differs from MIPS32
op2=(source[i]>>21)&0x1f;
- if (source[i]&0x3f) {
+ //if (op2 & 0x10) {
+ if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
if (gte_handlers[source[i]&0x3f]!=NULL) {
- snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
+ if (gte_regnames[source[i]&0x3f]!=NULL)
+ strcpy(insn[i],gte_regnames[source[i]&0x3f]);
+ else
+ snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
type=C2OP;
}
}
case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
#endif
default: strcpy(insn[i],"???"); type=NI;
- printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
+ SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
break;
}
itype[i]=type;
us2[i]=0;
dep1[i]=0;
dep2[i]=0;
+ gte_rs[i]=gte_rt[i]=0;
switch(type) {
case LOAD:
rs1[i]=(source[i]>>21)&0x1f;
if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
break;
case COP1:
- case COP2:
rs1[i]=0;
rs2[i]=0;
rt1[i]=0;
if(op2==5) us1[i]=rs1[i]; // DMTC1
rs2[i]=CSREG;
break;
+ case COP2:
+ rs1[i]=0;
+ rs2[i]=0;
+ rt1[i]=0;
+ rt2[i]=0;
+ if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
+ if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
+ rs2[i]=CSREG;
+ int gr=(source[i]>>11)&0x1F;
+ switch(op2)
+ {
+ case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
+ case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
+ case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
+ case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
+ }
+ break;
case C1LS:
rs1[i]=(source[i]>>21)&0x1F;
rs2[i]=CSREG;
rt1[i]=0;
rt2[i]=0;
imm[i]=(short)source[i];
+ if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
+ else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
+ break;
+ case C2OP:
+ rs1[i]=0;
+ rs2[i]=0;
+ rt1[i]=0;
+ rt2[i]=0;
+ gte_rs[i]=gte_reg_reads[source[i]&0x3f];
+ gte_rt[i]=gte_reg_writes[source[i]&0x3f];
+ gte_rt[i]|=1ll<<63; // every op changes flags
+ if((source[i]&0x3f)==GTE_MVMVA) {
+ int v = (source[i] >> 15) & 3;
+ gte_rs[i]&=~0xe3fll;
+ if(v==3) gte_rs[i]|=0xe00ll;
+ else gte_rs[i]|=3ll<<(v*2);
+ }
break;
case FLOAT:
case FCONV:
// branch in delay slot?
if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
// don't handle first branch and call interpreter if it's hit
- printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
+ SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
do_in_intrp=1;
}
// basic load delay detection
int t=(ba[i-1]-start)/4;
if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
// jump target wants DS result - potential load delay effect
- printf("load delay @%08x (%08x)\n", addr + i*4, addr);
+ SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
do_in_intrp=1;
bt[t+1]=1; // expected return from interpreter
}
else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
!(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
// v0 overwrite like this is a sign of trouble, bail out
- printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
+ SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
do_in_intrp=1;
}
}
// Does the block continue due to a branch?
for(j=i-1;j>=0;j--)
{
+ if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
if(ba[j]==start+i*4+4) done=j=0;
if(ba[j]==start+i*4+8) done=j=0;
}
// Stop if we're compiling junk
if(itype[i]==NI&&opcode[i]==0x11) {
done=stop_after_jal=1;
- printf("Disabled speculative precompilation\n");
+ SysPrintf("Disabled speculative precompilation\n");
}
}
slen=i;
dirty_reg(¤t,CCREG);
current.isconst=0;
current.wasconst=0;
+ current.waswritten=0;
int ds=0;
int cc=0;
int hr=-1;
if(current.regmap[hr]==0) current.regmap[hr]=-1;
}
current.isconst=0;
+ current.waswritten=0;
}
if(i>1)
{
}
if(temp_is32!=current.is32) {
//printf("dumping 32-bit regs (%x)\n",start+i*4);
- #ifdef DESTRUCTIVE_WRITEBACK
+ #ifndef DESTRUCTIVE_WRITEBACK
+ if(ds)
+ #endif
for(hr=0;hr<HOST_REGS;hr++)
{
int r=current.regmap[hr];
}
}
}
- #endif
current.is32=temp_is32;
}
}
regs[i].wasconst=current.isconst;
regs[i].was32=current.is32;
regs[i].wasdirty=current.dirty;
+ regs[i].loadedconst=0;
#if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
// To change a dirty register from 32 to 64 bits, we must write
// it out during the previous cycle (for branches, 2 cycles)
current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
current.u|=1;
current.uu|=1;
- } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
+ } else { SysPrintf("oops, branch at end of block with no delay slot\n");exit(1); }
}
is_ds[i]=ds;
if(ds) {
clear_const(¤t,rt1[i]);
alloc_cc(¤t,i);
dirty_reg(¤t,CCREG);
- ooo[i]=1;
- delayslot_alloc(¤t,i+1);
if (rt1[i]==31) {
alloc_reg(¤t,i,31);
dirty_reg(¤t,31);
#endif
//current.is32|=1LL<<rt1[i];
}
+ ooo[i]=1;
+ delayslot_alloc(¤t,i+1);
//current.isconst=0; // DEBUG
ds=1;
//printf("i=%d, isconst=%x\n",i,current.isconst);
}
memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
}
+
+ if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
+ current.waswritten|=1<<rs1[i-1];
+ current.waswritten&=~(1<<rt1[i]);
+ current.waswritten&=~(1<<rt2[i]);
+ if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
+ current.waswritten&=~(1<<rs1[i]);
+
/* Branch post-alloc */
if(i>0)
{
branch_regs[i-1].is32|=1LL<<31;
}
memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
- memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
+ memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
break;
case RJUMP:
memcpy(&branch_regs[i-1],¤t,sizeof(current));
}
#endif
memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
- memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
+ memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
break;
case CJUMP:
if((opcode[i-1]&0x3E)==4) // BEQ/BNE
branch_regs[i-1].isconst=0;
branch_regs[i-1].wasconst=0;
memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
- memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
+ memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
}
else
if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
branch_regs[i-1].isconst=0;
branch_regs[i-1].wasconst=0;
memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
- memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
+ memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
}
else
// Alloc the delay slot in case the branch is taken
branch_regs[i-1].isconst=0;
branch_regs[i-1].wasconst=0;
memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
- memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
+ memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
}
else
// Alloc the delay slot in case the branch is taken
{
cc=0;
}
-#ifdef PCSX
- else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
+#if defined(PCSX) && !defined(DRC_DBG)
+ else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2)
+ {
+ // GTE runs in parallel until accessed, divide by 2 for a rough guess
+ cc+=gte_cycletab[source[i]&0x3f]/2;
+ }
+ else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues
{
cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
}
regs[i].is32=current.is32;
regs[i].dirty=current.dirty;
regs[i].isconst=current.isconst;
- memcpy(constmap[i],current.constmap,sizeof(current.constmap));
+ memcpy(constmap[i],current_constmap,sizeof(current_constmap));
}
for(hr=0;hr<HOST_REGS;hr++) {
if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
}
}
if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
+ regs[i].waswritten=current.waswritten;
}
/* Pass 4 - Cull unused host registers */
if(likely[i]) {
regs[i].regmap[hr]=-1;
regs[i].isconst&=~(1<<hr);
- if(i<slen-2) regmap_pre[i+2][hr]=-1;
+ if(i<slen-2) {
+ regmap_pre[i+2][hr]=-1;
+ regs[i+2].wasconst&=~(1<<hr);
+ }
}
}
}
{
if(!likely[i]&&i<slen-2) {
regmap_pre[i+2][hr]=-1;
+ regs[i+2].wasconst&=~(1<<hr);
}
}
}
if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
{
- printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
+ SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
}
regmap_pre[i+1][hr]=-1;
if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
+ regs[i+1].wasconst&=~(1<<hr);
}
regs[i].regmap[hr]=-1;
regs[i].isconst&=~(1<<hr);
// If a register is allocated during a loop, try to allocate it for the
// entire loop, if possible. This avoids loading/storing registers
// inside of the loop.
-
+
signed char f_regmap[HOST_REGS];
clear_all_regs(f_regmap);
for(i=0;i<slen-1;i++)
{
int t=(ba[i]-start)>>2;
if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
- if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
+ if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
for(hr=0;hr<HOST_REGS;hr++)
{
if(regs[i].regmap[hr]>64) {
// a mov, which is of negligible benefit. So such cases are
// skipped below.
if(f_regmap[hr]>0) {
- if(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0) {
+ if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
int r=f_regmap[hr];
for(j=t;j<=i;j++)
{
break;
}
// call/ret fast path assumes no registers allocated
- if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
+ if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
break;
}
if(r>63) {
}
}
}else{
- int count=0;
+ // Non branch or undetermined branch target
for(hr=0;hr<HOST_REGS;hr++)
{
if(hr!=EXCLUDE_REG) {
f_regmap[hr]=regs[i].regmap[hr];
}
}
- else if(regs[i].regmap[hr]<0) count++;
}
}
// Try to restore cycle count at branch targets
}
}
+ // Cache memory offset or tlb map pointer if a register is available
+ #ifndef HOST_IMM_ADDR32
+ #ifndef RAM_OFFSET
+ if(using_tlb)
+ #endif
+ {
+ int earliest_available[HOST_REGS];
+ int loop_start[HOST_REGS];
+ int score[HOST_REGS];
+ int end[HOST_REGS];
+ int reg=using_tlb?MMREG:ROREG;
+
+ // Init
+ for(hr=0;hr<HOST_REGS;hr++) {
+ score[hr]=0;earliest_available[hr]=0;
+ loop_start[hr]=MAXBLOCK;
+ }
+ for(i=0;i<slen-1;i++)
+ {
+ // Can't do anything if no registers are available
+ if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ score[hr]=0;earliest_available[hr]=i+1;
+ loop_start[hr]=MAXBLOCK;
+ }
+ }
+ if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
+ if(!ooo[i]) {
+ if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ score[hr]=0;earliest_available[hr]=i+1;
+ loop_start[hr]=MAXBLOCK;
+ }
+ }
+ }else{
+ if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ score[hr]=0;earliest_available[hr]=i+1;
+ loop_start[hr]=MAXBLOCK;
+ }
+ }
+ }
+ }
+ // Mark unavailable registers
+ for(hr=0;hr<HOST_REGS;hr++) {
+ if(regs[i].regmap[hr]>=0) {
+ score[hr]=0;earliest_available[hr]=i+1;
+ loop_start[hr]=MAXBLOCK;
+ }
+ if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
+ if(branch_regs[i].regmap[hr]>=0) {
+ score[hr]=0;earliest_available[hr]=i+2;
+ loop_start[hr]=MAXBLOCK;
+ }
+ }
+ }
+ // No register allocations after unconditional jumps
+ if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
+ {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ score[hr]=0;earliest_available[hr]=i+2;
+ loop_start[hr]=MAXBLOCK;
+ }
+ i++; // Skip delay slot too
+ //printf("skip delay slot: %x\n",start+i*4);
+ }
+ else
+ // Possible match
+ if(itype[i]==LOAD||itype[i]==LOADLR||
+ itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ if(hr!=EXCLUDE_REG) {
+ end[hr]=i-1;
+ for(j=i;j<slen-1;j++) {
+ if(regs[j].regmap[hr]>=0) break;
+ if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
+ if(branch_regs[j].regmap[hr]>=0) break;
+ if(ooo[j]) {
+ if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
+ }else{
+ if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
+ }
+ }
+ else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
+ if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
+ int t=(ba[j]-start)>>2;
+ if(t<j&&t>=earliest_available[hr]) {
+ if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
+ // Score a point for hoisting loop invariant
+ if(t<loop_start[hr]) loop_start[hr]=t;
+ //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
+ score[hr]++;
+ end[hr]=j;
+ }
+ }
+ else if(t<j) {
+ if(regs[t].regmap[hr]==reg) {
+ // Score a point if the branch target matches this register
+ score[hr]++;
+ end[hr]=j;
+ }
+ }
+ if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
+ itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
+ score[hr]++;
+ end[hr]=j;
+ }
+ }
+ if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
+ {
+ // Stop on unconditional branch
+ break;
+ }
+ else
+ if(itype[j]==LOAD||itype[j]==LOADLR||
+ itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
+ score[hr]++;
+ end[hr]=j;
+ }
+ }
+ }
+ }
+ // Find highest score and allocate that register
+ int maxscore=0;
+ for(hr=0;hr<HOST_REGS;hr++) {
+ if(hr!=EXCLUDE_REG) {
+ if(score[hr]>score[maxscore]) {
+ maxscore=hr;
+ //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
+ }
+ }
+ }
+ if(score[maxscore]>1)
+ {
+ if(i<loop_start[maxscore]) loop_start[maxscore]=i;
+ for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
+ //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
+ assert(regs[j].regmap[maxscore]<0);
+ if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
+ regs[j].regmap[maxscore]=reg;
+ regs[j].dirty&=~(1<<maxscore);
+ regs[j].wasconst&=~(1<<maxscore);
+ regs[j].isconst&=~(1<<maxscore);
+ if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
+ branch_regs[j].regmap[maxscore]=reg;
+ branch_regs[j].wasdirty&=~(1<<maxscore);
+ branch_regs[j].dirty&=~(1<<maxscore);
+ branch_regs[j].wasconst&=~(1<<maxscore);
+ branch_regs[j].isconst&=~(1<<maxscore);
+ if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
+ regmap_pre[j+2][maxscore]=reg;
+ regs[j+2].wasdirty&=~(1<<maxscore);
+ }
+ // loop optimization (loop_preload)
+ int t=(ba[j]-start)>>2;
+ if(t==loop_start[maxscore]) {
+ if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
+ regs[t].regmap_entry[maxscore]=reg;
+ }
+ }
+ else
+ {
+ if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
+ regmap_pre[j+1][maxscore]=reg;
+ regs[j+1].wasdirty&=~(1<<maxscore);
+ }
+ }
+ }
+ i=j-1;
+ if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
+ for(hr=0;hr<HOST_REGS;hr++) {
+ score[hr]=0;earliest_available[hr]=i+i;
+ loop_start[hr]=MAXBLOCK;
+ }
+ }
+ }
+ }
+ }
+ #endif
+
// This allocates registers (if possible) one instruction prior
// to use, which can avoid a load-use penalty on certain CPUs.
for(i=0;i<slen-1;i++)
}
}
}
+ // Preload target address for load instruction (non-constant)
if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
{
}
}
}
+ // Load source into target register
if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
{
}
}
}
+ // Preload map address
#ifndef HOST_IMM_ADDR32
if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
hr=get_reg(regs[i+1].regmap,TLREG);
}
}
#endif
+ // Address for store instruction (non-constant)
if(itype[i+1]==STORE||itype[i+1]==STORELR
||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
if(itype[slen-1]==SPAN) {
bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
}
-
+
+#ifdef DISASM
/* Debug/disassembly */
- if((void*)assem_debug==(void*)printf)
for(i=0;i<slen;i++)
{
printf("U:");
#endif
}
}
+#endif // DISASM
/* Pass 8 - Assembly */
linkcount=0;stubcount=0;
#ifdef PCSX
if (start == 0x80030000) {
// nasty hack for fastbios thing
+ // override block entry to this code
instr_addr0_override=(u_int)out;
emit_movimm(start,0);
- emit_readword((int)&pcaddr,1);
+ // abuse io address var as a flag that we
+ // have already returned here once
+ emit_readword((int)&address,1);
emit_writeword(0,(int)&pcaddr);
+ emit_writeword(0,(int)&address);
emit_cmp(0,1);
emit_jne((int)new_dyna_leave);
}
for(i=0;i<slen;i++)
{
//if(ds) printf("ds: ");
- if((void*)assem_debug==(void*)printf) disassemble_inst(i);
+ disassemble_inst(i);
if(ds) {
ds=0; // Skip delay slot
if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
instr_addr[i]=0;
} else {
+ speculate_register_values(i);
#ifndef DESTRUCTIVE_WRITEBACK
if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
{
wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
unneeded_reg[i],unneeded_reg_upper[i]);
}
- is32_pre=regs[i].is32;
- dirty_pre=regs[i].dirty;
+ if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
+ is32_pre=branch_regs[i].is32;
+ dirty_pre=branch_regs[i].dirty;
+ }else{
+ is32_pre=regs[i].is32;
+ dirty_pre=regs[i].dirty;
+ }
#endif
// write back
if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
emit_loadreg(CCREG,HOST_CCREG);
- emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
+ emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
}
else if(!likely[i-2])
{
store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
emit_loadreg(CCREG,HOST_CCREG);
- emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
+ emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
add_to_linker((int)out,start+i*4,0);
emit_jmp(0);
}
u_int page=get_page(vaddr);
u_int vpage=get_vpage(vaddr);
literal_pool(256);
- //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
-#ifndef FORCE32
- if(!requires_32bit[i])
-#else
- if(1)
-#endif
{
assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
assem_debug("jump_in: %x\n",start+i*4);
ht_bin[3]=entry_point;
}
}
- else
- {
- u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
- assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
- assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
- //int entry_point=(int)out;
- ////assem_debug("entry_point: %x\n",entry_point);
- //load_regs_entry(i);
- //if(entry_point==(int)out)
- // entry_point=instr_addr[i];
- //else
- // emit_jmp(instr_addr[i]);
- //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
- ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
- int entry_point=do_dirty_stub(i);
- ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
- }
}
}
}
// If we're within 256K of the end of the buffer,
// start over from the beginning. (Is 256K enough?)
- if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
+ if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
// Trap writes to any of the pages we compiled
for(i=start>>12;i<=(start+slen*4)>>12;i++) {
}
#endif
}
+ inv_code_start=inv_code_end=~0;
#ifdef PCSX
- // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
+ // for PCSX we need to mark all mirrors too
if(get_page(start)<(RAM_SIZE>>12))
for(i=start>>12;i<=(start+slen*4)>>12;i++)
- invalid_code[((u_int)0x80000000>>12)|i]=0;
+ invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
+ invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
+ invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
#endif
/* Pass 10 - Free memory by expiring oldest blocks */
- int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
+ int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
while(expirep!=end)
{
int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
- int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
+ int base=(int)BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
inv_debug("EXP: Phase %d\n",expirep);
switch((expirep>>11)&3)
{
notaz.gp2x.de / pcsx_rearmed.git / blobdiff