#endif
#include "new_dynarec_config.h"
-#include "../psxhle.h" //emulator interface
+#include "../psxhle.h"
+#include "../psxinterpreter.h"
#include "emu_if.h" //emulator interface
+#define noinline __attribute__((noinline,noclone))
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
#endif
#ifdef __arm__
#include "assem_arm.h"
#endif
+#ifdef __aarch64__
+#include "assem_arm64.h"
+#endif
#define MAXBLOCK 4096
#define MAX_OUTPUT_BLOCK_SIZE 262144
{
signed char regmap_entry[HOST_REGS];
signed char regmap[HOST_REGS];
- uint64_t was32;
- uint64_t is32;
uint64_t wasdirty;
uint64_t dirty;
uint64_t u;
- uint64_t uu;
u_int wasconst;
u_int isconst;
u_int loadedconst; // host regs that have constants loaded
static u_char rs2[MAXBLOCK];
static u_char rt1[MAXBLOCK];
static u_char rt2[MAXBLOCK];
- static u_char us1[MAXBLOCK];
- static u_char us2[MAXBLOCK];
static u_char dep1[MAXBLOCK];
static u_char dep2[MAXBLOCK];
static u_char lt1[MAXBLOCK];
static char is_ds[MAXBLOCK];
static char ooo[MAXBLOCK];
static uint64_t unneeded_reg[MAXBLOCK];
- static uint64_t unneeded_reg_upper[MAXBLOCK];
static uint64_t branch_unneeded_reg[MAXBLOCK];
- static uint64_t branch_unneeded_reg_upper[MAXBLOCK];
- static signed char regmap_pre[MAXBLOCK][HOST_REGS];
+ static signed char regmap_pre[MAXBLOCK][HOST_REGS]; // pre-instruction i?
static uint64_t current_constmap[HOST_REGS];
static uint64_t constmap[MAXBLOCK][HOST_REGS];
static struct regstat regs[MAXBLOCK];
static u_int literals[1024][2];
static int literalcount;
static int is_delayslot;
- static int cop1_usable;
static char shadow[1048576] __attribute__((aligned(16)));
static void *copy;
static int expirep;
int new_dynarec_hacks;
int new_dynarec_did_compile;
+
+ extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
+ extern int last_count; // last absolute target, often = next_interupt
+ extern int pcaddr;
+ extern int pending_exception;
+ extern int branch_target;
+ extern uintptr_t mini_ht[32][2];
extern u_char restore_candidate[512];
- extern int cycle_count;
/* registers that may be allocated */
/* 1-31 gpr */
-#define HIREG 32 // hi
-#define LOREG 33 // lo
-#define FSREG 34 // FPU status (FCSR)
+#define LOREG 32 // lo
+#define HIREG 33 // hi
+//#define FSREG 34 // FPU status (FCSR)
#define CSREG 35 // Coprocessor status
#define CCREG 36 // Cycle count
#define INVCP 37 // Pointer to invalid_code
#define COP0 15 // Coprocessor 0
#define COP1 16 // Coprocessor 1
#define C1LS 17 // Coprocessor 1 load/store
-#define FJUMP 18 // Conditional branch (floating point)
-#define FLOAT 19 // Floating point unit
-#define FCONV 20 // Convert integer to float
-#define FCOMP 21 // Floating point compare (sets FSREG)
+//#define FJUMP 18 // Conditional branch (floating point)
+//#define FLOAT 19 // Floating point unit
+//#define FCONV 20 // Convert integer to float
+//#define FCOMP 21 // Floating point compare (sets FSREG)
#define SYSCALL 22// SYSCALL
#define OTHER 23 // Other
#define SPAN 24 // Branch/delay slot spans 2 pages
#define NOTTAKEN 2
#define NULLDS 3
+#define DJT_1 (void *)1l // no function, just a label in assem_debug log
+#define DJT_2 (void *)2l
+
// asm linkage
-int new_recompile_block(int addr);
+int new_recompile_block(u_int addr);
void *get_addr_ht(u_int vaddr);
void invalidate_block(u_int block);
void invalidate_addr(u_int addr);
void dyna_linker();
void dyna_linker_ds();
void verify_code();
-void verify_code_vm();
void verify_code_ds();
void cc_interrupt();
void fp_exception();
void fp_exception_ds();
-void jump_syscall_hle();
-void jump_hlecall();
-void jump_intcall();
+void jump_to_new_pc();
void new_dyna_leave();
// Needed by assembler
-static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
-static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
-static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
+static void wb_register(signed char r,signed char regmap[],uint64_t dirty);
+static void wb_dirtys(signed char i_regmap[],uint64_t i_dirty);
+static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr);
static void load_all_regs(signed char i_regmap[]);
static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
static void load_regs_entry(int t);
-static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
+static void load_all_consts(signed char regmap[],u_int dirty,int i);
-static int verify_dirty(u_int *ptr);
+static int verify_dirty(const u_int *ptr);
static int get_final_value(int hr, int i, int *value);
static void add_stub(enum stub_type type, void *addr, void *retaddr,
u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
int i, int addr_reg, struct regstat *i_regs, int ccadj, u_int reglist);
static void add_to_linker(void *addr, u_int target, int ext);
+static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override);
+static void *get_direct_memhandler(void *table, u_int addr,
+ enum stub_type type, uintptr_t *addr_host);
+static void pass_args(int a0, int a1);
static void mprotect_w_x(void *start, void *end, int is_x)
{
__clear_cache(start, end);
#endif
(void)len;
+#else
+ __clear_cache(start, end);
#endif
mprotect_w_x(start, end, 1);
// Get address from virtual address
// This is called from the recompiled JR/JALR instructions
-void *get_addr(u_int vaddr)
+void noinline *get_addr(u_int vaddr)
{
u_int page=get_page(vaddr);
u_int vpage=get_vpage(vaddr);
for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
}
-signed char get_reg(signed char regmap[],int r)
+static signed char get_reg(const signed char regmap[],int r)
{
int hr;
for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
}
// Find a register that is available for two consecutive cycles
-signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
+static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
{
int hr;
for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
}
}
-// If we dirty the lower half of a 64 bit register which is now being
-// sign-extended, we need to dump the upper half.
-// Note: Do this only after completion of the instruction, because
-// some instructions may need to read the full 64-bit value even if
-// overwriting it (eg SLTI, DSRA32).
-static void flush_dirty_uppers(struct regstat *cur)
-{
- int hr,reg;
- for (hr=0;hr<HOST_REGS;hr++) {
- if((cur->dirty>>hr)&1) {
- reg=cur->regmap[hr];
- if(reg>=64)
- if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
- }
- }
-}
-
void set_const(struct regstat *cur,signed char reg,uint64_t value)
{
int hr;
cur->isconst|=1<<hr;
current_constmap[hr]=value;
}
- else if((cur->regmap[hr]^64)==reg) {
- cur->isconst|=1<<hr;
- current_constmap[hr]=value>>32;
- }
}
}
}
}
SysPrintf("Unknown constant in r%d\n",reg);
- exit(1);
+ abort();
}
// Least soon needed registers
hsn[INVCP]=j;
}
#endif
- if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
+ if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP))
{
hsn[CCREG]=j;
b=j;
// TODO: preferred register based on backward branch
}
// Delay slot should preferably not overwrite branch conditions or cycle count
- if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
+ if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP)) {
if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
hsn[CCREG]=1;
if(rs1[i+j]==r) rn=j;
if(rs2[i+j]==r) rn=j;
if((unneeded_reg[i+j]>>r)&1) rn=10;
- if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
+ if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP))
{
b=j;
}
}
k=0;
if(i>0){
- if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
+ if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP)
k--;
}
for(;k<j;k++)
{
- if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
- if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
- if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
+ assert(r < 64);
+ if((unneeded_reg[i+k]>>r)&1) return hr;
+ if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP))
{
if(ba[i+k]>=start && ba[i+k]<(start+i*4))
{
}
}
+#ifndef NDEBUG
+static int host_tempreg_in_use;
+
+static void host_tempreg_acquire(void)
+{
+ assert(!host_tempreg_in_use);
+ host_tempreg_in_use = 1;
+}
+
+static void host_tempreg_release(void)
+{
+ host_tempreg_in_use = 0;
+}
+#else
+static void host_tempreg_acquire(void) {}
+static void host_tempreg_release(void) {}
+#endif
+
+#ifdef DRC_DBG
+extern void gen_interupt();
+extern void do_insn_cmp();
+#define FUNCNAME(f) { f, " " #f }
+static const struct {
+ void *addr;
+ const char *name;
+} function_names[] = {
+ FUNCNAME(cc_interrupt),
+ FUNCNAME(gen_interupt),
+ FUNCNAME(get_addr_ht),
+ FUNCNAME(get_addr),
+ FUNCNAME(jump_handler_read8),
+ FUNCNAME(jump_handler_read16),
+ FUNCNAME(jump_handler_read32),
+ FUNCNAME(jump_handler_write8),
+ FUNCNAME(jump_handler_write16),
+ FUNCNAME(jump_handler_write32),
+ FUNCNAME(invalidate_addr),
+ FUNCNAME(jump_to_new_pc),
+ FUNCNAME(new_dyna_leave),
+ FUNCNAME(pcsx_mtc0),
+ FUNCNAME(pcsx_mtc0_ds),
+ FUNCNAME(do_insn_cmp),
+#ifdef __arm__
+ FUNCNAME(verify_code),
+#endif
+};
+
+static const char *func_name(const void *a)
+{
+ int i;
+ for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
+ if (function_names[i].addr == a)
+ return function_names[i].name;
+ return "";
+}
+#else
+#define func_name(x) ""
+#endif
+
#ifdef __i386__
#include "assem_x86.c"
#endif
#ifdef __arm__
#include "assem_arm.c"
#endif
+#ifdef __aarch64__
+#include "assem_arm64.c"
+#endif
// Add virtual address mapping to linked list
void ll_add(struct ll_entry **head,int vaddr,void *addr)
{
inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
void *host_addr=find_extjump_insn(head->addr);
- #ifdef __arm__
+ #if defined(__arm__) || defined(__aarch64__)
mark_clear_cache(host_addr);
#endif
set_jump_target(host_addr, head->addr);
}
// This is called when we write to a compiled block (see do_invstub)
-void invalidate_page(u_int page)
+static void invalidate_page(u_int page)
{
struct ll_entry *head;
struct ll_entry *next;
while(head!=NULL) {
inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
void *host_addr=find_extjump_insn(head->addr);
- #ifdef __arm__
+ #if defined(__arm__) || defined(__aarch64__)
mark_clear_cache(host_addr);
#endif
set_jump_target(host_addr, head->addr);
for(first=page+1;first<last;first++) {
invalidate_page(first);
}
- #ifdef __arm__
+ #if defined(__arm__) || defined(__aarch64__)
do_clear_cache();
#endif
#endif
}
+static void do_invstub(int n)
+{
+ literal_pool(20);
+ u_int reglist=stubs[n].a;
+ set_jump_target(stubs[n].addr, out);
+ save_regs(reglist);
+ if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
+ emit_call(invalidate_addr);
+ restore_regs(reglist);
+ emit_jmp(stubs[n].retaddr); // return address
+}
+
// Add an entry to jump_out after making a link
+// src should point to code by emit_extjump2()
void add_link(u_int vaddr,void *src)
{
u_int page=get_page(vaddr);
inv_debug("add_link: %p -> %x (%d)\n",src,vaddr,page);
- int *ptr=(int *)(src+4);
- assert((*ptr&0x0fff0000)==0x059f0000);
- (void)ptr;
+ check_extjump2(src);
ll_add(jump_out+page,vaddr,src);
//void *ptr=get_pointer(src);
//inv_debug("add_link: Pointer is to %p\n",ptr);
}
}
+/* Register allocation */
-void mov_alloc(struct regstat *current,int i)
+// Note: registers are allocated clean (unmodified state)
+// if you intend to modify the register, you must call dirty_reg().
+static void alloc_reg(struct regstat *cur,int i,signed char reg)
{
- // Note: Don't need to actually alloc the source registers
- if((~current->is32>>rs1[i])&1) {
- //alloc_reg64(current,i,rs1[i]);
- alloc_reg64(current,i,rt1[i]);
- current->is32&=~(1LL<<rt1[i]);
- } else {
- //alloc_reg(current,i,rs1[i]);
- alloc_reg(current,i,rt1[i]);
- current->is32|=(1LL<<rt1[i]);
+ int r,hr;
+ int preferred_reg = (reg&7);
+ if(reg==CCREG) preferred_reg=HOST_CCREG;
+ if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
+
+ // Don't allocate unused registers
+ if((cur->u>>reg)&1) return;
+
+ // see if it's already allocated
+ for(hr=0;hr<HOST_REGS;hr++)
+ {
+ if(cur->regmap[hr]==reg) return;
+ }
+
+ // Keep the same mapping if the register was already allocated in a loop
+ preferred_reg = loop_reg(i,reg,preferred_reg);
+
+ // Try to allocate the preferred register
+ if(cur->regmap[preferred_reg]==-1) {
+ cur->regmap[preferred_reg]=reg;
+ cur->dirty&=~(1<<preferred_reg);
+ cur->isconst&=~(1<<preferred_reg);
+ return;
+ }
+ r=cur->regmap[preferred_reg];
+ assert(r < 64);
+ if((cur->u>>r)&1) {
+ cur->regmap[preferred_reg]=reg;
+ cur->dirty&=~(1<<preferred_reg);
+ cur->isconst&=~(1<<preferred_reg);
+ return;
+ }
+
+ // Clear any unneeded registers
+ // We try to keep the mapping consistent, if possible, because it
+ // makes branches easier (especially loops). So we try to allocate
+ // first (see above) before removing old mappings. If this is not
+ // possible then go ahead and clear out the registers that are no
+ // longer needed.
+ for(hr=0;hr<HOST_REGS;hr++)
+ {
+ r=cur->regmap[hr];
+ if(r>=0) {
+ assert(r < 64);
+ if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
+ }
+ }
+ // Try to allocate any available register, but prefer
+ // registers that have not been used recently.
+ if(i>0) {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
+ if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
+ cur->regmap[hr]=reg;
+ cur->dirty&=~(1<<hr);
+ cur->isconst&=~(1<<hr);
+ return;
+ }
+ }
+ }
+ }
+ // Try to allocate any available register
+ for(hr=0;hr<HOST_REGS;hr++) {
+ if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
+ cur->regmap[hr]=reg;
+ cur->dirty&=~(1<<hr);
+ cur->isconst&=~(1<<hr);
+ return;
+ }
+ }
+
+ // Ok, now we have to evict someone
+ // Pick a register we hopefully won't need soon
+ u_char hsn[MAXREG+1];
+ memset(hsn,10,sizeof(hsn));
+ int j;
+ lsn(hsn,i,&preferred_reg);
+ //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
+ //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
+ if(i>0) {
+ // Don't evict the cycle count at entry points, otherwise the entry
+ // stub will have to write it.
+ if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
+ if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP)) hsn[CCREG]=2;
+ for(j=10;j>=3;j--)
+ {
+ // Alloc preferred register if available
+ if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ // Evict both parts of a 64-bit register
+ if((cur->regmap[hr]&63)==r) {
+ cur->regmap[hr]=-1;
+ cur->dirty&=~(1<<hr);
+ cur->isconst&=~(1<<hr);
+ }
+ }
+ cur->regmap[preferred_reg]=reg;
+ return;
+ }
+ for(r=1;r<=MAXREG;r++)
+ {
+ if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ if(hr!=HOST_CCREG||j<hsn[CCREG]) {
+ if(cur->regmap[hr]==r) {
+ cur->regmap[hr]=reg;
+ cur->dirty&=~(1<<hr);
+ cur->isconst&=~(1<<hr);
+ return;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ for(j=10;j>=0;j--)
+ {
+ for(r=1;r<=MAXREG;r++)
+ {
+ if(hsn[r]==j) {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ if(cur->regmap[hr]==r) {
+ cur->regmap[hr]=reg;
+ cur->dirty&=~(1<<hr);
+ cur->isconst&=~(1<<hr);
+ return;
+ }
+ }
+ }
+ }
+ }
+ SysPrintf("This shouldn't happen (alloc_reg)");abort();
+}
+
+// Allocate a temporary register. This is done without regard to
+// dirty status or whether the register we request is on the unneeded list
+// Note: This will only allocate one register, even if called multiple times
+static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
+{
+ int r,hr;
+ int preferred_reg = -1;
+
+ // see if it's already allocated
+ for(hr=0;hr<HOST_REGS;hr++)
+ {
+ if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
+ }
+
+ // Try to allocate any available register
+ for(hr=HOST_REGS-1;hr>=0;hr--) {
+ if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
+ cur->regmap[hr]=reg;
+ cur->dirty&=~(1<<hr);
+ cur->isconst&=~(1<<hr);
+ return;
+ }
+ }
+
+ // Find an unneeded register
+ for(hr=HOST_REGS-1;hr>=0;hr--)
+ {
+ r=cur->regmap[hr];
+ if(r>=0) {
+ assert(r < 64);
+ if((cur->u>>r)&1) {
+ if(i==0||((unneeded_reg[i-1]>>r)&1)) {
+ cur->regmap[hr]=reg;
+ cur->dirty&=~(1<<hr);
+ cur->isconst&=~(1<<hr);
+ return;
+ }
+ }
+ }
+ }
+
+ // Ok, now we have to evict someone
+ // Pick a register we hopefully won't need soon
+ // TODO: we might want to follow unconditional jumps here
+ // TODO: get rid of dupe code and make this into a function
+ u_char hsn[MAXREG+1];
+ memset(hsn,10,sizeof(hsn));
+ int j;
+ lsn(hsn,i,&preferred_reg);
+ //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
+ if(i>0) {
+ // Don't evict the cycle count at entry points, otherwise the entry
+ // stub will have to write it.
+ if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
+ if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP)) hsn[CCREG]=2;
+ for(j=10;j>=3;j--)
+ {
+ for(r=1;r<=MAXREG;r++)
+ {
+ if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ if(hr!=HOST_CCREG||hsn[CCREG]>2) {
+ if(cur->regmap[hr]==r) {
+ cur->regmap[hr]=reg;
+ cur->dirty&=~(1<<hr);
+ cur->isconst&=~(1<<hr);
+ return;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ for(j=10;j>=0;j--)
+ {
+ for(r=1;r<=MAXREG;r++)
+ {
+ if(hsn[r]==j) {
+ for(hr=0;hr<HOST_REGS;hr++) {
+ if(cur->regmap[hr]==r) {
+ cur->regmap[hr]=reg;
+ cur->dirty&=~(1<<hr);
+ cur->isconst&=~(1<<hr);
+ return;
+ }
+ }
+ }
+ }
}
+ SysPrintf("This shouldn't happen");abort();
+}
+
+static void mov_alloc(struct regstat *current,int i)
+{
+ // Note: Don't need to actually alloc the source registers
+ //alloc_reg(current,i,rs1[i]);
+ alloc_reg(current,i,rt1[i]);
+
clear_const(current,rs1[i]);
clear_const(current,rt1[i]);
dirty_reg(current,rt1[i]);
}
-void shiftimm_alloc(struct regstat *current,int i)
+static void shiftimm_alloc(struct regstat *current,int i)
{
if(opcode2[i]<=0x3) // SLL/SRL/SRA
{
if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
else lt1[i]=rs1[i];
alloc_reg(current,i,rt1[i]);
- current->is32|=1LL<<rt1[i];
dirty_reg(current,rt1[i]);
if(is_const(current,rs1[i])) {
int v=get_const(current,rs1[i]);
}
}
-void shift_alloc(struct regstat *current,int i)
+static void shift_alloc(struct regstat *current,int i)
{
if(rt1[i]) {
if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
alloc_reg_temp(current,i,-1);
minimum_free_regs[i]=1;
}
- current->is32|=1LL<<rt1[i];
} else { // DSLLV/DSRLV/DSRAV
- if(rs1[i]) alloc_reg64(current,i,rs1[i]);
- if(rs2[i]) alloc_reg(current,i,rs2[i]);
- alloc_reg64(current,i,rt1[i]);
- current->is32&=~(1LL<<rt1[i]);
- if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
- {
- alloc_reg_temp(current,i,-1);
- minimum_free_regs[i]=1;
- }
+ assert(0);
}
clear_const(current,rs1[i]);
clear_const(current,rs2[i]);
}
}
-void alu_alloc(struct regstat *current,int i)
+static void alu_alloc(struct regstat *current,int i)
{
if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
if(rt1[i]) {
}
alloc_reg(current,i,rt1[i]);
}
- current->is32|=1LL<<rt1[i];
}
if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
if(rt1[i]) {
- if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
- {
- alloc_reg64(current,i,rs1[i]);
- alloc_reg64(current,i,rs2[i]);
- alloc_reg(current,i,rt1[i]);
- } else {
- alloc_reg(current,i,rs1[i]);
- alloc_reg(current,i,rs2[i]);
- alloc_reg(current,i,rt1[i]);
- }
+ alloc_reg(current,i,rs1[i]);
+ alloc_reg(current,i,rs2[i]);
+ alloc_reg(current,i,rt1[i]);
}
- current->is32|=1LL<<rt1[i];
}
if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
if(rt1[i]) {
if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
}
alloc_reg(current,i,rt1[i]);
- if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
- {
- if(!((current->uu>>rt1[i])&1)) {
- alloc_reg64(current,i,rt1[i]);
- }
- if(get_reg(current->regmap,rt1[i]|64)>=0) {
- if(rs1[i]&&rs2[i]) {
- alloc_reg64(current,i,rs1[i]);
- alloc_reg64(current,i,rs2[i]);
- }
- else
- {
- // Is is really worth it to keep 64-bit values in registers?
- #ifdef NATIVE_64BIT
- if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
- if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
- #endif
- }
- }
- current->is32&=~(1LL<<rt1[i]);
- } else {
- current->is32|=1LL<<rt1[i];
- }
}
}
if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
- if(rt1[i]) {
- if(rs1[i]&&rs2[i]) {
- if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
- alloc_reg64(current,i,rs1[i]);
- alloc_reg64(current,i,rs2[i]);
- alloc_reg64(current,i,rt1[i]);
- } else {
- alloc_reg(current,i,rs1[i]);
- alloc_reg(current,i,rs2[i]);
- alloc_reg(current,i,rt1[i]);
- }
- }
- else {
- alloc_reg(current,i,rt1[i]);
- if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
- // DADD used as move, or zeroing
- // If we have a 64-bit source, then make the target 64 bits too
- if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
- if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
- alloc_reg64(current,i,rt1[i]);
- } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
- if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
- alloc_reg64(current,i,rt1[i]);
- }
- if(opcode2[i]>=0x2e&&rs2[i]) {
- // DSUB used as negation - 64-bit result
- // If we have a 32-bit register, extend it to 64 bits
- if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
- alloc_reg64(current,i,rt1[i]);
- }
- }
- }
- if(rs1[i]&&rs2[i]) {
- current->is32&=~(1LL<<rt1[i]);
- } else if(rs1[i]) {
- current->is32&=~(1LL<<rt1[i]);
- if((current->is32>>rs1[i])&1)
- current->is32|=1LL<<rt1[i];
- } else if(rs2[i]) {
- current->is32&=~(1LL<<rt1[i]);
- if((current->is32>>rs2[i])&1)
- current->is32|=1LL<<rt1[i];
- } else {
- current->is32|=1LL<<rt1[i];
- }
- }
+ assert(0);
}
clear_const(current,rs1[i]);
clear_const(current,rs2[i]);
dirty_reg(current,rt1[i]);
}
-void imm16_alloc(struct regstat *current,int i)
+static void imm16_alloc(struct regstat *current,int i)
{
if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
else lt1[i]=rs1[i];
if(rt1[i]) alloc_reg(current,i,rt1[i]);
if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
- current->is32&=~(1LL<<rt1[i]);
- if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
- // TODO: Could preserve the 32-bit flag if the immediate is zero
- alloc_reg64(current,i,rt1[i]);
- alloc_reg64(current,i,rs1[i]);
- }
- clear_const(current,rs1[i]);
- clear_const(current,rt1[i]);
+ assert(0);
}
else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
- if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
- current->is32|=1LL<<rt1[i];
clear_const(current,rs1[i]);
clear_const(current,rt1[i]);
}
else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
- if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
- if(rs1[i]!=rt1[i]) {
- if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
- alloc_reg64(current,i,rt1[i]);
- current->is32&=~(1LL<<rt1[i]);
- }
- }
- else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
if(is_const(current,rs1[i])) {
int v=get_const(current,rs1[i]);
if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
set_const(current,rt1[i],v+imm[i]);
}
else clear_const(current,rt1[i]);
- current->is32|=1LL<<rt1[i];
}
else {
set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
- current->is32|=1LL<<rt1[i];
}
dirty_reg(current,rt1[i]);
}
-void load_alloc(struct regstat *current,int i)
+static void load_alloc(struct regstat *current,int i)
{
clear_const(current,rt1[i]);
//if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
assert(get_reg(current->regmap,rt1[i])>=0);
if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
{
- current->is32&=~(1LL<<rt1[i]);
- alloc_reg64(current,i,rt1[i]);
+ assert(0);
}
else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
{
- current->is32&=~(1LL<<rt1[i]);
- alloc_reg64(current,i,rt1[i]);
- alloc_all(current,i);
- alloc_reg64(current,i,FTEMP);
- minimum_free_regs[i]=HOST_REGS;
+ assert(0);
}
- else current->is32|=1LL<<rt1[i];
dirty_reg(current,rt1[i]);
// LWL/LWR need a temporary register for the old value
if(opcode[i]==0x22||opcode[i]==0x26)
minimum_free_regs[i]=1;
if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
{
- alloc_all(current,i);
- alloc_reg64(current,i,FTEMP);
- minimum_free_regs[i]=HOST_REGS;
+ assert(0);
}
}
}
if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
alloc_reg(current,i,rs2[i]);
if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
- alloc_reg64(current,i,rs2[i]);
- if(rs2[i]) alloc_reg(current,i,FTEMP);
+ assert(0);
}
#if defined(HOST_IMM8)
// On CPUs without 32-bit immediates we need a pointer to invalid_code
alloc_reg(current,i,CSREG); // Status
alloc_reg(current,i,FTEMP);
if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
- alloc_reg64(current,i,FTEMP);
+ assert(0);
}
#if defined(HOST_IMM8)
// On CPUs without 32-bit immediates we need a pointer to invalid_code
alloc_reg(current,i,LOREG);
alloc_reg(current,i,rs1[i]);
alloc_reg(current,i,rs2[i]);
- current->is32|=1LL<<HIREG;
- current->is32|=1LL<<LOREG;
dirty_reg(current,HIREG);
dirty_reg(current,LOREG);
}
else // 64-bit
{
- current->u&=~(1LL<<HIREG);
- current->u&=~(1LL<<LOREG);
- current->uu&=~(1LL<<HIREG);
- current->uu&=~(1LL<<LOREG);
- alloc_reg64(current,i,HIREG);
- //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
- alloc_reg64(current,i,rs1[i]);
- alloc_reg64(current,i,rs2[i]);
- alloc_all(current,i);
- current->is32&=~(1LL<<HIREG);
- current->is32&=~(1LL<<LOREG);
- dirty_reg(current,HIREG);
- dirty_reg(current,LOREG);
- minimum_free_regs[i]=HOST_REGS;
+ assert(0);
}
}
else
// The result is undefined, we return zero.
alloc_reg(current,i,HIREG);
alloc_reg(current,i,LOREG);
- current->is32|=1LL<<HIREG;
- current->is32|=1LL<<LOREG;
dirty_reg(current,HIREG);
dirty_reg(current,LOREG);
}
clear_const(current,rt1[i]);
alloc_all(current,i);
alloc_reg(current,i,rt1[i]);
- current->is32|=1LL<<rt1[i];
dirty_reg(current,rt1[i]);
}
}
minimum_free_regs[i]=HOST_REGS;
}
-void cop1_alloc(struct regstat *current,int i)
+static void cop12_alloc(struct regstat *current,int i)
{
alloc_reg(current,i,CSREG); // Load status
- if(opcode2[i]<3) // MFC1/DMFC1/CFC1
+ if(opcode2[i]<3) // MFC1/CFC1
{
if(rt1[i]){
clear_const(current,rt1[i]);
- if(opcode2[i]==1) {
- alloc_reg64(current,i,rt1[i]); // DMFC1
- current->is32&=~(1LL<<rt1[i]);
- }else{
- alloc_reg(current,i,rt1[i]); // MFC1/CFC1
- current->is32|=1LL<<rt1[i];
- }
+ alloc_reg(current,i,rt1[i]);
dirty_reg(current,rt1[i]);
}
alloc_reg_temp(current,i,-1);
}
- else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
+ else if(opcode2[i]>3) // MTC1/CTC1
{
if(rs1[i]){
clear_const(current,rs1[i]);
- if(opcode2[i]==5)
- alloc_reg64(current,i,rs1[i]); // DMTC1
- else
- alloc_reg(current,i,rs1[i]); // MTC1/CTC1
- alloc_reg_temp(current,i,-1);
+ alloc_reg(current,i,rs1[i]);
}
else {
current->u&=~1LL;
alloc_reg(current,i,0);
- alloc_reg_temp(current,i,-1);
}
+ alloc_reg_temp(current,i,-1);
}
minimum_free_regs[i]=1;
}
-void fconv_alloc(struct regstat *current,int i)
-{
- alloc_reg(current,i,CSREG); // Load status
- alloc_reg_temp(current,i,-1);
- minimum_free_regs[i]=1;
-}
-void float_alloc(struct regstat *current,int i)
-{
- alloc_reg(current,i,CSREG); // Load status
- alloc_reg_temp(current,i,-1);
- minimum_free_regs[i]=1;
-}
+
void c2op_alloc(struct regstat *current,int i)
{
alloc_reg_temp(current,i,-1);
}
-void fcomp_alloc(struct regstat *current,int i)
-{
- alloc_reg(current,i,CSREG); // Load status
- alloc_reg(current,i,FSREG); // Load flags
- dirty_reg(current,FSREG); // Flag will be modified
- alloc_reg_temp(current,i,-1);
- minimum_free_regs[i]=1;
-}
void syscall_alloc(struct regstat *current,int i)
{
case CJUMP:
case SJUMP:
case RJUMP:
- case FJUMP:
case SYSCALL:
case HLECALL:
case SPAN:
- assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
+ assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort();
SysPrintf("Disabled speculative precompilation\n");
stop_after_jal=1;
break;
break;
case COP1:
case COP2:
- cop1_alloc(current,i);
+ cop12_alloc(current,i);
break;
case C1LS:
c1ls_alloc(current,i);
case C2LS:
c2ls_alloc(current,i);
break;
- case FCONV:
- fconv_alloc(current,i);
- break;
- case FLOAT:
- float_alloc(current,i);
- break;
- case FCOMP:
- fcomp_alloc(current,i);
- break;
case C2OP:
c2op_alloc(current,i);
break;
{
if(rs1[i]) alloc_reg(current,i,rs1[i]);
if(rs2[i]) alloc_reg(current,i,rs2[i]);
- if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
- {
- if(rs1[i]) alloc_reg64(current,i,rs1[i]);
- if(rs2[i]) alloc_reg64(current,i,rs2[i]);
- }
}
else
if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
{
if(rs1[i]) alloc_reg(current,i,rs1[i]);
- if(!((current->is32>>rs1[i])&1))
- {
- if(rs1[i]) alloc_reg64(current,i,rs1[i]);
- }
- }
- else
- if(opcode[i]==0x11) // BC1
- {
- alloc_reg(current,i,FSREG);
- alloc_reg(current,i,CSREG);
}
//else ...
}
static void add_stub(enum stub_type type, void *addr, void *retaddr,
u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
{
- assert(a < ARRAY_SIZE(stubs));
+ assert(stubcount < ARRAY_SIZE(stubs));
stubs[stubcount].type = type;
stubs[stubcount].addr = addr;
stubs[stubcount].retaddr = retaddr;
}
// Write out a single register
-void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
+static void wb_register(signed char r,signed char regmap[],uint64_t dirty)
{
int hr;
for(hr=0;hr<HOST_REGS;hr++) {
if(hr!=EXCLUDE_REG) {
if((regmap[hr]&63)==r) {
if((dirty>>hr)&1) {
- if(regmap[hr]<64) {
- emit_storereg(r,hr);
- }else{
- emit_storereg(r|64,hr);
+ assert(regmap[hr]<64);
+ emit_storereg(r,hr);
+ }
+ }
+ }
+ }
+}
+
+static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
+{
+ //if(dirty_pre==dirty) return;
+ int hr,reg;
+ for(hr=0;hr<HOST_REGS;hr++) {
+ if(hr!=EXCLUDE_REG) {
+ reg=pre[hr];
+ if(((~u)>>(reg&63))&1) {
+ if(reg>0) {
+ if(((dirty_pre&~dirty)>>hr)&1) {
+ if(reg>0&®<34) {
+ emit_storereg(reg,hr);
+ }
+ else if(reg>=64) {
+ assert(0);
+ }
}
}
}
}
}
-void rlist()
+// trashes r2
+static void pass_args(int a0, int a1)
{
- int i;
- printf("TRACE: ");
- for(i=0;i<32;i++)
- printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
- printf("\n");
+ if(a0==1&&a1==0) {
+ // must swap
+ emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
+ }
+ else if(a0!=0&&a1==0) {
+ emit_mov(a1,1);
+ if (a0>=0) emit_mov(a0,0);
+ }
+ else {
+ if(a0>=0&&a0!=0) emit_mov(a0,0);
+ if(a1>=0&&a1!=1) emit_mov(a1,1);
+ }
}
-void alu_assemble(int i,struct regstat *i_regs)
+static void alu_assemble(int i,struct regstat *i_regs)
{
if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
if(rt1[i]) {
}
}
if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
+ assert(0);
+ }
+ if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
if(rt1[i]) {
- signed char s1l,s2l,s1h,s2h,tl,th;
- tl=get_reg(i_regs->regmap,rt1[i]);
- th=get_reg(i_regs->regmap,rt1[i]|64);
- if(tl>=0) {
- s1l=get_reg(i_regs->regmap,rs1[i]);
- s2l=get_reg(i_regs->regmap,rs2[i]);
- s1h=get_reg(i_regs->regmap,rs1[i]|64);
- s2h=get_reg(i_regs->regmap,rs2[i]|64);
- if(rs1[i]&&rs2[i]) {
- assert(s1l>=0);
- assert(s2l>=0);
- if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
- else emit_adds(s1l,s2l,tl);
- if(th>=0) {
- #ifdef INVERTED_CARRY
- if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
- #else
- if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
- #endif
- else emit_add(s1h,s2h,th);
- }
- }
- else if(rs1[i]) {
- if(s1l>=0) emit_mov(s1l,tl);
- else emit_loadreg(rs1[i],tl);
- if(th>=0) {
- if(s1h>=0) emit_mov(s1h,th);
- else emit_loadreg(rs1[i]|64,th);
- }
- }
- else if(rs2[i]) {
- if(s2l>=0) {
- if(opcode2[i]&2) emit_negs(s2l,tl);
- else emit_mov(s2l,tl);
- }
- else {
- emit_loadreg(rs2[i],tl);
- if(opcode2[i]&2) emit_negs(tl,tl);
- }
- if(th>=0) {
- #ifdef INVERTED_CARRY
- if(s2h>=0) emit_mov(s2h,th);
- else emit_loadreg(rs2[i]|64,th);
- if(opcode2[i]&2) {
- emit_adcimm(-1,th); // x86 has inverted carry flag
- emit_not(th,th);
- }
- #else
- if(opcode2[i]&2) {
- if(s2h>=0) emit_rscimm(s2h,0,th);
- else {
- emit_loadreg(rs2[i]|64,th);
- emit_rscimm(th,0,th);
- }
- }else{
- if(s2h>=0) emit_mov(s2h,th);
- else emit_loadreg(rs2[i]|64,th);
- }
- #endif
- }
- }
- else {
- emit_zeroreg(tl);
- if(th>=0) emit_zeroreg(th);
- }
- }
- }
- }
- if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
- if(rt1[i]) {
- signed char s1l,s1h,s2l,s2h,t;
- if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
- {
- t=get_reg(i_regs->regmap,rt1[i]);
- //assert(t>=0);
- if(t>=0) {
- s1l=get_reg(i_regs->regmap,rs1[i]);
- s1h=get_reg(i_regs->regmap,rs1[i]|64);
- s2l=get_reg(i_regs->regmap,rs2[i]);
- s2h=get_reg(i_regs->regmap,rs2[i]|64);
- if(rs2[i]==0) // rx<r0
- {
- assert(s1h>=0);
- if(opcode2[i]==0x2a) // SLT
- emit_shrimm(s1h,31,t);
- else // SLTU (unsigned can not be less than zero)
- emit_zeroreg(t);
- }
- else if(rs1[i]==0) // r0<rx
- {
- assert(s2h>=0);
- if(opcode2[i]==0x2a) // SLT
- emit_set_gz64_32(s2h,s2l,t);
- else // SLTU (set if not zero)
- emit_set_nz64_32(s2h,s2l,t);
- }
- else {
- assert(s1l>=0);assert(s1h>=0);
- assert(s2l>=0);assert(s2h>=0);
- if(opcode2[i]==0x2a) // SLT
- emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
- else // SLTU
- emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
- }
- }
- } else {
- t=get_reg(i_regs->regmap,rt1[i]);
- //assert(t>=0);
- if(t>=0) {
- s1l=get_reg(i_regs->regmap,rs1[i]);
- s2l=get_reg(i_regs->regmap,rs2[i]);
- if(rs2[i]==0) // rx<r0
- {
- assert(s1l>=0);
- if(opcode2[i]==0x2a) // SLT
- emit_shrimm(s1l,31,t);
- else // SLTU (unsigned can not be less than zero)
- emit_zeroreg(t);
+ signed char s1l,s2l,t;
+ {
+ t=get_reg(i_regs->regmap,rt1[i]);
+ //assert(t>=0);
+ if(t>=0) {
+ s1l=get_reg(i_regs->regmap,rs1[i]);
+ s2l=get_reg(i_regs->regmap,rs2[i]);
+ if(rs2[i]==0) // rx<r0
+ {
+ assert(s1l>=0);
+ if(opcode2[i]==0x2a) // SLT
+ emit_shrimm(s1l,31,t);
+ else // SLTU (unsigned can not be less than zero)
+ emit_zeroreg(t);
}
else if(rs1[i]==0) // r0<rx
{
}
if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
if(rt1[i]) {
- signed char s1l,s1h,s2l,s2h,th,tl;
+ signed char s1l,s2l,tl;
tl=get_reg(i_regs->regmap,rt1[i]);
- th=get_reg(i_regs->regmap,rt1[i]|64);
- if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
- {
- assert(tl>=0);
- if(tl>=0) {
- s1l=get_reg(i_regs->regmap,rs1[i]);
- s1h=get_reg(i_regs->regmap,rs1[i]|64);
- s2l=get_reg(i_regs->regmap,rs2[i]);
- s2h=get_reg(i_regs->regmap,rs2[i]|64);
- if(rs1[i]&&rs2[i]) {
- assert(s1l>=0);assert(s1h>=0);
- assert(s2l>=0);assert(s2h>=0);
- if(opcode2[i]==0x24) { // AND
- emit_and(s1l,s2l,tl);
- emit_and(s1h,s2h,th);
- } else
- if(opcode2[i]==0x25) { // OR
- emit_or(s1l,s2l,tl);
- emit_or(s1h,s2h,th);
- } else
- if(opcode2[i]==0x26) { // XOR
- emit_xor(s1l,s2l,tl);
- emit_xor(s1h,s2h,th);
- } else
- if(opcode2[i]==0x27) { // NOR
- emit_or(s1l,s2l,tl);
- emit_or(s1h,s2h,th);
- emit_not(tl,tl);
- emit_not(th,th);
- }
- }
- else
- {
- if(opcode2[i]==0x24) { // AND
- emit_zeroreg(tl);
- emit_zeroreg(th);
- } else
- if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
- if(rs1[i]){
- if(s1l>=0) emit_mov(s1l,tl);
- else emit_loadreg(rs1[i],tl);
- if(s1h>=0) emit_mov(s1h,th);
- else emit_loadreg(rs1[i]|64,th);
- }
- else
- if(rs2[i]){
- if(s2l>=0) emit_mov(s2l,tl);
- else emit_loadreg(rs2[i],tl);
- if(s2h>=0) emit_mov(s2h,th);
- else emit_loadreg(rs2[i]|64,th);
- }
- else{
- emit_zeroreg(tl);
- emit_zeroreg(th);
- }
- } else
- if(opcode2[i]==0x27) { // NOR
- if(rs1[i]){
- if(s1l>=0) emit_not(s1l,tl);
- else{
- emit_loadreg(rs1[i],tl);
- emit_not(tl,tl);
- }
- if(s1h>=0) emit_not(s1h,th);
- else{
- emit_loadreg(rs1[i]|64,th);
- emit_not(th,th);
- }
- }
- else
- if(rs2[i]){
- if(s2l>=0) emit_not(s2l,tl);
- else{
- emit_loadreg(rs2[i],tl);
- emit_not(tl,tl);
- }
- if(s2h>=0) emit_not(s2h,th);
- else{
- emit_loadreg(rs2[i]|64,th);
- emit_not(th,th);
- }
- }
- else {
- emit_movimm(-1,tl);
- emit_movimm(-1,th);
- }
- }
- }
- }
- }
- else
{
- // 32 bit
if(tl>=0) {
s1l=get_reg(i_regs->regmap,rs1[i]);
s2l=get_reg(i_regs->regmap,rs2[i]);
}
if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
if(rt1[i]) {
- signed char sh,sl,th,tl;
- th=get_reg(i_regs->regmap,rt1[i]|64);
+ signed char sl,tl;
tl=get_reg(i_regs->regmap,rt1[i]);
- sh=get_reg(i_regs->regmap,rs1[i]|64);
sl=get_reg(i_regs->regmap,rs1[i]);
if(tl>=0) {
if(rs1[i]) {
- assert(sh>=0);
assert(sl>=0);
- if(th>=0) {
- emit_addimm64_32(sh,sl,imm[i],th,tl);
- }
- else {
- emit_addimm(sl,imm[i],tl);
- }
+ emit_addimm(sl,imm[i],tl);
} else {
emit_movimm(imm[i],tl);
- if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
}
}
}
else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
if(rt1[i]) {
//assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
- signed char sh,sl,t;
+ signed char sl,t;
t=get_reg(i_regs->regmap,rt1[i]);
- sh=get_reg(i_regs->regmap,rs1[i]|64);
sl=get_reg(i_regs->regmap,rs1[i]);
//assert(t>=0);
if(t>=0) {
if(rs1[i]>0) {
- if(sh<0) assert((i_regs->was32>>rs1[i])&1);
- if(sh<0||((i_regs->was32>>rs1[i])&1)) {
if(opcode[i]==0x0a) { // SLTI
if(sl<0) {
if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
emit_sltiu32(sl,imm[i],t);
}
}
- }else{ // 64-bit
- assert(sl>=0);
- if(opcode[i]==0x0a) // SLTI
- emit_slti64_32(sh,sl,imm[i],t);
- else // SLTIU
- emit_sltiu64_32(sh,sl,imm[i],t);
- }
}else{
// SLTI(U) with r0 is just stupid,
// nonetheless examples can be found
}
else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
if(rt1[i]) {
- signed char sh,sl,th,tl;
- th=get_reg(i_regs->regmap,rt1[i]|64);
+ signed char sl,tl;
tl=get_reg(i_regs->regmap,rt1[i]);
- sh=get_reg(i_regs->regmap,rs1[i]|64);
sl=get_reg(i_regs->regmap,rs1[i]);
if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
if(opcode[i]==0x0c) //ANDI
}
else
emit_zeroreg(tl);
- if(th>=0) emit_zeroreg(th);
}
else
{
if(sl<0) {
if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
}
- if(th>=0) {
- if(sh<0) {
- emit_loadreg(rs1[i]|64,th);
- }else{
- emit_mov(sh,th);
- }
- }
if(opcode[i]==0x0d) { // ORI
if(sl<0) {
emit_orimm(tl,imm[i],tl);
}
else {
emit_movimm(imm[i],tl);
- if(th>=0) emit_zeroreg(th);
}
}
}
}
#ifndef shift_assemble
-void shift_assemble(int i,struct regstat *i_regs)
-{
- printf("Need shift_assemble for this architecture.\n");
- exit(1);
+static void shift_assemble(int i,struct regstat *i_regs)
+{
+ signed char s,t,shift;
+ if (rt1[i] == 0)
+ return;
+ assert(opcode2[i]<=0x07); // SLLV/SRLV/SRAV
+ t = get_reg(i_regs->regmap, rt1[i]);
+ s = get_reg(i_regs->regmap, rs1[i]);
+ shift = get_reg(i_regs->regmap, rs2[i]);
+ if (t < 0)
+ return;
+
+ if(rs1[i]==0)
+ emit_zeroreg(t);
+ else if(rs2[i]==0) {
+ assert(s>=0);
+ if(s!=t) emit_mov(s,t);
+ }
+ else {
+ host_tempreg_acquire();
+ emit_andimm(shift,31,HOST_TEMPREG);
+ switch(opcode2[i]) {
+ case 4: // SLLV
+ emit_shl(s,HOST_TEMPREG,t);
+ break;
+ case 6: // SRLV
+ emit_shr(s,HOST_TEMPREG,t);
+ break;
+ case 7: // SRAV
+ emit_sar(s,HOST_TEMPREG,t);
+ break;
+ default:
+ assert(0);
+ }
+ host_tempreg_release();
+ }
}
+
#endif
-void load_assemble(int i,struct regstat *i_regs)
+enum {
+ MTYPE_8000 = 0,
+ MTYPE_8020,
+ MTYPE_0000,
+ MTYPE_A000,
+ MTYPE_1F80,
+};
+
+static int get_ptr_mem_type(u_int a)
+{
+ if(a < 0x00200000) {
+ if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
+ // return wrong, must use memhandler for BIOS self-test to pass
+ // 007 does similar stuff from a00 mirror, weird stuff
+ return MTYPE_8000;
+ return MTYPE_0000;
+ }
+ if(0x1f800000 <= a && a < 0x1f801000)
+ return MTYPE_1F80;
+ if(0x80200000 <= a && a < 0x80800000)
+ return MTYPE_8020;
+ if(0xa0000000 <= a && a < 0xa0200000)
+ return MTYPE_A000;
+ return MTYPE_8000;
+}
+
+static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override)
{
- int s,th,tl,addr;
+ void *jaddr = NULL;
+ int type=0;
+ int mr=rs1[i];
+ if(((smrv_strong|smrv_weak)>>mr)&1) {
+ type=get_ptr_mem_type(smrv[mr]);
+ //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
+ }
+ else {
+ // use the mirror we are running on
+ type=get_ptr_mem_type(start);
+ //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
+ }
+
+ if(type==MTYPE_8020) { // RAM 80200000+ mirror
+ host_tempreg_acquire();
+ emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
+ addr=*addr_reg_override=HOST_TEMPREG;
+ type=0;
+ }
+ else if(type==MTYPE_0000) { // RAM 0 mirror
+ host_tempreg_acquire();
+ emit_orimm(addr,0x80000000,HOST_TEMPREG);
+ addr=*addr_reg_override=HOST_TEMPREG;
+ type=0;
+ }
+ else if(type==MTYPE_A000) { // RAM A mirror
+ host_tempreg_acquire();
+ emit_andimm(addr,~0x20000000,HOST_TEMPREG);
+ addr=*addr_reg_override=HOST_TEMPREG;
+ type=0;
+ }
+ else if(type==MTYPE_1F80) { // scratchpad
+ if (psxH == (void *)0x1f800000) {
+ host_tempreg_acquire();
+ emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
+ emit_cmpimm(HOST_TEMPREG,0x1000);
+ host_tempreg_release();
+ jaddr=out;
+ emit_jc(0);
+ }
+ else {
+ // do the usual RAM check, jump will go to the right handler
+ type=0;
+ }
+ }
+
+ if(type==0)
+ {
+ emit_cmpimm(addr,RAM_SIZE);
+ jaddr=out;
+ #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
+ // Hint to branch predictor that the branch is unlikely to be taken
+ if(rs1[i]>=28)
+ emit_jno_unlikely(0);
+ else
+ #endif
+ emit_jno(0);
+ if(ram_offset!=0) {
+ host_tempreg_acquire();
+ emit_addimm(addr,ram_offset,HOST_TEMPREG);
+ addr=*addr_reg_override=HOST_TEMPREG;
+ }
+ }
+
+ return jaddr;
+}
+
+// return memhandler, or get directly accessable address and return 0
+static void *get_direct_memhandler(void *table, u_int addr,
+ enum stub_type type, uintptr_t *addr_host)
+{
+ uintptr_t l1, l2 = 0;
+ l1 = ((uintptr_t *)table)[addr>>12];
+ if ((l1 & (1ul << (sizeof(l1)*8-1))) == 0) {
+ uintptr_t v = l1 << 1;
+ *addr_host = v + addr;
+ return NULL;
+ }
+ else {
+ l1 <<= 1;
+ if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
+ l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
+ else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
+ l2=((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
+ else
+ l2=((uintptr_t *)l1)[(addr&0xfff)/4];
+ if ((l2 & (1<<31)) == 0) {
+ uintptr_t v = l2 << 1;
+ *addr_host = v + (addr&0xfff);
+ return NULL;
+ }
+ return (void *)(l2 << 1);
+ }
+}
+
+static void load_assemble(int i,struct regstat *i_regs)
+{
+ int s,tl,addr;
int offset;
void *jaddr=0;
int memtarget=0,c=0;
- int fastload_reg_override=0;
+ int fastio_reg_override=-1;
u_int hr,reglist=0;
- th=get_reg(i_regs->regmap,rt1[i]|64);
tl=get_reg(i_regs->regmap,rt1[i]);
s=get_reg(i_regs->regmap,rs1[i]);
offset=imm[i];
//if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
reglist&=~(1<<tl);
- if(th>=0) reglist&=~(1<<th);
if(!c) {
#ifdef R29_HACK
// Strmnnrmn's speed hack
if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
#endif
{
- jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
+ jaddr=emit_fastpath_cmp_jump(i,addr,&fastio_reg_override);
}
}
else if(ram_offset&&memtarget) {
+ host_tempreg_acquire();
emit_addimm(addr,ram_offset,HOST_TEMPREG);
- fastload_reg_override=HOST_TEMPREG;
+ fastio_reg_override=HOST_TEMPREG;
}
int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
if (opcode[i]==0x20) { // LB
{
int x=0,a=tl;
if(!c) a=addr;
- if(fastload_reg_override) a=fastload_reg_override;
+ if(fastio_reg_override>=0) a=fastio_reg_override;
emit_movsbl_indexed(x,a,tl);
}
if(!dummy) {
int x=0,a=tl;
if(!c) a=addr;
- if(fastload_reg_override) a=fastload_reg_override;
+ if(fastio_reg_override>=0) a=fastio_reg_override;
emit_movswl_indexed(x,a,tl);
}
if(jaddr)
if(!c||memtarget) {
if(!dummy) {
int a=addr;
- if(fastload_reg_override) a=fastload_reg_override;
+ if(fastio_reg_override>=0) a=fastio_reg_override;
emit_readword_indexed(0,a,tl);
}
if(jaddr)
if(!dummy) {
int x=0,a=tl;
if(!c) a=addr;
- if(fastload_reg_override) a=fastload_reg_override;
+ if(fastio_reg_override>=0) a=fastio_reg_override;
emit_movzbl_indexed(x,a,tl);
}
if(!dummy) {
int x=0,a=tl;
if(!c) a=addr;
- if(fastload_reg_override) a=fastload_reg_override;
+ if(fastio_reg_override>=0) a=fastio_reg_override;
emit_movzwl_indexed(x,a,tl);
}
if(jaddr)
inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
}
if (opcode[i]==0x27) { // LWU
- assert(th>=0);
- if(!c||memtarget) {
- if(!dummy) {
- int a=addr;
- if(fastload_reg_override) a=fastload_reg_override;
- emit_readword_indexed(0,a,tl);
- }
- if(jaddr)
- add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
- }
- else {
- inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
- }
- emit_zeroreg(th);
+ assert(0);
}
if (opcode[i]==0x37) { // LD
assert(0);
}
}
+ if (fastio_reg_override == HOST_TEMPREG)
+ host_tempreg_release();
}
#ifndef loadlr_assemble
-void loadlr_assemble(int i,struct regstat *i_regs)
+static void loadlr_assemble(int i,struct regstat *i_regs)
{
- printf("Need loadlr_assemble for this architecture.\n");
- exit(1);
+ int s,tl,temp,temp2,addr;
+ int offset;
+ void *jaddr=0;
+ int memtarget=0,c=0;
+ int fastio_reg_override=-1;
+ u_int hr,reglist=0;
+ tl=get_reg(i_regs->regmap,rt1[i]);
+ s=get_reg(i_regs->regmap,rs1[i]);
+ temp=get_reg(i_regs->regmap,-1);
+ temp2=get_reg(i_regs->regmap,FTEMP);
+ addr=get_reg(i_regs->regmap,AGEN1+(i&1));
+ assert(addr<0);
+ offset=imm[i];
+ for(hr=0;hr<HOST_REGS;hr++) {
+ if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
+ }
+ reglist|=1<<temp;
+ if(offset||s<0||c) addr=temp2;
+ else addr=s;
+ if(s>=0) {
+ c=(i_regs->wasconst>>s)&1;
+ if(c) {
+ memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
+ }
+ }
+ if(!c) {
+ emit_shlimm(addr,3,temp);
+ if (opcode[i]==0x22||opcode[i]==0x26) {
+ emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
+ }else{
+ emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
+ }
+ jaddr=emit_fastpath_cmp_jump(i,temp2,&fastio_reg_override);
+ }
+ else {
+ if(ram_offset&&memtarget) {
+ host_tempreg_acquire();
+ emit_addimm(temp2,ram_offset,HOST_TEMPREG);
+ fastio_reg_override=HOST_TEMPREG;
+ }
+ if (opcode[i]==0x22||opcode[i]==0x26) {
+ emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
+ }else{
+ emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
+ }
+ }
+ if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
+ if(!c||memtarget) {
+ int a=temp2;
+ if(fastio_reg_override>=0) a=fastio_reg_override;
+ emit_readword_indexed(0,a,temp2);
+ if(fastio_reg_override==HOST_TEMPREG) host_tempreg_release();
+ if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj[i],reglist);
+ }
+ else
+ inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
+ if(rt1[i]) {
+ assert(tl>=0);
+ emit_andimm(temp,24,temp);
+ if (opcode[i]==0x22) // LWL
+ emit_xorimm(temp,24,temp);
+ host_tempreg_acquire();
+ emit_movimm(-1,HOST_TEMPREG);
+ if (opcode[i]==0x26) {
+ emit_shr(temp2,temp,temp2);
+ emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
+ }else{
+ emit_shl(temp2,temp,temp2);
+ emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
+ }
+ host_tempreg_release();
+ emit_or(temp2,tl,tl);
+ }
+ //emit_storereg(rt1[i],tl); // DEBUG
+ }
+ if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
+ assert(0);
+ }
}
#endif
enum stub_type type;
int memtarget=0,c=0;
int agr=AGEN1+(i&1);
- int faststore_reg_override=0;
+ int fastio_reg_override=-1;
u_int hr,reglist=0;
tl=get_reg(i_regs->regmap,rs2[i]);
s=get_reg(i_regs->regmap,rs1[i]);
if(offset||s<0||c) addr=temp;
else addr=s;
if(!c) {
- jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
+ jaddr=emit_fastpath_cmp_jump(i,addr,&fastio_reg_override);
}
else if(ram_offset&&memtarget) {
+ host_tempreg_acquire();
emit_addimm(addr,ram_offset,HOST_TEMPREG);
- faststore_reg_override=HOST_TEMPREG;
+ fastio_reg_override=HOST_TEMPREG;
}
if (opcode[i]==0x28) { // SB
if(!c||memtarget) {
int x=0,a=temp;
if(!c) a=addr;
- if(faststore_reg_override) a=faststore_reg_override;
+ if(fastio_reg_override>=0) a=fastio_reg_override;
emit_writebyte_indexed(tl,x,a);
}
type=STOREB_STUB;
if(!c||memtarget) {
int x=0,a=temp;
if(!c) a=addr;
- if(faststore_reg_override) a=faststore_reg_override;
+ if(fastio_reg_override>=0) a=fastio_reg_override;
emit_writehword_indexed(tl,x,a);
}
type=STOREH_STUB;
if (opcode[i]==0x2B) { // SW
if(!c||memtarget) {
int a=addr;
- if(faststore_reg_override) a=faststore_reg_override;
+ if(fastio_reg_override>=0) a=fastio_reg_override;
emit_writeword_indexed(tl,0,a);
}
type=STOREW_STUB;
assert(0);
type=STORED_STUB;
}
+ if(fastio_reg_override==HOST_TEMPREG)
+ host_tempreg_release();
if(jaddr) {
// PCSX store handlers don't check invcode again
reglist|=1<<addr;
}
// basic current block modification detection..
// not looking back as that should be in mips cache already
+ // (see Spyro2 title->attract mode)
if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
assert(i_regs->regmap==regs[i].regmap); // not delay slot
if(i_regs->regmap==regs[i].regmap) {
- load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
- wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
+ load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
+ wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
emit_movimm(start+i*4+4,0);
emit_writeword(0,&pcaddr);
- emit_jmp(do_interrupt);
+ emit_addimm(HOST_CCREG,2,HOST_CCREG);
+ emit_call(get_addr_ht);
+ emit_jmpreg(0);
}
}
}
-void storelr_assemble(int i,struct regstat *i_regs)
+static void storelr_assemble(int i,struct regstat *i_regs)
{
int s,tl;
int temp;
emit_jmp(0);
}
}
- emit_addimm_no_flags(ram_offset,temp);
+ if(ram_offset)
+ emit_addimm_no_flags(ram_offset,temp);
if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
assert(0);
if (opcode[i]==0x2A) { // SWL
emit_writeword_indexed(tl,0,temp);
}
- if (opcode[i]==0x2E) { // SWR
+ else if (opcode[i]==0x2E) { // SWR
emit_writebyte_indexed(tl,3,temp);
}
- if (opcode[i]==0x2C) { // SDL
- assert(0);
- }
- if (opcode[i]==0x2D) { // SDR
+ else
assert(0);
- }
done0=out;
emit_jmp(0);
// 1
emit_writebyte_indexed(tl,1,temp);
if(rs2[i]) emit_rorimm(tl,8,tl);
}
- if (opcode[i]==0x2E) { // SWR
+ else if (opcode[i]==0x2E) { // SWR
// Write two lsb into two most significant bytes
emit_writehword_indexed(tl,1,temp);
}
- if (opcode[i]==0x2C) { // SDL
- assert(0);
- }
- if (opcode[i]==0x2D) { // SDR
- assert(0);
- }
done1=out;
emit_jmp(0);
// 2
emit_writehword_indexed(tl,-2,temp);
if(rs2[i]) emit_rorimm(tl,16,tl);
}
- if (opcode[i]==0x2E) { // SWR
+ else if (opcode[i]==0x2E) { // SWR
// Write 3 lsb into three most significant bytes
emit_writebyte_indexed(tl,-1,temp);
if(rs2[i]) emit_rorimm(tl,8,tl);
emit_writehword_indexed(tl,0,temp);
if(rs2[i]) emit_rorimm(tl,24,tl);
}
- if (opcode[i]==0x2C) { // SDL
- assert(0);
- }
- if (opcode[i]==0x2D) { // SDR
- assert(0);
- }
done2=out;
emit_jmp(0);
// 3
emit_writebyte_indexed(tl,-3,temp);
if(rs2[i]) emit_rorimm(tl,8,tl);
}
- if (opcode[i]==0x2E) { // SWR
+ else if (opcode[i]==0x2E) { // SWR
// Write entire word
emit_writeword_indexed(tl,-3,temp);
}
- if (opcode[i]==0x2C) { // SDL
- assert(0);
- }
- if (opcode[i]==0x2D) { // SDR
- assert(0);
- }
set_jump_target(done0, out);
set_jump_target(done1, out);
set_jump_target(done2, out);
- if (opcode[i]==0x2C) { // SDL
- assert(0);
- }
- if (opcode[i]==0x2D) { // SDR
- assert(0);
- }
if(!c||!memtarget)
add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj[i],reglist);
if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
}
}
-void c1ls_assemble(int i,struct regstat *i_regs)
+static void cop0_assemble(int i,struct regstat *i_regs)
+{
+ if(opcode2[i]==0) // MFC0
+ {
+ signed char t=get_reg(i_regs->regmap,rt1[i]);
+ u_int copr=(source[i]>>11)&0x1f;
+ //assert(t>=0); // Why does this happen? OOT is weird
+ if(t>=0&&rt1[i]!=0) {
+ emit_readword(®_cop0[copr],t);
+ }
+ }
+ else if(opcode2[i]==4) // MTC0
+ {
+ signed char s=get_reg(i_regs->regmap,rs1[i]);
+ char copr=(source[i]>>11)&0x1f;
+ assert(s>=0);
+ wb_register(rs1[i],i_regs->regmap,i_regs->dirty);
+ if(copr==9||copr==11||copr==12||copr==13) {
+ emit_readword(&last_count,HOST_TEMPREG);
+ emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
+ emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
+ emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
+ emit_writeword(HOST_CCREG,&Count);
+ }
+ // What a mess. The status register (12) can enable interrupts,
+ // so needs a special case to handle a pending interrupt.
+ // The interrupt must be taken immediately, because a subsequent
+ // instruction might disable interrupts again.
+ if(copr==12||copr==13) {
+ if (is_delayslot) {
+ // burn cycles to cause cc_interrupt, which will
+ // reschedule next_interupt. Relies on CCREG from above.
+ assem_debug("MTC0 DS %d\n", copr);
+ emit_writeword(HOST_CCREG,&last_count);
+ emit_movimm(0,HOST_CCREG);
+ emit_storereg(CCREG,HOST_CCREG);
+ emit_loadreg(rs1[i],1);
+ emit_movimm(copr,0);
+ emit_call(pcsx_mtc0_ds);
+ emit_loadreg(rs1[i],s);
+ return;
+ }
+ emit_movimm(start+i*4+4,HOST_TEMPREG);
+ emit_writeword(HOST_TEMPREG,&pcaddr);
+ emit_movimm(0,HOST_TEMPREG);
+ emit_writeword(HOST_TEMPREG,&pending_exception);
+ }
+ //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
+ //else
+ if(s==HOST_CCREG)
+ emit_loadreg(rs1[i],1);
+ else if(s!=1)
+ emit_mov(s,1);
+ emit_movimm(copr,0);
+ emit_call(pcsx_mtc0);
+ if(copr==9||copr==11||copr==12||copr==13) {
+ emit_readword(&Count,HOST_CCREG);
+ emit_readword(&next_interupt,HOST_TEMPREG);
+ emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
+ emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
+ emit_writeword(HOST_TEMPREG,&last_count);
+ emit_storereg(CCREG,HOST_CCREG);
+ }
+ if(copr==12||copr==13) {
+ assert(!is_delayslot);
+ emit_readword(&pending_exception,14);
+ emit_test(14,14);
+ void *jaddr = out;
+ emit_jeq(0);
+ emit_readword(&pcaddr, 0);
+ emit_addimm(HOST_CCREG,2,HOST_CCREG);
+ emit_call(get_addr_ht);
+ emit_jmpreg(0);
+ set_jump_target(jaddr, out);
+ }
+ emit_loadreg(rs1[i],s);
+ }
+ else
+ {
+ assert(opcode2[i]==0x10);
+ //if((source[i]&0x3f)==0x10) // RFE
+ {
+ emit_readword(&Status,0);
+ emit_andimm(0,0x3c,1);
+ emit_andimm(0,~0xf,0);
+ emit_orrshr_imm(1,2,0);
+ emit_writeword(0,&Status);
+ }
+ }
+}
+
+static void cop1_unusable(int i,struct regstat *i_regs)
+{
+ // XXX: should just just do the exception instead
+ //if(!cop1_usable)
+ {
+ void *jaddr=out;
+ emit_jmp(0);
+ add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
+ }
+}
+
+static void cop1_assemble(int i,struct regstat *i_regs)
{
cop1_unusable(i, i_regs);
}
-void c2ls_assemble(int i,struct regstat *i_regs)
+static void c1ls_assemble(int i,struct regstat *i_regs)
+{
+ cop1_unusable(i, i_regs);
+}
+
+// FP_STUB
+static void do_cop1stub(int n)
+{
+ literal_pool(256);
+ assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
+ set_jump_target(stubs[n].addr, out);
+ int i=stubs[n].a;
+// int rs=stubs[n].b;
+ struct regstat *i_regs=(struct regstat *)stubs[n].c;
+ int ds=stubs[n].d;
+ if(!ds) {
+ load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
+ //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
+ }
+ //else {printf("fp exception in delay slot\n");}
+ wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
+ if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
+ emit_movimm(start+(i-ds)*4,EAX); // Get PC
+ emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
+ emit_jmp(ds?fp_exception_ds:fp_exception);
+}
+
+static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
+{
+ switch (copr) {
+ case 1:
+ case 3:
+ case 5:
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ emit_readword(®_cop2d[copr],tl);
+ emit_signextend16(tl,tl);
+ emit_writeword(tl,®_cop2d[copr]); // hmh
+ break;
+ case 7:
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ emit_readword(®_cop2d[copr],tl);
+ emit_andimm(tl,0xffff,tl);
+ emit_writeword(tl,®_cop2d[copr]);
+ break;
+ case 15:
+ emit_readword(®_cop2d[14],tl); // SXY2
+ emit_writeword(tl,®_cop2d[copr]);
+ break;
+ case 28:
+ case 29:
+ c2op_mfc2_29_assemble(tl,temp);
+ break;
+ default:
+ emit_readword(®_cop2d[copr],tl);
+ break;
+ }
+}
+
+static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
+{
+ switch (copr) {
+ case 15:
+ emit_readword(®_cop2d[13],temp); // SXY1
+ emit_writeword(sl,®_cop2d[copr]);
+ emit_writeword(temp,®_cop2d[12]); // SXY0
+ emit_readword(®_cop2d[14],temp); // SXY2
+ emit_writeword(sl,®_cop2d[14]);
+ emit_writeword(temp,®_cop2d[13]); // SXY1
+ break;
+ case 28:
+ emit_andimm(sl,0x001f,temp);
+ emit_shlimm(temp,7,temp);
+ emit_writeword(temp,®_cop2d[9]);
+ emit_andimm(sl,0x03e0,temp);
+ emit_shlimm(temp,2,temp);
+ emit_writeword(temp,®_cop2d[10]);
+ emit_andimm(sl,0x7c00,temp);
+ emit_shrimm(temp,3,temp);
+ emit_writeword(temp,®_cop2d[11]);
+ emit_writeword(sl,®_cop2d[28]);
+ break;
+ case 30:
+ emit_xorsar_imm(sl,sl,31,temp);
+#if defined(HAVE_ARMV5) || defined(__aarch64__)
+ emit_clz(temp,temp);
+#else
+ emit_movs(temp,HOST_TEMPREG);
+ emit_movimm(0,temp);
+ emit_jeq((int)out+4*4);
+ emit_addpl_imm(temp,1,temp);
+ emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
+ emit_jns((int)out-2*4);
+#endif
+ emit_writeword(sl,®_cop2d[30]);
+ emit_writeword(temp,®_cop2d[31]);
+ break;
+ case 31:
+ break;
+ default:
+ emit_writeword(sl,®_cop2d[copr]);
+ break;
+ }
+}
+
+static void c2ls_assemble(int i,struct regstat *i_regs)
{
int s,tl;
int ar;
void *jaddr2=NULL;
enum stub_type type;
int agr=AGEN1+(i&1);
- int fastio_reg_override=0;
+ int fastio_reg_override=-1;
u_int hr,reglist=0;
u_int copr=(source[i]>>16)&0x1f;
s=get_reg(i_regs->regmap,rs1[i]);
assert(ar>=0);
if (opcode[i]==0x3a) { // SWC2
- cop2_get_dreg(copr,tl,HOST_TEMPREG);
+ cop2_get_dreg(copr,tl,-1);
type=STOREW_STUB;
}
else
jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
}
else if(ram_offset&&memtarget) {
+ host_tempreg_acquire();
emit_addimm(ar,ram_offset,HOST_TEMPREG);
fastio_reg_override=HOST_TEMPREG;
}
if (opcode[i]==0x32) { // LWC2
int a=ar;
- if(fastio_reg_override) a=fastio_reg_override;
+ if(fastio_reg_override>=0) a=fastio_reg_override;
emit_readword_indexed(0,a,tl);
}
if (opcode[i]==0x3a) { // SWC2
if(!offset&&!c&&s>=0) emit_mov(s,ar);
#endif
int a=ar;
- if(fastio_reg_override) a=fastio_reg_override;
+ if(fastio_reg_override>=0) a=fastio_reg_override;
emit_writeword_indexed(tl,0,a);
}
}
+ if(fastio_reg_override==HOST_TEMPREG)
+ host_tempreg_release();
if(jaddr2)
add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj[i],reglist);
if(opcode[i]==0x3a) // SWC2
#endif
}
if (opcode[i]==0x32) { // LWC2
+ host_tempreg_acquire();
cop2_put_dreg(copr,tl,HOST_TEMPREG);
+ host_tempreg_release();
+ }
+}
+
+static void cop2_assemble(int i,struct regstat *i_regs)
+{
+ u_int copr=(source[i]>>11)&0x1f;
+ signed char temp=get_reg(i_regs->regmap,-1);
+ if (opcode2[i]==0) { // MFC2
+ signed char tl=get_reg(i_regs->regmap,rt1[i]);
+ if(tl>=0&&rt1[i]!=0)
+ cop2_get_dreg(copr,tl,temp);
+ }
+ else if (opcode2[i]==4) { // MTC2
+ signed char sl=get_reg(i_regs->regmap,rs1[i]);
+ cop2_put_dreg(copr,sl,temp);
+ }
+ else if (opcode2[i]==2) // CFC2
+ {
+ signed char tl=get_reg(i_regs->regmap,rt1[i]);
+ if(tl>=0&&rt1[i]!=0)
+ emit_readword(®_cop2c[copr],tl);
+ }
+ else if (opcode2[i]==6) // CTC2
+ {
+ signed char sl=get_reg(i_regs->regmap,rs1[i]);
+ switch(copr) {
+ case 4:
+ case 12:
+ case 20:
+ case 26:
+ case 27:
+ case 29:
+ case 30:
+ emit_signextend16(sl,temp);
+ break;
+ case 31:
+ c2op_ctc2_31_assemble(sl,temp);
+ break;
+ default:
+ temp=sl;
+ break;
+ }
+ emit_writeword(temp,®_cop2c[copr]);
+ assert(sl>=0);
+ }
+}
+
+static void do_unalignedwritestub(int n)
+{
+ assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
+ literal_pool(256);
+ set_jump_target(stubs[n].addr, out);
+
+ int i=stubs[n].a;
+ struct regstat *i_regs=(struct regstat *)stubs[n].c;
+ int addr=stubs[n].b;
+ u_int reglist=stubs[n].e;
+ signed char *i_regmap=i_regs->regmap;
+ int temp2=get_reg(i_regmap,FTEMP);
+ int rt;
+ rt=get_reg(i_regmap,rs2[i]);
+ assert(rt>=0);
+ assert(addr>=0);
+ assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
+ reglist|=(1<<addr);
+ reglist&=~(1<<temp2);
+
+#if 1
+ // don't bother with it and call write handler
+ save_regs(reglist);
+ pass_args(addr,rt);
+ int cc=get_reg(i_regmap,CCREG);
+ if(cc<0)
+ emit_loadreg(CCREG,2);
+ emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n].d+1),2);
+ emit_call((opcode[i]==0x2a?jump_handle_swl:jump_handle_swr));
+ emit_addimm(0,-CLOCK_ADJUST((int)stubs[n].d+1),cc<0?2:cc);
+ if(cc<0)
+ emit_storereg(CCREG,2);
+ restore_regs(reglist);
+ emit_jmp(stubs[n].retaddr); // return address
+#else
+ emit_andimm(addr,0xfffffffc,temp2);
+ emit_writeword(temp2,&address);
+
+ save_regs(reglist);
+ emit_shrimm(addr,16,1);
+ int cc=get_reg(i_regmap,CCREG);
+ if(cc<0) {
+ emit_loadreg(CCREG,2);
+ }
+ emit_movimm((u_int)readmem,0);
+ emit_addimm(cc<0?2:cc,2*stubs[n].d+2,2);
+ emit_call((int)&indirect_jump_indexed);
+ restore_regs(reglist);
+
+ emit_readword(&readmem_dword,temp2);
+ int temp=addr; //hmh
+ emit_shlimm(addr,3,temp);
+ emit_andimm(temp,24,temp);
+ if (opcode[i]==0x2a) // SWL
+ emit_xorimm(temp,24,temp);
+ emit_movimm(-1,HOST_TEMPREG);
+ if (opcode[i]==0x2a) { // SWL
+ emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
+ emit_orrshr(rt,temp,temp2);
+ }else{
+ emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
+ emit_orrshl(rt,temp,temp2);
+ }
+ emit_readword(&address,addr);
+ emit_writeword(temp2,&word);
+ //save_regs(reglist); // don't need to, no state changes
+ emit_shrimm(addr,16,1);
+ emit_movimm((u_int)writemem,0);
+ //emit_call((int)&indirect_jump_indexed);
+ emit_mov(15,14);
+ emit_readword_dualindexedx4(0,1,15);
+ emit_readword(&Count,HOST_TEMPREG);
+ emit_readword(&next_interupt,2);
+ emit_addimm(HOST_TEMPREG,-2*stubs[n].d-2,HOST_TEMPREG);
+ emit_writeword(2,&last_count);
+ emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
+ if(cc<0) {
+ emit_storereg(CCREG,HOST_TEMPREG);
}
+ restore_regs(reglist);
+ emit_jmp(stubs[n].retaddr); // return address
+#endif
}
#ifndef multdiv_assemble
void multdiv_assemble(int i,struct regstat *i_regs)
{
printf("Need multdiv_assemble for this architecture.\n");
- exit(1);
+ abort();
}
#endif
-void mov_assemble(int i,struct regstat *i_regs)
+static void mov_assemble(int i,struct regstat *i_regs)
{
//if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
//if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
if(rt1[i]) {
- signed char sh,sl,th,tl;
- th=get_reg(i_regs->regmap,rt1[i]|64);
+ signed char sl,tl;
tl=get_reg(i_regs->regmap,rt1[i]);
//assert(tl>=0);
if(tl>=0) {
- sh=get_reg(i_regs->regmap,rs1[i]|64);
sl=get_reg(i_regs->regmap,rs1[i]);
if(sl>=0) emit_mov(sl,tl);
else emit_loadreg(rs1[i],tl);
- if(th>=0) {
- if(sh>=0) emit_mov(sh,th);
- else emit_loadreg(rs1[i]|64,th);
- }
}
}
}
-#ifndef fconv_assemble
-void fconv_assemble(int i,struct regstat *i_regs)
+// call interpreter, exception handler, things that change pc/regs/cycles ...
+static void call_c_cpu_handler(int i, const struct regstat *i_regs, u_int pc, void *func)
{
- printf("Need fconv_assemble for this architecture.\n");
- exit(1);
+ signed char ccreg=get_reg(i_regs->regmap,CCREG);
+ assert(ccreg==HOST_CCREG);
+ assert(!is_delayslot);
+ (void)ccreg;
+
+ emit_movimm(pc,3); // Get PC
+ emit_readword(&last_count,2);
+ emit_writeword(3,&psxRegs.pc);
+ emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
+ emit_add(2,HOST_CCREG,2);
+ emit_writeword(2,&psxRegs.cycle);
+ emit_call(func);
+ emit_jmp(jump_to_new_pc);
}
-#endif
-#if 0
-void float_assemble(int i,struct regstat *i_regs)
+static void syscall_assemble(int i,struct regstat *i_regs)
{
- printf("Need float_assemble for this architecture.\n");
- exit(1);
+ emit_movimm(0x20,0); // cause code
+ emit_movimm(0,1); // not in delay slot
+ call_c_cpu_handler(i,i_regs,start+i*4,psxException);
}
-#endif
-void syscall_assemble(int i,struct regstat *i_regs)
+static void hlecall_assemble(int i,struct regstat *i_regs)
{
- signed char ccreg=get_reg(i_regs->regmap,CCREG);
- assert(ccreg==HOST_CCREG);
- assert(!is_delayslot);
- (void)ccreg;
- emit_movimm(start+i*4,EAX); // Get PC
- emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
- emit_jmp(jump_syscall_hle); // XXX
+ void *hlefunc = psxNULL;
+ uint32_t hleCode = source[i] & 0x03ffffff;
+ if (hleCode < ARRAY_SIZE(psxHLEt))
+ hlefunc = psxHLEt[hleCode];
+
+ call_c_cpu_handler(i,i_regs,start+i*4+4,hlefunc);
}
-void hlecall_assemble(int i,struct regstat *i_regs)
+static void intcall_assemble(int i,struct regstat *i_regs)
{
- extern void psxNULL();
- signed char ccreg=get_reg(i_regs->regmap,CCREG);
- assert(ccreg==HOST_CCREG);
- assert(!is_delayslot);
- (void)ccreg;
- emit_movimm(start+i*4+4,0); // Get PC
- uint32_t hleCode = source[i] & 0x03ffffff;
- if (hleCode >= ARRAY_SIZE(psxHLEt))
- emit_movimm((uintptr_t)psxNULL,1);
- else
- emit_movimm((uintptr_t)psxHLEt[hleCode],1);
- emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
- emit_jmp(jump_hlecall);
+ call_c_cpu_handler(i,i_regs,start+i*4,execI);
}
-void intcall_assemble(int i,struct regstat *i_regs)
+static void speculate_mov(int rs,int rt)
{
- signed char ccreg=get_reg(i_regs->regmap,CCREG);
- assert(ccreg==HOST_CCREG);
- assert(!is_delayslot);
- (void)ccreg;
- emit_movimm(start+i*4,0); // Get PC
- emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
- emit_jmp(jump_intcall);
+ if(rt!=0) {
+ smrv_strong_next|=1<<rt;
+ smrv[rt]=smrv[rs];
+ }
+}
+
+static void speculate_mov_weak(int rs,int rt)
+{
+ if(rt!=0) {
+ smrv_weak_next|=1<<rt;
+ smrv[rt]=smrv[rs];
+ }
}
-void ds_assemble(int i,struct regstat *i_regs)
+static void speculate_register_values(int i)
+{
+ if(i==0) {
+ memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
+ // gp,sp are likely to stay the same throughout the block
+ smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
+ smrv_weak_next=~smrv_strong_next;
+ //printf(" llr %08x\n", smrv[4]);
+ }
+ smrv_strong=smrv_strong_next;
+ smrv_weak=smrv_weak_next;
+ switch(itype[i]) {
+ case ALU:
+ if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
+ else if((smrv_strong>>rs2[i])&1) speculate_mov(rs2[i],rt1[i]);
+ else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
+ else if((smrv_weak>>rs2[i])&1) speculate_mov_weak(rs2[i],rt1[i]);
+ else {
+ smrv_strong_next&=~(1<<rt1[i]);
+ smrv_weak_next&=~(1<<rt1[i]);
+ }
+ break;
+ case SHIFTIMM:
+ smrv_strong_next&=~(1<<rt1[i]);
+ smrv_weak_next&=~(1<<rt1[i]);
+ // fallthrough
+ case IMM16:
+ if(rt1[i]&&is_const(®s[i],rt1[i])) {
+ int value,hr=get_reg(regs[i].regmap,rt1[i]);
+ if(hr>=0) {
+ if(get_final_value(hr,i,&value))
+ smrv[rt1[i]]=value;
+ else smrv[rt1[i]]=constmap[i][hr];
+ smrv_strong_next|=1<<rt1[i];
+ }
+ }
+ else {
+ if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
+ else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
+ }
+ break;
+ case LOAD:
+ if(start<0x2000&&(rt1[i]==26||(smrv[rt1[i]]>>24)==0xa0)) {
+ // special case for BIOS
+ smrv[rt1[i]]=0xa0000000;
+ smrv_strong_next|=1<<rt1[i];
+ break;
+ }
+ // fallthrough
+ case SHIFT:
+ case LOADLR:
+ case MOV:
+ smrv_strong_next&=~(1<<rt1[i]);
+ smrv_weak_next&=~(1<<rt1[i]);
+ break;
+ case COP0:
+ case COP2:
+ if(opcode2[i]==0||opcode2[i]==2) { // MFC/CFC
+ smrv_strong_next&=~(1<<rt1[i]);
+ smrv_weak_next&=~(1<<rt1[i]);
+ }
+ break;
+ case C2LS:
+ if (opcode[i]==0x32) { // LWC2
+ smrv_strong_next&=~(1<<rt1[i]);
+ smrv_weak_next&=~(1<<rt1[i]);
+ }
+ break;
+ }
+#if 0
+ int r=4;
+ printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
+ ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
+#endif
+}
+
+static void ds_assemble(int i,struct regstat *i_regs)
{
speculate_register_values(i);
is_delayslot=1;
c2ls_assemble(i,i_regs);break;
case C2OP:
c2op_assemble(i,i_regs);break;
- case FCONV:
- fconv_assemble(i,i_regs);break;
- case FLOAT:
- float_assemble(i,i_regs);break;
- case FCOMP:
- fcomp_assemble(i,i_regs);break;
case MULTDIV:
multdiv_assemble(i,i_regs);break;
case MOV:
case RJUMP:
case CJUMP:
case SJUMP:
- case FJUMP:
SysPrintf("Jump in the delay slot. This is probably a bug.\n");
}
is_delayslot=0;
}
// Is the branch target a valid internal jump?
-int internal_branch(uint64_t i_is32,int addr)
+static int internal_branch(int addr)
{
if(addr&1) return 0; // Indirect (register) jump
if(addr>=start && addr<start+slen*4-4)
{
- //int t=(addr-start)>>2;
- // Delay slots are not valid branch targets
- //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
- // 64 -> 32 bit transition requires a recompile
- /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
- {
- if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
- else printf("optimizable: yes\n");
- }*/
- //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
return 1;
}
return 0;
}
-#ifndef wb_invalidate
-void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
- uint64_t u,uint64_t uu)
+static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
{
int hr;
for(hr=0;hr<HOST_REGS;hr++) {
if(pre[hr]>=0) {
if((dirty>>hr)&1) {
if(get_reg(entry,pre[hr])<0) {
- if(pre[hr]<64) {
- if(!((u>>pre[hr])&1)) {
- emit_storereg(pre[hr],hr);
- if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
- emit_sarimm(hr,31,hr);
- emit_storereg(pre[hr]|64,hr);
- }
- }
- }else{
- if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
- emit_storereg(pre[hr],hr);
- }
- }
+ assert(pre[hr]<64);
+ if(!((u>>pre[hr])&1))
+ emit_storereg(pre[hr],hr);
}
}
}
}
}
}
-#endif
// Load the specified registers
// This only loads the registers given as arguments because
// we don't want to load things that will be overwritten
-void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
+static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2)
{
int hr;
// Load 32-bit regs
}
}
}
- //Load 64-bit regs
- for(hr=0;hr<HOST_REGS;hr++) {
- if(hr!=EXCLUDE_REG&®map[hr]>=0) {
- if(entry[hr]!=regmap[hr]) {
- if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
- {
- assert(regmap[hr]!=64);
- if((is32>>(regmap[hr]&63))&1) {
- int lr=get_reg(regmap,regmap[hr]-64);
- if(lr>=0)
- emit_sarimm(lr,31,hr);
- else
- emit_loadreg(regmap[hr],hr);
- }
- else
- {
- emit_loadreg(regmap[hr],hr);
- }
- }
- }
- }
- }
}
// Load registers prior to the start of a loop
*value=constmap[i][hr];
//printf("c=%lx\n",(long)constmap[i][hr]);
if(i==slen-1) return 1;
- if(reg<64) {
- return !((unneeded_reg[i+1]>>reg)&1);
- }else{
- return !((unneeded_reg_upper[i+1]>>reg)&1);
- }
+ assert(reg < 64);
+ return !((unneeded_reg[i+1]>>reg)&1);
}
// Load registers with known constants
-void load_consts(signed char pre[],signed char regmap[],int is32,int i)
+static void load_consts(signed char pre[],signed char regmap[],int i)
{
int hr,hr2;
// propagate loaded constant flags
if(hr!=EXCLUDE_REG&®map[hr]>=0) {
//if(entry[hr]!=regmap[hr]) {
if(!((regs[i].loadedconst>>hr)&1)) {
- if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
+ assert(regmap[hr]<64);
+ if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
int value,similar=0;
if(get_final_value(hr,i,&value)) {
// see if some other register has similar value
}
}
}
- // Load 64-bit regs
- for(hr=0;hr<HOST_REGS;hr++) {
- if(hr!=EXCLUDE_REG&®map[hr]>=0) {
- //if(entry[hr]!=regmap[hr]) {
- if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
- if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
- if((is32>>(regmap[hr]&63))&1) {
- int lr=get_reg(regmap,regmap[hr]-64);
- assert(lr>=0);
- emit_sarimm(lr,31,hr);
- }
- else
- {
- int value;
- if(get_final_value(hr,i,&value)) {
- if(value==0) {
- emit_zeroreg(hr);
- }
- else {
- emit_movimm(value,hr);
- }
- }
- }
- }
- }
- }
- }
}
-void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
+
+void load_all_consts(signed char regmap[], u_int dirty, int i)
{
int hr;
// Load 32-bit regs
for(hr=0;hr<HOST_REGS;hr++) {
if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
- if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
+ assert(regmap[hr] < 64);
+ if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
int value=constmap[i][hr];
if(value==0) {
emit_zeroreg(hr);
}
}
}
- // Load 64-bit regs
- for(hr=0;hr<HOST_REGS;hr++) {
- if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
- if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
- if((is32>>(regmap[hr]&63))&1) {
- int lr=get_reg(regmap,regmap[hr]-64);
- assert(lr>=0);
- emit_sarimm(lr,31,hr);
- }
- else
- {
- int value=constmap[i][hr];
- if(value==0) {
- emit_zeroreg(hr);
- }
- else {
- emit_movimm(value,hr);
- }
- }
- }
- }
- }
}
// Write out all dirty registers (except cycle count)
-void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
+static void wb_dirtys(signed char i_regmap[],uint64_t i_dirty)
{
int hr;
for(hr=0;hr<HOST_REGS;hr++) {
if(i_regmap[hr]>0) {
if(i_regmap[hr]!=CCREG) {
if((i_dirty>>hr)&1) {
- if(i_regmap[hr]<64) {
- emit_storereg(i_regmap[hr],hr);
- }else{
- if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
- emit_storereg(i_regmap[hr],hr);
- }
- }
+ assert(i_regmap[hr]<64);
+ emit_storereg(i_regmap[hr],hr);
}
}
}
}
}
}
+
// Write out dirty registers that we need to reload (pair with load_needed_regs)
// This writes the registers not written by store_regs_bt
-void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
+void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr)
{
int hr;
int t=(addr-start)>>2;
if(hr!=EXCLUDE_REG) {
if(i_regmap[hr]>0) {
if(i_regmap[hr]!=CCREG) {
- if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
+ if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
if((i_dirty>>hr)&1) {
- if(i_regmap[hr]<64) {
- emit_storereg(i_regmap[hr],hr);
- }else{
- if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
- emit_storereg(i_regmap[hr],hr);
- }
- }
+ assert(i_regmap[hr]<64);
+ emit_storereg(i_regmap[hr],hr);
}
}
}
}
}
}
- // Load 64-bit regs
- for(hr=0;hr<HOST_REGS;hr++) {
- if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
- assert(regs[t].regmap_entry[hr]!=64);
- if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
- int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
- if(lr<0) {
- emit_loadreg(regs[t].regmap_entry[hr],hr);
- }
- else
- {
- emit_sarimm(lr,31,hr);
- }
- }
- else
- {
- emit_loadreg(regs[t].regmap_entry[hr],hr);
- }
- }
- }
}
// Store dirty registers prior to branch
-void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
+void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
{
- if(internal_branch(i_is32,addr))
+ if(internal_branch(addr))
{
int t=(addr-start)>>2;
int hr;
for(hr=0;hr<HOST_REGS;hr++) {
- if(hr!=EXCLUDE_REG) {
- if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
- if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
- if((i_dirty>>hr)&1) {
- if(i_regmap[hr]<64) {
- if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
- emit_storereg(i_regmap[hr],hr);
- if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
- #ifdef DESTRUCTIVE_WRITEBACK
- emit_sarimm(hr,31,hr);
- emit_storereg(i_regmap[hr]|64,hr);
- #else
- emit_sarimm(hr,31,HOST_TEMPREG);
- emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
- #endif
- }
- }
- }else{
- if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
- emit_storereg(i_regmap[hr],hr);
- }
- }
+ if(hr!=EXCLUDE_REG) {
+ if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
+ if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
+ if((i_dirty>>hr)&1) {
+ assert(i_regmap[hr]<64);
+ if(!((unneeded_reg[t]>>i_regmap[hr])&1))
+ emit_storereg(i_regmap[hr],hr);
}
}
}
else
{
// Branch out of this block, write out all dirty regs
- wb_dirtys(i_regmap,i_is32,i_dirty);
+ wb_dirtys(i_regmap,i_dirty);
}
}
// Load all needed registers for branch target
-void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
+static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
{
//if(addr>=start && addr<(start+slen*4))
- if(internal_branch(i_is32,addr))
+ if(internal_branch(addr))
{
int t=(addr-start)>>2;
int hr;
// Load 32-bit regs
for(hr=0;hr<HOST_REGS;hr++) {
if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
- #ifdef DESTRUCTIVE_WRITEBACK
- if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
- #else
- if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
- #endif
+ if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
if(regs[t].regmap_entry[hr]==0) {
emit_zeroreg(hr);
}
}
}
}
- //Load 64-bit regs
- for(hr=0;hr<HOST_REGS;hr++) {
- if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
- if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
- assert(regs[t].regmap_entry[hr]!=64);
- if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
- int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
- if(lr<0) {
- emit_loadreg(regs[t].regmap_entry[hr],hr);
- }
- else
- {
- emit_sarimm(lr,31,hr);
- }
- }
- else
- {
- emit_loadreg(regs[t].regmap_entry[hr],hr);
- }
- }
- else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
- int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
- assert(lr>=0);
- emit_sarimm(lr,31,hr);
- }
- }
- }
}
}
-int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
+static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
{
if(addr>=start && addr<start+slen*4-4)
{
}
else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
{
- if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
- return 0;
+ assert(0);
}
}
}
}
}
}
- if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
- {
- //printf("%x: is32 no match\n",addr);
- return 0;
- }
}
}
}
- //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
// Delay slots are not valid branch targets
- //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
+ //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP)) return 0;
// Delay slots require additional processing, so do not match
if(is_ds[t]) return 0;
}
static void drc_dbg_emit_do_cmp(int i)
{
extern void do_insn_cmp();
- extern int cycle;
+ //extern int cycle;
u_int hr,reglist=0;
for(hr=0;hr<HOST_REGS;hr++)
//emit_readword(&cycle,0);
//emit_addimm(0,2,0);
//emit_writeword(0,&cycle);
+ (void)get_reg2;
restore_regs(reglist);
}
#else
#endif
// Used when a branch jumps into the delay slot of another branch
-void ds_assemble_entry(int i)
+static void ds_assemble_entry(int i)
{
int t=(ba[i]-start)>>2;
if (!instr_addr[t])
assem_debug("<->\n");
drc_dbg_emit_do_cmp(t);
if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
- wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
- load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
+ wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
+ load_regs(regs[t].regmap_entry,regs[t].regmap,rs1[t],rs2[t]);
address_generation(t,®s[t],regs[t].regmap_entry);
if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
- load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
- cop1_usable=0;
+ load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP);
is_delayslot=0;
switch(itype[t]) {
case ALU:
c2ls_assemble(t,®s[t]);break;
case C2OP:
c2op_assemble(t,®s[t]);break;
- case FCONV:
- fconv_assemble(t,®s[t]);break;
- case FLOAT:
- float_assemble(t,®s[t]);break;
- case FCOMP:
- fcomp_assemble(t,®s[t]);break;
case MULTDIV:
multdiv_assemble(t,®s[t]);break;
case MOV:
case RJUMP:
case CJUMP:
case SJUMP:
- case FJUMP:
SysPrintf("Jump in the delay slot. This is probably a bug.\n");
}
- store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
- load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
- if(internal_branch(regs[t].is32,ba[i]+4))
+ store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
+ load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
+ if(internal_branch(ba[i]+4))
assem_debug("branch: internal\n");
else
assem_debug("branch: external\n");
- assert(internal_branch(regs[t].is32,ba[i]+4));
- add_to_linker(out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
+ assert(internal_branch(ba[i]+4));
+ add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
emit_jmp(0);
}
+static void emit_extjump(void *addr, u_int target)
+{
+ emit_extjump2(addr, target, dyna_linker);
+}
+
+static void emit_extjump_ds(void *addr, u_int target)
+{
+ emit_extjump2(addr, target, dyna_linker_ds);
+}
+
+// Load 2 immediates optimizing for small code size
+static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
+{
+ emit_movimm(imm1,rt1);
+ emit_movimm_from(imm1,rt1,imm2,rt2);
+}
+
void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
{
int count;
*adj=0;
}
//if(ba[i]>=start && ba[i]<(start+slen*4))
- if(internal_branch(branch_regs[i].is32,ba[i]))
+ if(internal_branch(ba[i]))
{
t=(ba[i]-start)>>2;
if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
static void do_ccstub(int n)
{
literal_pool(256);
- assem_debug("do_ccstub %x\n",start+stubs[n].b*4);
+ assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
set_jump_target(stubs[n].addr, out);
int i=stubs[n].b;
if(stubs[n].d==NULLDS) {
// Delay slot instruction is nullified ("likely" branch)
- wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
+ wb_dirtys(regs[i].regmap,regs[i].dirty);
}
else if(stubs[n].d!=TAKEN) {
- wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
+ wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
}
else {
- if(internal_branch(branch_regs[i].is32,ba[i]))
- wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
+ if(internal_branch(ba[i]))
+ wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
}
if(stubs[n].c!=-1)
{
else
{
// Return address depends on which way the branch goes
- if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
+ if(itype[i]==CJUMP||itype[i]==SJUMP)
{
int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
- int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
- int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
if(rs1[i]==0)
{
- s1l=s2l;s1h=s2h;
- s2l=s2h=-1;
+ s1l=s2l;
+ s2l=-1;
}
else if(rs2[i]==0)
{
- s2l=s2h=-1;
- }
- if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
- s1h=s2h=-1;
+ s2l=-1;
}
assert(s1l>=0);
#ifdef DESTRUCTIVE_WRITEBACK
if(rs1[i]) {
- if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
+ if((branch_regs[i].dirty>>s1l)&&1)
emit_loadreg(rs1[i],s1l);
}
else {
- if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
+ if((branch_regs[i].dirty>>s1l)&1)
emit_loadreg(rs2[i],s1l);
}
if(s2l>=0)
- if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
+ if((branch_regs[i].dirty>>s2l)&1)
emit_loadreg(rs2[i],s2l);
#endif
int hr=0;
if((opcode[i]&0x2f)==4) // BEQ
{
#ifdef HAVE_CMOV_IMM
- if(s1h<0) {
- if(s2l>=0) emit_cmp(s1l,s2l);
- else emit_test(s1l,s1l);
- emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
- }
- else
+ if(s2l>=0) emit_cmp(s1l,s2l);
+ else emit_test(s1l,s1l);
+ emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
+ #else
+ emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
+ if(s2l>=0) emit_cmp(s1l,s2l);
+ else emit_test(s1l,s1l);
+ emit_cmovne_reg(alt,addr);
#endif
- {
- emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
- if(s1h>=0) {
- if(s2h>=0) emit_cmp(s1h,s2h);
- else emit_test(s1h,s1h);
- emit_cmovne_reg(alt,addr);
- }
- if(s2l>=0) emit_cmp(s1l,s2l);
- else emit_test(s1l,s1l);
- emit_cmovne_reg(alt,addr);
- }
}
if((opcode[i]&0x2f)==5) // BNE
{
#ifdef HAVE_CMOV_IMM
- if(s1h<0) {
- if(s2l>=0) emit_cmp(s1l,s2l);
- else emit_test(s1l,s1l);
- emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
- }
- else
+ if(s2l>=0) emit_cmp(s1l,s2l);
+ else emit_test(s1l,s1l);
+ emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
+ #else
+ emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
+ if(s2l>=0) emit_cmp(s1l,s2l);
+ else emit_test(s1l,s1l);
+ emit_cmovne_reg(alt,addr);
#endif
- {
- emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
- if(s1h>=0) {
- if(s2h>=0) emit_cmp(s1h,s2h);
- else emit_test(s1h,s1h);
- emit_cmovne_reg(alt,addr);
- }
- if(s2l>=0) emit_cmp(s1l,s2l);
- else emit_test(s1l,s1l);
- emit_cmovne_reg(alt,addr);
- }
}
if((opcode[i]&0x2f)==6) // BLEZ
{
//emit_movimm(start+i*4+8,addr);
emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
emit_cmpimm(s1l,1);
- if(s1h>=0) emit_mov(addr,ntaddr);
emit_cmovl_reg(alt,addr);
- if(s1h>=0) {
- emit_test(s1h,s1h);
- emit_cmovne_reg(ntaddr,addr);
- emit_cmovs_reg(alt,addr);
- }
}
if((opcode[i]&0x2f)==7) // BGTZ
{
//emit_movimm(start+i*4+8,ntaddr);
emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
emit_cmpimm(s1l,1);
- if(s1h>=0) emit_mov(addr,alt);
emit_cmovl_reg(ntaddr,addr);
- if(s1h>=0) {
- emit_test(s1h,s1h);
- emit_cmovne_reg(alt,addr);
- emit_cmovs_reg(ntaddr,addr);
- }
}
if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
{
//emit_movimm(ba[i],alt);
//emit_movimm(start+i*4+8,addr);
emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
- if(s1h>=0) emit_test(s1h,s1h);
- else emit_test(s1l,s1l);
+ emit_test(s1l,s1l);
emit_cmovs_reg(alt,addr);
}
if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
//emit_movimm(ba[i],addr);
//emit_movimm(start+i*4+8,alt);
emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
- if(s1h>=0) emit_test(s1h,s1h);
- else emit_test(s1l,s1l);
+ emit_test(s1l,s1l);
emit_cmovs_reg(alt,addr);
}
if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
}
emit_writeword(r,&pcaddr);
}
- else {SysPrintf("Unknown branch type in do_ccstub\n");exit(1);}
+ else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
}
// Update cycle count
assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
emit_call(cc_interrupt);
if(stubs[n].a) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((signed int)stubs[n].a),HOST_CCREG);
if(stubs[n].d==TAKEN) {
- if(internal_branch(branch_regs[i].is32,ba[i]))
+ if(internal_branch(ba[i]))
load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
else if(itype[i]==RJUMP) {
if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
}else{
load_all_regs(branch_regs[i].regmap);
}
- emit_jmp(stubs[n].retaddr);
+ if (stubs[n].retaddr)
+ emit_jmp(stubs[n].retaddr);
+ else
+ do_jump_vaddr(stubs[n].e);
}
static void add_to_linker(void *addr, u_int target, int ext)
return_address=start+i*4+8;
if(rt>=0) {
#ifdef USE_MINI_HT
- if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
+ if(internal_branch(return_address)&&rt1[i+1]!=31) {
int temp=-1; // note: must be ds-safe
#ifdef HOST_TEMPREG
temp=HOST_TEMPREG;
}
}
-void ujump_assemble(int i,struct regstat *i_regs)
+static void ujump_assemble(int i,struct regstat *i_regs)
{
int ra_done=0;
if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
}
ds_assemble(i+1,i_regs);
uint64_t bc_unneeded=branch_regs[i].u;
- uint64_t bc_unneeded_upper=branch_regs[i].uu;
bc_unneeded|=1|(1LL<<rt1[i]);
- bc_unneeded_upper|=1|(1LL<<rt1[i]);
- wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
- bc_unneeded,bc_unneeded_upper);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
+ wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
+ load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
if(!ra_done&&rt1[i]==31)
ujump_assemble_write_ra(i);
int cc,adj;
cc=get_reg(branch_regs[i].regmap,CCREG);
assert(cc==HOST_CCREG);
- store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
+ store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
#ifdef REG_PREFETCH
if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
#endif
do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
- load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
- if(internal_branch(branch_regs[i].is32,ba[i]))
+ load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
+ if(internal_branch(ba[i]))
assem_debug("branch: internal\n");
else
assem_debug("branch: external\n");
- if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
+ if(internal_branch(ba[i])&&is_ds[(ba[i]-start)>>2]) {
ds_assemble_entry(i);
}
else {
- add_to_linker(out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
+ add_to_linker(out,ba[i],internal_branch(ba[i]));
emit_jmp(0);
}
}
#endif
}
-void rjump_assemble(int i,struct regstat *i_regs)
+static void rjump_assemble(int i,struct regstat *i_regs)
{
int temp;
int rs,cc;
}
ds_assemble(i+1,i_regs);
uint64_t bc_unneeded=branch_regs[i].u;
- uint64_t bc_unneeded_upper=branch_regs[i].uu;
bc_unneeded|=1|(1LL<<rt1[i]);
- bc_unneeded_upper|=1|(1LL<<rt1[i]);
bc_unneeded&=~(1LL<<rs1[i]);
- wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
- bc_unneeded,bc_unneeded_upper);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
+ wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
+ load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i],CCREG);
if(!ra_done&&rt1[i]!=0)
rjump_assemble_write_ra(i);
cc=get_reg(branch_regs[i].regmap,CCREG);
do_rhash(rs,rh);
}
#endif
- store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
+ store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
#ifdef DESTRUCTIVE_WRITEBACK
- if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
+ if((branch_regs[i].dirty>>rs)&1) {
if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
emit_loadreg(rs1[i],rs);
}
//if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
//assert(adj==0);
emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
- add_stub(CC_STUB,out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
+ add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
// special case for RFE
emit_jmp(0);
else
emit_jns(0);
- //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
+ //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
#ifdef USE_MINI_HT
if(rs1[i]==31) {
do_miniht_jump(rs,rh,ht);
else
#endif
{
- emit_jmp(jump_vaddr_reg[rs]);
+ do_jump_vaddr(rs);
}
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
#endif
}
-void cjump_assemble(int i,struct regstat *i_regs)
+static void cjump_assemble(int i,struct regstat *i_regs)
{
signed char *i_regmap=i_regs->regmap;
int cc;
int match;
- match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
+ match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
assem_debug("match=%d\n",match);
- int s1h,s1l,s2h,s2l;
- int prev_cop1_usable=cop1_usable;
+ int s1l,s2l;
int unconditional=0,nop=0;
- int only32=0;
int invert=0;
- int internal=internal_branch(branch_regs[i].is32,ba[i]);
+ int internal=internal_branch(ba[i]);
if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
if(!match) invert=1;
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
if(i>(ba[i]-start)>>2) invert=1;
#endif
+ #ifdef __aarch64__
+ invert=1; // because of near cond. branches
+ #endif
if(ooo[i]) {
s1l=get_reg(branch_regs[i].regmap,rs1[i]);
- s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
s2l=get_reg(branch_regs[i].regmap,rs2[i]);
- s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
}
else {
s1l=get_reg(i_regmap,rs1[i]);
- s1h=get_reg(i_regmap,rs1[i]|64);
s2l=get_reg(i_regmap,rs2[i]);
- s2h=get_reg(i_regmap,rs2[i]|64);
}
if(rs1[i]==0&&rs2[i]==0)
{
}
else if(rs1[i]==0)
{
- s1l=s2l;s1h=s2h;
- s2l=s2h=-1;
- only32=(regs[i].was32>>rs2[i])&1;
+ s1l=s2l;
+ s2l=-1;
}
else if(rs2[i]==0)
{
- s2l=s2h=-1;
- only32=(regs[i].was32>>rs1[i])&1;
- }
- else {
- only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
+ s2l=-1;
}
if(ooo[i]) {
ds_assemble(i+1,i_regs);
int adj;
uint64_t bc_unneeded=branch_regs[i].u;
- uint64_t bc_unneeded_upper=branch_regs[i].uu;
bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
- bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
bc_unneeded|=1;
- bc_unneeded_upper|=1;
- wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
- bc_unneeded,bc_unneeded_upper);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
+ wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
+ load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i],rs2[i]);
+ load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
cc=get_reg(branch_regs[i].regmap,CCREG);
assert(cc==HOST_CCREG);
if(unconditional)
- store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
+ store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
//do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
//assem_debug("cycle count (adj)\n");
if(unconditional) {
do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
- load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
+ load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
if(internal)
assem_debug("branch: internal\n");
else
void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
- if(!only32)
- {
- assert(s1h>=0);
- if(opcode[i]==4) // BEQ
- {
- if(s2h>=0) emit_cmp(s1h,s2h);
- else emit_test(s1h,s1h);
- nottaken1=out;
- emit_jne((void *)1l);
- }
- if(opcode[i]==5) // BNE
- {
- if(s2h>=0) emit_cmp(s1h,s2h);
- else emit_test(s1h,s1h);
- if(invert) taken=out;
- else add_to_linker(out,ba[i],internal);
- emit_jne(0);
- }
- if(opcode[i]==6) // BLEZ
- {
- emit_test(s1h,s1h);
- if(invert) taken=out;
- else add_to_linker(out,ba[i],internal);
- emit_js(0);
- nottaken1=out;
- emit_jne((void *)1l);
- }
- if(opcode[i]==7) // BGTZ
- {
- emit_test(s1h,s1h);
- nottaken1=out;
- emit_js(1);
- if(invert) taken=out;
- else add_to_linker(out,ba[i],internal);
- emit_jne(0);
- }
- } // if(!only32)
//printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
assert(s1l>=0);
else emit_test(s1l,s1l);
if(invert){
nottaken=out;
- emit_jne((void *)1l);
+ emit_jne(DJT_1);
}else{
add_to_linker(out,ba[i],internal);
emit_jeq(0);
else emit_test(s1l,s1l);
if(invert){
nottaken=out;
- emit_jeq(1);
+ emit_jeq(DJT_1);
}else{
add_to_linker(out,ba[i],internal);
emit_jne(0);
emit_cmpimm(s1l,1);
if(invert){
nottaken=out;
- emit_jge(1);
+ emit_jge(DJT_1);
}else{
add_to_linker(out,ba[i],internal);
emit_jl(0);
emit_cmpimm(s1l,1);
if(invert){
nottaken=out;
- emit_jl(1);
+ emit_jl(DJT_1);
}else{
add_to_linker(out,ba[i],internal);
emit_jge(0);
#endif
{
if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
- store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
- load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
+ store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
+ load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
if(internal)
assem_debug("branch: internal\n");
else
//printf("IOE\n");
void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
if(!unconditional&&!nop) {
- if(!only32)
- {
- assert(s1h>=0);
- if((opcode[i]&0x2f)==4) // BEQ
- {
- if(s2h>=0) emit_cmp(s1h,s2h);
- else emit_test(s1h,s1h);
- nottaken1=out;
- emit_jne((void *)2l);
- }
- if((opcode[i]&0x2f)==5) // BNE
- {
- if(s2h>=0) emit_cmp(s1h,s2h);
- else emit_test(s1h,s1h);
- taken=out;
- emit_jne((void *)1l);
- }
- if((opcode[i]&0x2f)==6) // BLEZ
- {
- emit_test(s1h,s1h);
- taken=out;
- emit_js(1);
- nottaken1=out;
- emit_jne((void *)2l);
- }
- if((opcode[i]&0x2f)==7) // BGTZ
- {
- emit_test(s1h,s1h);
- nottaken1=out;
- emit_js(2);
- taken=out;
- emit_jne((void *)1l);
- }
- } // if(!only32)
-
//printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
assert(s1l>=0);
if((opcode[i]&0x2f)==4) // BEQ
if(s2l>=0) emit_cmp(s1l,s2l);
else emit_test(s1l,s1l);
nottaken=out;
- emit_jne((void *)2l);
+ emit_jne(DJT_2);
}
if((opcode[i]&0x2f)==5) // BNE
{
if(s2l>=0) emit_cmp(s1l,s2l);
else emit_test(s1l,s1l);
nottaken=out;
- emit_jeq(2);
+ emit_jeq(DJT_2);
}
if((opcode[i]&0x2f)==6) // BLEZ
{
emit_cmpimm(s1l,1);
nottaken=out;
- emit_jge(2);
+ emit_jge(DJT_2);
}
if((opcode[i]&0x2f)==7) // BGTZ
{
emit_cmpimm(s1l,1);
nottaken=out;
- emit_jl(2);
+ emit_jl(DJT_2);
}
} // if(!unconditional)
int adj;
uint64_t ds_unneeded=branch_regs[i].u;
- uint64_t ds_unneeded_upper=branch_regs[i].uu;
ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
- ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
- if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
ds_unneeded|=1;
- ds_unneeded_upper|=1;
// branch taken
if(!nop) {
if(taken) set_jump_target(taken, out);
assem_debug("1:\n");
- wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
- ds_unneeded,ds_unneeded_upper);
+ wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
// load regs
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
+ load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i+1],rs2[i+1]);
address_generation(i+1,&branch_regs[i],0);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
+ load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
ds_assemble(i+1,&branch_regs[i]);
cc=get_reg(branch_regs[i].regmap,CCREG);
if(cc==-1) {
// CHECK: Is the following instruction (fall thru) allocated ok?
}
assert(cc==HOST_CCREG);
- store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
+ store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
assem_debug("cycle count (adj)\n");
if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
- load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
+ load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
if(internal)
assem_debug("branch: internal\n");
else
}
}
// branch not taken
- cop1_usable=prev_cop1_usable;
if(!unconditional) {
if(nottaken1) set_jump_target(nottaken1, out);
set_jump_target(nottaken, out);
assem_debug("2:\n");
if(!likely[i]) {
- wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
- ds_unneeded,ds_unneeded_upper);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
+ wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
+ load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i+1],rs2[i+1]);
address_generation(i+1,&branch_regs[i],0);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
+ load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
ds_assemble(i+1,&branch_regs[i]);
}
cc=get_reg(branch_regs[i].regmap,CCREG);
}
}
-void sjump_assemble(int i,struct regstat *i_regs)
+static void sjump_assemble(int i,struct regstat *i_regs)
{
signed char *i_regmap=i_regs->regmap;
int cc;
int match;
- match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
+ match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
assem_debug("smatch=%d\n",match);
- int s1h,s1l;
- int prev_cop1_usable=cop1_usable;
+ int s1l;
int unconditional=0,nevertaken=0;
- int only32=0;
int invert=0;
- int internal=internal_branch(branch_regs[i].is32,ba[i]);
+ int internal=internal_branch(ba[i]);
if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
if(!match) invert=1;
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
if(i>(ba[i]-start)>>2) invert=1;
#endif
+ #ifdef __aarch64__
+ invert=1; // because of near cond. branches
+ #endif
//if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
//assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
if(ooo[i]) {
s1l=get_reg(branch_regs[i].regmap,rs1[i]);
- s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
}
else {
s1l=get_reg(i_regmap,rs1[i]);
- s1h=get_reg(i_regmap,rs1[i]|64);
}
if(rs1[i]==0)
{
//assert(opcode2[i]!=0x10);
//assert(opcode2[i]!=0x12);
}
- else {
- only32=(regs[i].was32>>rs1[i])&1;
- }
if(ooo[i]) {
// Out of order execution (delay slot first)
ds_assemble(i+1,i_regs);
int adj;
uint64_t bc_unneeded=branch_regs[i].u;
- uint64_t bc_unneeded_upper=branch_regs[i].uu;
bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
- bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
bc_unneeded|=1;
- bc_unneeded_upper|=1;
- wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
- bc_unneeded,bc_unneeded_upper);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
+ wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
+ load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i],rs1[i]);
+ load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
if(rt1[i]==31) {
int rt,return_address;
rt=get_reg(branch_regs[i].regmap,31);
cc=get_reg(branch_regs[i].regmap,CCREG);
assert(cc==HOST_CCREG);
if(unconditional)
- store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
+ store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
//do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
assem_debug("cycle count (adj)\n");
if(unconditional) {
do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
- load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
+ load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
if(internal)
assem_debug("branch: internal\n");
else
void *nottaken = NULL;
do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
- if(!only32)
- {
- assert(s1h>=0);
- if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
- {
- emit_test(s1h,s1h);
- if(invert){
- nottaken=out;
- emit_jns(1);
- }else{
- add_to_linker(out,ba[i],internal);
- emit_js(0);
- }
- }
- if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
- {
- emit_test(s1h,s1h);
- if(invert){
- nottaken=out;
- emit_js(1);
- }else{
- add_to_linker(out,ba[i],internal);
- emit_jns(0);
- }
- }
- } // if(!only32)
- else
{
assert(s1l>=0);
if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
emit_test(s1l,s1l);
if(invert){
nottaken=out;
- emit_jns(1);
+ emit_jns(DJT_1);
}else{
add_to_linker(out,ba[i],internal);
emit_js(0);
emit_test(s1l,s1l);
if(invert){
nottaken=out;
- emit_js(1);
+ emit_js(DJT_1);
}else{
add_to_linker(out,ba[i],internal);
emit_jns(0);
}
}
- } // if(!only32)
+ }
if(invert) {
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
#endif
{
if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
- store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
- load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
+ store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
+ load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
if(internal)
assem_debug("branch: internal\n");
else
}
if(!unconditional) {
//printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
- if(!only32)
- {
- assert(s1h>=0);
- if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
- {
- emit_test(s1h,s1h);
- nottaken=out;
- emit_jns(1);
- }
- if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
- {
- emit_test(s1h,s1h);
- nottaken=out;
- emit_js(1);
- }
- } // if(!only32)
- else
- {
assert(s1l>=0);
if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
{
emit_test(s1l,s1l);
nottaken=out;
- emit_jns(1);
+ emit_jns(DJT_1);
}
if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
{
emit_test(s1l,s1l);
nottaken=out;
- emit_js(1);
+ emit_js(DJT_1);
}
- }
} // if(!unconditional)
int adj;
uint64_t ds_unneeded=branch_regs[i].u;
- uint64_t ds_unneeded_upper=branch_regs[i].uu;
ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
- ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
- if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
ds_unneeded|=1;
- ds_unneeded_upper|=1;
// branch taken
if(!nevertaken) {
//assem_debug("1:\n");
- wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
- ds_unneeded,ds_unneeded_upper);
+ wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
// load regs
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
+ load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i+1],rs2[i+1]);
address_generation(i+1,&branch_regs[i],0);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
+ load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
ds_assemble(i+1,&branch_regs[i]);
cc=get_reg(branch_regs[i].regmap,CCREG);
if(cc==-1) {
// CHECK: Is the following instruction (fall thru) allocated ok?
}
assert(cc==HOST_CCREG);
- store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
+ store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
assem_debug("cycle count (adj)\n");
if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
- load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
+ load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
if(internal)
- assem_debug("branch: internal\n");
- else
- assem_debug("branch: external\n");
- if(internal&&is_ds[(ba[i]-start)>>2]) {
- ds_assemble_entry(i);
- }
- else {
- add_to_linker(out,ba[i],internal);
- emit_jmp(0);
- }
- }
- // branch not taken
- cop1_usable=prev_cop1_usable;
- if(!unconditional) {
- set_jump_target(nottaken, out);
- assem_debug("1:\n");
- if(!likely[i]) {
- wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
- ds_unneeded,ds_unneeded_upper);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
- address_generation(i+1,&branch_regs[i],0);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
- ds_assemble(i+1,&branch_regs[i]);
- }
- cc=get_reg(branch_regs[i].regmap,CCREG);
- if(cc==-1&&!likely[i]) {
- // Cycle count isn't in a register, temporarily load it then write it out
- emit_loadreg(CCREG,HOST_CCREG);
- emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
- void *jaddr=out;
- emit_jns(0);
- add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
- emit_storereg(CCREG,HOST_CCREG);
- }
- else{
- cc=get_reg(i_regmap,CCREG);
- assert(cc==HOST_CCREG);
- emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
- void *jaddr=out;
- emit_jns(0);
- add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
- }
- }
- }
-}
-
-void fjump_assemble(int i,struct regstat *i_regs)
-{
- signed char *i_regmap=i_regs->regmap;
- int cc;
- int match;
- match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
- assem_debug("fmatch=%d\n",match);
- int fs,cs;
- void *eaddr;
- int invert=0;
- int internal=internal_branch(branch_regs[i].is32,ba[i]);
- if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
- if(!match) invert=1;
- #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
- if(i>(ba[i]-start)>>2) invert=1;
- #endif
-
- if(ooo[i]) {
- fs=get_reg(branch_regs[i].regmap,FSREG);
- address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
- }
- else {
- fs=get_reg(i_regmap,FSREG);
- }
-
- // Check cop1 unusable
- if(!cop1_usable) {
- cs=get_reg(i_regmap,CSREG);
- assert(cs>=0);
- emit_testimm(cs,0x20000000);
- eaddr=out;
- emit_jeq(0);
- add_stub_r(FP_STUB,eaddr,out,i,cs,i_regs,0,0);
- cop1_usable=1;
- }
-
- if(ooo[i]) {
- // Out of order execution (delay slot first)
- //printf("OOOE\n");
- ds_assemble(i+1,i_regs);
- int adj;
- uint64_t bc_unneeded=branch_regs[i].u;
- uint64_t bc_unneeded_upper=branch_regs[i].uu;
- bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
- bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
- bc_unneeded|=1;
- bc_unneeded_upper|=1;
- wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
- bc_unneeded,bc_unneeded_upper);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
- cc=get_reg(branch_regs[i].regmap,CCREG);
- assert(cc==HOST_CCREG);
- do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
- assem_debug("cycle count (adj)\n");
- if(1) {
- void *nottaken = NULL;
- if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
- if(1) {
- assert(fs>=0);
- emit_testimm(fs,0x800000);
- if(source[i]&0x10000) // BC1T
- {
- if(invert){
- nottaken=out;
- emit_jeq(1);
- }else{
- add_to_linker(out,ba[i],internal);
- emit_jne(0);
- }
- }
- else // BC1F
- if(invert){
- nottaken=out;
- emit_jne((void *)1l);
- }else{
- add_to_linker(out,ba[i],internal);
- emit_jeq(0);
- }
- {
- }
- } // if(!only32)
-
- if(invert) {
- if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
- #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
- else if(match) emit_addnop(13);
- #endif
- store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
- load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
- if(internal)
- assem_debug("branch: internal\n");
- else
- assem_debug("branch: external\n");
- if(internal&&is_ds[(ba[i]-start)>>2]) {
- ds_assemble_entry(i);
- }
- else {
- add_to_linker(out,ba[i],internal);
- emit_jmp(0);
- }
- set_jump_target(nottaken, out);
- }
-
- if(adj) {
- if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
- }
- } // (!unconditional)
- } // if(ooo)
- else
- {
- // In-order execution (branch first)
- //printf("IOE\n");
- void *nottaken = NULL;
- if(1) {
- //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
- if(1) {
- assert(fs>=0);
- emit_testimm(fs,0x800000);
- if(source[i]&0x10000) // BC1T
- {
- nottaken=out;
- emit_jeq(1);
- }
- else // BC1F
- {
- nottaken=out;
- emit_jne((void *)1l);
- }
+ assem_debug("branch: internal\n");
+ else
+ assem_debug("branch: external\n");
+ if(internal&&is_ds[(ba[i]-start)>>2]) {
+ ds_assemble_entry(i);
+ }
+ else {
+ add_to_linker(out,ba[i],internal);
+ emit_jmp(0);
}
- } // if(!unconditional)
- int adj;
- uint64_t ds_unneeded=branch_regs[i].u;
- uint64_t ds_unneeded_upper=branch_regs[i].uu;
- ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
- ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
- if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
- ds_unneeded|=1;
- ds_unneeded_upper|=1;
- // branch taken
- //assem_debug("1:\n");
- wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
- ds_unneeded,ds_unneeded_upper);
- // load regs
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
- address_generation(i+1,&branch_regs[i],0);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
- ds_assemble(i+1,&branch_regs[i]);
- cc=get_reg(branch_regs[i].regmap,CCREG);
- if(cc==-1) {
- emit_loadreg(CCREG,cc=HOST_CCREG);
- // CHECK: Is the following instruction (fall thru) allocated ok?
- }
- assert(cc==HOST_CCREG);
- store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
- do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
- assem_debug("cycle count (adj)\n");
- if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
- load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
- if(internal)
- assem_debug("branch: internal\n");
- else
- assem_debug("branch: external\n");
- if(internal&&is_ds[(ba[i]-start)>>2]) {
- ds_assemble_entry(i);
- }
- else {
- add_to_linker(out,ba[i],internal);
- emit_jmp(0);
}
-
// branch not taken
- if(1) { // <- FIXME (don't need this)
+ if(!unconditional) {
set_jump_target(nottaken, out);
assem_debug("1:\n");
if(!likely[i]) {
- wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
- ds_unneeded,ds_unneeded_upper);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
+ wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
+ load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i+1],rs2[i+1]);
address_generation(i+1,&branch_regs[i],0);
- load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
+ load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
ds_assemble(i+1,&branch_regs[i]);
}
cc=get_reg(branch_regs[i].regmap,CCREG);
static void pagespan_assemble(int i,struct regstat *i_regs)
{
int s1l=get_reg(i_regs->regmap,rs1[i]);
- int s1h=get_reg(i_regs->regmap,rs1[i]|64);
int s2l=get_reg(i_regs->regmap,rs2[i]);
- int s2h=get_reg(i_regs->regmap,rs2[i]|64);
void *taken = NULL;
void *nottaken = NULL;
int unconditional=0;
if(rs1[i]==0)
{
- s1l=s2l;s1h=s2h;
- s2l=s2h=-1;
+ s1l=s2l;
+ s2l=-1;
}
else if(rs2[i]==0)
{
- s2l=s2h=-1;
- }
- if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
- s1h=s2h=-1;
+ s2l=-1;
}
int hr=0;
int addr=-1,alt=-1,ntaddr=-1;
}
assert(hr<HOST_REGS);
if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
- load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
+ load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
}
emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
if(opcode[i]==2) // J
}
else
#ifdef HAVE_CMOV_IMM
- if(s1h<0) {
+ if(1) {
if(s2l>=0) emit_cmp(s1l,s2l);
else emit_test(s1l,s1l);
emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
{
assert(s1l>=0);
emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
- if(s1h>=0) {
- if(s2h>=0) emit_cmp(s1h,s2h);
- else emit_test(s1h,s1h);
- emit_cmovne_reg(alt,addr);
- }
if(s2l>=0) emit_cmp(s1l,s2l);
else emit_test(s1l,s1l);
emit_cmovne_reg(alt,addr);
if((opcode[i]&0x3f)==5) // BNE
{
#ifdef HAVE_CMOV_IMM
- if(s1h<0) {
- if(s2l>=0) emit_cmp(s1l,s2l);
- else emit_test(s1l,s1l);
- emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
- }
- else
+ if(s2l>=0) emit_cmp(s1l,s2l);
+ else emit_test(s1l,s1l);
+ emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
+ #else
+ assert(s1l>=0);
+ emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
+ if(s2l>=0) emit_cmp(s1l,s2l);
+ else emit_test(s1l,s1l);
+ emit_cmovne_reg(alt,addr);
#endif
- {
- assert(s1l>=0);
- emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
- if(s1h>=0) {
- if(s2h>=0) emit_cmp(s1h,s2h);
- else emit_test(s1h,s1h);
- emit_cmovne_reg(alt,addr);
- }
- if(s2l>=0) emit_cmp(s1l,s2l);
- else emit_test(s1l,s1l);
- emit_cmovne_reg(alt,addr);
- }
}
if((opcode[i]&0x3f)==0x14) // BEQL
{
- if(s1h>=0) {
- if(s2h>=0) emit_cmp(s1h,s2h);
- else emit_test(s1h,s1h);
- nottaken=out;
- emit_jne(0);
- }
if(s2l>=0) emit_cmp(s1l,s2l);
else emit_test(s1l,s1l);
if(nottaken) set_jump_target(nottaken, out);
}
if((opcode[i]&0x3f)==0x15) // BNEL
{
- if(s1h>=0) {
- if(s2h>=0) emit_cmp(s1h,s2h);
- else emit_test(s1h,s1h);
- taken=out;
- emit_jne(0);
- }
if(s2l>=0) emit_cmp(s1l,s2l);
else emit_test(s1l,s1l);
nottaken=out;
{
emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
emit_cmpimm(s1l,1);
- if(s1h>=0) emit_mov(addr,ntaddr);
emit_cmovl_reg(alt,addr);
- if(s1h>=0) {
- emit_test(s1h,s1h);
- emit_cmovne_reg(ntaddr,addr);
- emit_cmovs_reg(alt,addr);
- }
}
if((opcode[i]&0x3f)==7) // BGTZ
{
emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
emit_cmpimm(s1l,1);
- if(s1h>=0) emit_mov(addr,alt);
emit_cmovl_reg(ntaddr,addr);
- if(s1h>=0) {
- emit_test(s1h,s1h);
- emit_cmovne_reg(alt,addr);
- emit_cmovs_reg(ntaddr,addr);
- }
}
if((opcode[i]&0x3f)==0x16) // BLEZL
{
}
assert(i_regs->regmap[HOST_CCREG]==CCREG);
- wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
+ wb_dirtys(regs[i].regmap,regs[i].dirty);
if(likely[i]||unconditional)
{
emit_movimm(ba[i],HOST_BTREG);
if(likely[i]) {
// Not-taken path
set_jump_target(nottaken, out);
- wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
+ wb_dirtys(regs[i].regmap,regs[i].dirty);
void *branch_addr=out;
emit_jmp(0);
int target_addr=start+i*4+8;
ll_add(jump_in+page,vaddr,(void *)out);
assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
if(regs[0].regmap[HOST_CCREG]!=CCREG)
- wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
+ wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty);
if(regs[0].regmap[HOST_BTREG]!=BTREG)
emit_writeword(HOST_BTREG,&branch_target);
- load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
+ load_regs(regs[0].regmap_entry,regs[0].regmap,rs1[0],rs2[0]);
address_generation(0,®s[0],regs[0].regmap_entry);
if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
- load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
- cop1_usable=0;
+ load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP);
is_delayslot=0;
switch(itype[0]) {
case ALU:
c2ls_assemble(0,®s[0]);break;
case C2OP:
c2op_assemble(0,®s[0]);break;
- case FCONV:
- fconv_assemble(0,®s[0]);break;
- case FLOAT:
- float_assemble(0,®s[0]);break;
- case FCOMP:
- fcomp_assemble(0,®s[0]);break;
case MULTDIV:
multdiv_assemble(0,®s[0]);break;
case MOV:
case RJUMP:
case CJUMP:
case SJUMP:
- case FJUMP:
SysPrintf("Jump in the delay slot. This is probably a bug.\n");
}
int btaddr=get_reg(regs[0].regmap,BTREG);
assert(btaddr!=HOST_CCREG);
if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
#ifdef HOST_IMM8
+ host_tempreg_acquire();
emit_movimm(start+4,HOST_TEMPREG);
emit_cmp(btaddr,HOST_TEMPREG);
+ host_tempreg_release();
#else
emit_cmpimm(btaddr,start+4);
#endif
void *branch = out;
emit_jeq(0);
- store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
- emit_jmp(jump_vaddr_reg[btaddr]);
+ store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
+ do_jump_vaddr(btaddr);
set_jump_target(branch, out);
- store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
- load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
+ store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
+ load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
}
// Basic liveness analysis for MIPS registers
void unneeded_registers(int istart,int iend,int r)
{
int i;
- uint64_t u,uu,gte_u,b,bu,gte_bu;
- uint64_t temp_u,temp_uu,temp_gte_u=0;
- uint64_t tdep;
+ uint64_t u,gte_u,b,gte_b;
+ uint64_t temp_u,temp_gte_u=0;
uint64_t gte_u_unknown=0;
if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
gte_u_unknown=~0ll;
if(iend==slen-1) {
- u=1;uu=1;
+ u=1;
gte_u=gte_u_unknown;
}else{
- u=unneeded_reg[iend+1];
- uu=unneeded_reg_upper[iend+1];
- u=1;uu=1;
+ //u=unneeded_reg[iend+1];
+ u=1;
gte_u=gte_unneeded[iend+1];
}
for (i=iend;i>=istart;i--)
{
//printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
- if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
+ if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
{
// If subroutine call, flag return address as a possible branch target
if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
{
// Branch out of this block, flush all regs
u=1;
- uu=1;
gte_u=gte_u_unknown;
- /* Hexagon hack
- if(itype[i]==UJUMP&&rt1[i]==31)
- {
- uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
- }
- if(itype[i]==RJUMP&&rs1[i]==31)
- {
- uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
- }
- if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
- if(itype[i]==UJUMP&&rt1[i]==31)
- {
- //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
- uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
- }
- if(itype[i]==RJUMP&&rs1[i]==31)
- {
- //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
- uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
- }
- }*/
branch_unneeded_reg[i]=u;
- branch_unneeded_reg_upper[i]=uu;
// Merge in delay slot
- tdep=(~uu>>rt1[i+1])&1;
u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
- uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
- uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
- uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
- u|=1;uu|=1;
+ u|=1;
gte_u|=gte_rt[i+1];
gte_u&=~gte_rs[i+1];
// If branch is "likely" (and conditional)
if(likely[i]) {
if(i<slen-1) {
u&=unneeded_reg[i+2];
- uu&=unneeded_reg_upper[i+2];
gte_u&=gte_unneeded[i+2];
}
else
{
u=1;
- uu=1;
gte_u=gte_u_unknown;
}
}
if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
{
// Unconditional branch
- temp_u=1;temp_uu=1;
+ temp_u=1;
temp_gte_u=0;
} else {
// Conditional branch (not taken case)
temp_u=unneeded_reg[i+2];
- temp_uu=unneeded_reg_upper[i+2];
temp_gte_u&=gte_unneeded[i+2];
}
// Merge in delay slot
- tdep=(~temp_uu>>rt1[i+1])&1;
temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
- temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
- temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
- temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
- temp_u|=1;temp_uu|=1;
+ temp_u|=1;
temp_gte_u|=gte_rt[i+1];
temp_gte_u&=~gte_rs[i+1];
// If branch is "likely" (and conditional)
if(likely[i]) {
if(i<slen-1) {
temp_u&=unneeded_reg[i+2];
- temp_uu&=unneeded_reg_upper[i+2];
temp_gte_u&=gte_unneeded[i+2];
}
else
{
temp_u=1;
- temp_uu=1;
temp_gte_u=gte_u_unknown;
}
}
- tdep=(~temp_uu>>rt1[i])&1;
temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
- temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
- temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
- temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
- temp_u|=1;temp_uu|=1;
+ temp_u|=1;
temp_gte_u|=gte_rt[i];
temp_gte_u&=~gte_rs[i];
unneeded_reg[i]=temp_u;
- unneeded_reg_upper[i]=temp_uu;
gte_unneeded[i]=temp_gte_u;
// Only go three levels deep. This recursion can take an
// excessive amount of time if there are a lot of nested loops.
unneeded_registers((ba[i]-start)>>2,i-1,r+1);
}else{
unneeded_reg[(ba[i]-start)>>2]=1;
- unneeded_reg_upper[(ba[i]-start)>>2]=1;
gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
}
} /*else*/ if(1) {
{
// Unconditional branch
u=unneeded_reg[(ba[i]-start)>>2];
- uu=unneeded_reg_upper[(ba[i]-start)>>2];
gte_u=gte_unneeded[(ba[i]-start)>>2];
branch_unneeded_reg[i]=u;
- branch_unneeded_reg_upper[i]=uu;
- //u=1;
- //uu=1;
- //branch_unneeded_reg[i]=u;
- //branch_unneeded_reg_upper[i]=uu;
// Merge in delay slot
- tdep=(~uu>>rt1[i+1])&1;
u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
- uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
- uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
- uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
- u|=1;uu|=1;
+ u|=1;
gte_u|=gte_rt[i+1];
gte_u&=~gte_rs[i+1];
} else {
// Conditional branch
b=unneeded_reg[(ba[i]-start)>>2];
- bu=unneeded_reg_upper[(ba[i]-start)>>2];
- gte_bu=gte_unneeded[(ba[i]-start)>>2];
+ gte_b=gte_unneeded[(ba[i]-start)>>2];
branch_unneeded_reg[i]=b;
- branch_unneeded_reg_upper[i]=bu;
- //b=1;
- //bu=1;
- //branch_unneeded_reg[i]=b;
- //branch_unneeded_reg_upper[i]=bu;
// Branch delay slot
- tdep=(~uu>>rt1[i+1])&1;
b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
- bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
- bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
- bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
- b|=1;bu|=1;
- gte_bu|=gte_rt[i+1];
- gte_bu&=~gte_rs[i+1];
+ b|=1;
+ gte_b|=gte_rt[i+1];
+ gte_b&=~gte_rs[i+1];
// If branch is "likely" then we skip the
// delay slot on the fall-thru path
if(likely[i]) {
u=b;
- uu=bu;
- gte_u=gte_bu;
+ gte_u=gte_b;
if(i<slen-1) {
u&=unneeded_reg[i+2];
- uu&=unneeded_reg_upper[i+2];
gte_u&=gte_unneeded[i+2];
- //u=1;
- //uu=1;
}
} else {
u&=b;
- uu&=bu;
- gte_u&=gte_bu;
- //u=1;
- //uu=1;
+ gte_u&=gte_b;
}
if(i<slen-1) {
branch_unneeded_reg[i]&=unneeded_reg[i+2];
- branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
- //branch_unneeded_reg[i]=1;
- //branch_unneeded_reg_upper[i]=1;
} else {
branch_unneeded_reg[i]=1;
- branch_unneeded_reg_upper[i]=1;
}
}
}
{
// SYSCALL instruction (software interrupt)
u=1;
- uu=1;
}
else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
{
// ERET instruction (return from interrupt)
u=1;
- uu=1;
}
- //u=uu=1; // DEBUG
- tdep=(~uu>>rt1[i])&1;
+ //u=1; // DEBUG
// Written registers are unneeded
u|=1LL<<rt1[i];
u|=1LL<<rt2[i];
- uu|=1LL<<rt1[i];
- uu|=1LL<<rt2[i];
gte_u|=gte_rt[i];
// Accessed registers are needed
u&=~(1LL<<rs1[i]);
u&=~(1LL<<rs2[i]);
- uu&=~(1LL<<us1[i]);
- uu&=~(1LL<<us2[i]);
gte_u&=~gte_rs[i];
if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
// Source-target dependencies
- uu&=~(tdep<<dep1[i]);
- uu&=~(tdep<<dep2[i]);
// R0 is always unneeded
- u|=1;uu|=1;
+ u|=1;
// Save it
unneeded_reg[i]=u;
- unneeded_reg_upper[i]=uu;
gte_unneeded[i]=gte_u;
/*
printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
else printf(" r%d",r);
}
}
- printf(" UU:");
- for(r=1;r<=CCREG;r++) {
- if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
- if(r==HIREG) printf(" HI");
- else if(r==LOREG) printf(" LO");
- else printf(" r%d",r);
- }
- }
- printf("\n");*/
- }
- for (i=iend;i>=istart;i--)
- {
- unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
+ printf("\n");
+ */
}
}
}
for (i=iend;i>=istart;i--)
{
- if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
+ if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
{
if(ba[i]<start || ba[i]>=(start+slen*4))
{
if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
if(i>istart) {
- if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
+ if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP)
{
// Don't store a register immediately after writing it,
// may prevent dual-issue.
}
printf("\n");*/
- //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
+ //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP)) {
regs[i].dirty|=will_dirty_i;
#ifndef DESTRUCTIVE_WRITEBACK
regs[i].dirty&=wont_dirty_i;
- if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
+ if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
{
if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
for(r=0;r<HOST_REGS;r++) {
printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
case SJUMP:
printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
- case FJUMP:
- printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
case RJUMP:
if (opcode[i]==0x9&&rt1[i]!=31)
printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
#define DRC_TEST_VAL 0x74657374
-static int new_dynarec_test(void)
+static void new_dynarec_test(void)
{
- int (*testfunc)(void) = (void *)out;
+ int (*testfunc)(void);
void *beginning;
- int ret;
+ int ret[2];
+ size_t i;
- beginning = start_block();
- emit_movimm(DRC_TEST_VAL,0); // test
- emit_jmpreg(14);
- literal_pool(0);
- end_block(beginning);
- SysPrintf("testing if we can run recompiled code..\n");
- ret = testfunc();
- if (ret == DRC_TEST_VAL)
+ // check structure linkage
+ if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
+ {
+ SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
+ }
+
+ SysPrintf("testing if we can run recompiled code...\n");
+ ((volatile u_int *)out)[0]++; // make cache dirty
+
+ for (i = 0; i < ARRAY_SIZE(ret); i++) {
+ out = translation_cache;
+ beginning = start_block();
+ emit_movimm(DRC_TEST_VAL + i, 0); // test
+ emit_ret();
+ literal_pool(0);
+ end_block(beginning);
+ testfunc = beginning;
+ ret[i] = testfunc();
+ }
+
+ if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
SysPrintf("test passed.\n");
else
- SysPrintf("test failed: %08x\n", ret);
+ SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
out = translation_cache;
- return ret == DRC_TEST_VAL;
}
// clear the state completely, instead of just marking
memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
}
-int new_recompile_block(int addr)
+int new_recompile_block(u_int addr)
{
u_int pagelimit = 0;
u_int state_rflags = 0;
}
start = (u_int)addr&~3;
- //assert(((u_int)addr&1)==0);
+ //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
new_dynarec_did_compile=1;
if (Config.HLE && start == 0x80001000) // hlecall
{
source = get_source_start(start, &pagelimit);
if (source == NULL) {
SysPrintf("Compile at bogus memory address: %08x\n", addr);
- exit(1);
+ abort();
}
/* Pass 1: disassemble */
switch(op2)
{
case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
+ case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break;
case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
- case 0x10: strcpy(insn[i],"tlb"); type=NI;
- switch(source[i]&0x3f)
- {
- case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
- case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
- case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
- case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
- case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
- //case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
- }
+ case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break;
+ case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
}
break;
- case 0x11: strcpy(insn[i],"cop1"); type=NI;
+ case 0x11: strcpy(insn[i],"cop1"); type=COP1;
op2=(source[i]>>21)&0x1f;
- switch(op2)
- {
- case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
- case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
- case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
- case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
- case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
- case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
- case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
- switch((source[i]>>16)&0x3)
- {
- case 0x00: strcpy(insn[i],"BC1F"); break;
- case 0x01: strcpy(insn[i],"BC1T"); break;
- case 0x02: strcpy(insn[i],"BC1FL"); break;
- case 0x03: strcpy(insn[i],"BC1TL"); break;
- }
- break;
- case 0x10: strcpy(insn[i],"C1.S"); type=NI;
- switch(source[i]&0x3f)
- {
- case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
- case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
- case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
- case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
- case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
- case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
- case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
- case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
- case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
- case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
- case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
- case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
- case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
- case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
- case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
- case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
- case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
- case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
- case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
- case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
- case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
- case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
- case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
- case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
- case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
- case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
- case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
- case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
- case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
- case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
- case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
- case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
- case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
- case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
- case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
- }
- break;
- case 0x11: strcpy(insn[i],"C1.D"); type=NI;
- switch(source[i]&0x3f)
- {
- case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
- case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
- case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
- case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
- case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
- case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
- case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
- case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
- case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
- case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
- case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
- case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
- case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
- case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
- case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
- case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
- case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
- case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
- case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
- case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
- case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
- case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
- case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
- case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
- case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
- case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
- case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
- case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
- case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
- case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
- case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
- case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
- case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
- case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
- case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
- }
- break;
- case 0x14: strcpy(insn[i],"C1.W"); type=NI;
- switch(source[i]&0x3f)
- {
- case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
- case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
- }
- break;
- case 0x15: strcpy(insn[i],"C1.L"); type=NI;
- switch(source[i]&0x3f)
- {
- case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
- case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
- }
- break;
- }
break;
#if 0
case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
#endif
case 0x12: strcpy(insn[i],"COP2"); type=NI;
op2=(source[i]>>21)&0x1f;
- //if (op2 & 0x10) {
+ //if (op2 & 0x10)
if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
if (gte_handlers[source[i]&0x3f]!=NULL) {
if (gte_regnames[source[i]&0x3f]!=NULL)
opcode2[i]=op2;
/* Get registers/immediates */
lt1[i]=0;
- us1[i]=0;
- us2[i]=0;
dep1[i]=0;
dep2[i]=0;
gte_rs[i]=gte_rt[i]=0;
rt1[i]=0;
rt2[i]=0;
imm[i]=(short)source[i];
- if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
break;
case LOADLR:
// LWL/LWR only load part of the register,
rt1[i]=(source[i]>>16)&0x1f;
rt2[i]=0;
imm[i]=(short)source[i];
- if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
if(op==0x26) dep1[i]=rt1[i]; // LWR
break;
case IMM16:
}else{
imm[i]=(short)source[i];
}
- if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
- if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
break;
case UJUMP:
if(op&2) { // BGTZ/BLEZ
rs2[i]=0;
}
- us1[i]=rs1[i];
- us2[i]=rs2[i];
likely[i]=op>>4;
break;
case SJUMP:
rs2[i]=CCREG;
rt1[i]=0;
rt2[i]=0;
- us1[i]=rs1[i];
if(op2&0x10) { // BxxAL
rt1[i]=31;
// NOTE: If the branch is not taken, r31 is still overwritten
}
likely[i]=(op2&2)>>1;
break;
- case FJUMP:
- rs1[i]=FSREG;
- rs2[i]=CSREG;
- rt1[i]=0;
- rt2[i]=0;
- likely[i]=((source[i])>>17)&1;
- break;
case ALU:
rs1[i]=(source[i]>>21)&0x1f; // source
rs2[i]=(source[i]>>16)&0x1f; // subtract amount
rt1[i]=(source[i]>>11)&0x1f; // destination
rt2[i]=0;
- if(op2==0x2a||op2==0x2b) { // SLT/SLTU
- us1[i]=rs1[i];us2[i]=rs2[i];
- }
- else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
+ if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
dep1[i]=rs1[i];dep2[i]=rs2[i];
}
else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
rs2[i]=(source[i]>>16)&0x1f; // divisor
rt1[i]=HIREG;
rt2[i]=LOREG;
- if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
- us1[i]=rs1[i];us2[i]=rs2[i];
- }
break;
case MOV:
rs1[i]=0;
rs2[i]=(source[i]>>21)&0x1f; // shift amount
rt1[i]=(source[i]>>11)&0x1f; // destination
rt2[i]=0;
- // DSLLV/DSRLV/DSRAV are 64-bit
- if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
break;
case SHIFTIMM:
rs1[i]=(source[i]>>16)&0x1f;
imm[i]=(source[i]>>6)&0x1f;
// DSxx32 instructions
if(op2>=0x3c) imm[i]|=0x20;
- // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
- if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
break;
case COP0:
rs1[i]=0;
rs2[i]=0;
rt1[i]=0;
rt2[i]=0;
- if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
- if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
+ if(op2==0||op2==2) rt1[i]=(source[i]>>16)&0x1F; // MFC0/CFC0
+ if(op2==4||op2==6) rs1[i]=(source[i]>>16)&0x1F; // MTC0/CTC0
if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
break;
rt2[i]=0;
if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
- if(op2==5) us1[i]=rs1[i]; // DMTC1
rs2[i]=CSREG;
break;
case COP2:
else gte_rs[i]|=3ll<<(v*2);
}
break;
- case FLOAT:
- case FCONV:
- rs1[i]=0;
- rs2[i]=CSREG;
- rt1[i]=0;
- rt2[i]=0;
- break;
- case FCOMP:
- rs1[i]=FSREG;
- rs2[i]=CSREG;
- rt1[i]=FSREG;
- rt2[i]=0;
- break;
case SYSCALL:
case HLECALL:
case INTCALL:
ba[i]=start+i*4+8; // Ignore never taken branch
else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
ba[i]=start+i*4+8; // Ignore never taken branch
- else if(type==CJUMP||type==SJUMP||type==FJUMP)
+ else if(type==CJUMP||type==SJUMP)
ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
else ba[i]=-1;
- if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
+ if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP)) {
int do_in_intrp=0;
// branch in delay slot?
- if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
+ if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP) {
// don't handle first branch and call interpreter if it's hit
SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
do_in_intrp=1;
}
}
slen=i;
- if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
+ if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP) {
if(start+i*4==pagelimit) {
itype[i-1]=SPAN;
}
/* Pass 3 - Register allocation */
struct regstat current; // Current register allocations/status
- current.is32=1;
current.dirty=0;
current.u=unneeded_reg[0];
- current.uu=unneeded_reg_upper[0];
clear_all_regs(current.regmap);
alloc_reg(¤t,0,CCREG);
dirty_reg(¤t,CCREG);
bt[1]=1;
ds=1;
unneeded_reg[0]=1;
- unneeded_reg_upper[0]=1;
current.regmap[HOST_BTREG]=BTREG;
}
current.isconst=0;
current.waswritten=0;
}
- if(i>1)
- {
- if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
- {
- if(rs1[i-2]==0||rs2[i-2]==0)
- {
- if(rs1[i-2]) {
- current.is32|=1LL<<rs1[i-2];
- int hr=get_reg(current.regmap,rs1[i-2]|64);
- if(hr>=0) current.regmap[hr]=-1;
- }
- if(rs2[i-2]) {
- current.is32|=1LL<<rs2[i-2];
- int hr=get_reg(current.regmap,rs2[i-2]|64);
- if(hr>=0) current.regmap[hr]=-1;
- }
- }
- }
- }
- current.is32=-1LL;
memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
regs[i].wasconst=current.isconst;
- regs[i].was32=current.is32;
regs[i].wasdirty=current.dirty;
regs[i].loadedconst=0;
- if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
+ if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP) {
if(i+1<slen) {
current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
- current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
- if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
current.u|=1;
- current.uu|=1;
} else {
current.u=1;
- current.uu=1;
}
} else {
if(i+1<slen) {
current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
- current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
- if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
- current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
current.u|=1;
- current.uu|=1;
- } else { SysPrintf("oops, branch at end of block with no delay slot\n");exit(1); }
+ } else { SysPrintf("oops, branch at end of block with no delay slot\n");abort(); }
}
is_ds[i]=ds;
if(ds) {
// ...but we need to alloc it in case something jumps here
if(i+1<slen) {
current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
- current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
}else{
current.u=branch_unneeded_reg[i-1];
- current.uu=branch_unneeded_reg_upper[i-1];
}
current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
- current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
- if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
current.u|=1;
- current.uu|=1;
struct regstat temp;
memcpy(&temp,¤t,sizeof(current));
temp.wasdirty=temp.dirty;
- temp.was32=temp.is32;
// TODO: Take into account unconditional branches, as below
delayslot_alloc(&temp,i);
memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
regs[i].wasdirty=temp.wasdirty;
- regs[i].was32=temp.was32;
regs[i].dirty=temp.dirty;
- regs[i].is32=temp.is32;
regs[i].isconst=0;
regs[i].wasconst=0;
current.isconst=0;
}
else
{
- if(r<64){
+ assert(r < 64);
if((current.u>>r)&1) {
regs[i].regmap_entry[hr]=-1;
regs[i].regmap[hr]=-1;
//current.regmap[hr]=-1;
}else
regs[i].regmap_entry[hr]=r;
- }
- else {
- if((current.uu>>(r&63))&1) {
- regs[i].regmap_entry[hr]=-1;
- regs[i].regmap[hr]=-1;
- //Don't clear regs in the delay slot as the branch might need them
- //current.regmap[hr]=-1;
- }else
- regs[i].regmap_entry[hr]=r;
- }
}
} else {
// First instruction expects CCREG to be allocated
#ifdef REG_PREFETCH
alloc_reg(¤t,i,PTEMP);
#endif
- //current.is32|=1LL<<rt1[i];
}
ooo[i]=1;
delayslot_alloc(¤t,i+1);
dirty_reg(¤t,CCREG);
if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
- if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
- {
- if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
- if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
- }
if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
(rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
// The delay slot overwrites one of our conditions.
regs[i].wasconst=0;
if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
- if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
- {
- if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
- if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
- }
}
else
{
alloc_cc(¤t,i);
dirty_reg(¤t,CCREG);
alloc_reg(¤t,i,rs1[i]);
- if(!(current.is32>>rs1[i]&1))
- {
- alloc_reg64(¤t,i,rs1[i]);
- }
if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
// The delay slot overwrites one of our conditions.
// Allocate the branch condition registers instead.
current.wasconst=0;
regs[i].wasconst=0;
if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
- if(!((current.is32>>rs1[i])&1))
- {
- if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
- }
}
else
{
dirty_reg(¤t,CCREG);
alloc_reg(¤t,i,rs1[i]);
alloc_reg(¤t,i,rs2[i]);
- if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
- {
- alloc_reg64(¤t,i,rs1[i]);
- alloc_reg64(¤t,i,rs2[i]);
- }
}
else
if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
alloc_cc(¤t,i);
dirty_reg(¤t,CCREG);
alloc_reg(¤t,i,rs1[i]);
- if(!(current.is32>>rs1[i]&1))
- {
- alloc_reg64(¤t,i,rs1[i]);
- }
}
ds=1;
//current.isconst=0;
alloc_cc(¤t,i);
dirty_reg(¤t,CCREG);
alloc_reg(¤t,i,rs1[i]);
- if(!(current.is32>>rs1[i]&1))
- {
- alloc_reg64(¤t,i,rs1[i]);
- }
if (rt1[i]==31) { // BLTZAL/BGEZAL
alloc_reg(¤t,i,31);
dirty_reg(¤t,31);
//#ifdef REG_PREFETCH
//alloc_reg(¤t,i,PTEMP);
//#endif
- //current.is32|=1LL<<rt1[i];
}
if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
current.wasconst=0;
regs[i].wasconst=0;
if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
- if(!((current.is32>>rs1[i])&1))
- {
- if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
- }
}
else
{
alloc_cc(¤t,i);
dirty_reg(¤t,CCREG);
alloc_reg(¤t,i,rs1[i]);
- if(!(current.is32>>rs1[i]&1))
- {
- alloc_reg64(¤t,i,rs1[i]);
- }
}
ds=1;
//current.isconst=0;
break;
- case FJUMP:
- current.isconst=0;
- current.wasconst=0;
- regs[i].wasconst=0;
- if(likely[i]==0) // BC1F/BC1T
- {
- // TODO: Theoretically we can run out of registers here on x86.
- // The delay slot can allocate up to six, and we need to check
- // CSREG before executing the delay slot. Possibly we can drop
- // the cycle count and then reload it after checking that the
- // FPU is in a usable state, or don't do out-of-order execution.
- alloc_cc(¤t,i);
- dirty_reg(¤t,CCREG);
- alloc_reg(¤t,i,FSREG);
- alloc_reg(¤t,i,CSREG);
- if(itype[i+1]==FCOMP) {
- // The delay slot overwrites the branch condition.
- // Allocate the branch condition registers instead.
- alloc_cc(¤t,i);
- dirty_reg(¤t,CCREG);
- alloc_reg(¤t,i,CSREG);
- alloc_reg(¤t,i,FSREG);
- }
- else {
- ooo[i]=1;
- delayslot_alloc(¤t,i+1);
- alloc_reg(¤t,i+1,CSREG);
- }
- }
- else
- // Don't alloc the delay slot yet because we might not execute it
- if(likely[i]) // BC1FL/BC1TL
- {
- alloc_cc(¤t,i);
- dirty_reg(¤t,CCREG);
- alloc_reg(¤t,i,CSREG);
- alloc_reg(¤t,i,FSREG);
- }
- ds=1;
- current.isconst=0;
- break;
case IMM16:
imm16_alloc(¤t,i);
break;
break;
case COP1:
case COP2:
- cop1_alloc(¤t,i);
+ cop12_alloc(¤t,i);
break;
case C1LS:
c1ls_alloc(¤t,i);
case C2OP:
c2op_alloc(¤t,i);
break;
- case FCONV:
- fconv_alloc(¤t,i);
- break;
- case FLOAT:
- float_alloc(¤t,i);
- break;
- case FCOMP:
- fcomp_alloc(¤t,i);
- break;
case SYSCALL:
case HLECALL:
case INTCALL:
break;
}
- // Drop the upper half of registers that have become 32-bit
- current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
- if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
- current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
- if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
- current.uu|=1;
- } else {
- current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
- current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
- if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
- current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
- current.uu|=1;
- }
-
// Create entry (branch target) regmap
for(hr=0;hr<HOST_REGS;hr++)
{
regs[i].regmap_entry[hr]=0;
}
else
- if(r<64){
+ {
+ assert(r<64);
if((current.u>>r)&1) {
regs[i].regmap_entry[hr]=-1;
//regs[i].regmap[hr]=-1;
}else
regs[i].regmap_entry[hr]=r;
}
- else {
- if((current.uu>>(r&63))&1) {
- regs[i].regmap_entry[hr]=-1;
- //regs[i].regmap[hr]=-1;
- current.regmap[hr]=-1;
- }else
- regs[i].regmap_entry[hr]=r;
- }
}
} else {
// Branches expect CCREG to be allocated at the target
/* Branch post-alloc */
if(i>0)
{
- current.was32=current.is32;
current.wasdirty=current.dirty;
switch(itype[i-1]) {
case UJUMP:
branch_regs[i-1].isconst=0;
branch_regs[i-1].wasconst=0;
branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
- branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
alloc_cc(&branch_regs[i-1],i-1);
dirty_reg(&branch_regs[i-1],CCREG);
if(rt1[i-1]==31) { // JAL
alloc_reg(&branch_regs[i-1],i-1,31);
dirty_reg(&branch_regs[i-1],31);
- branch_regs[i-1].is32|=1LL<<31;
}
memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
branch_regs[i-1].isconst=0;
branch_regs[i-1].wasconst=0;
branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
- branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
alloc_cc(&branch_regs[i-1],i-1);
dirty_reg(&branch_regs[i-1],CCREG);
alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
if(rt1[i-1]!=0) { // JALR
alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
dirty_reg(&branch_regs[i-1],rt1[i-1]);
- branch_regs[i-1].is32|=1LL<<rt1[i-1];
}
#ifdef USE_MINI_HT
if(rs1[i-1]==31) { // JALR
// The delay slot overwrote one of our conditions
// Delay slot goes after the test (in order)
current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
- current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
- if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
current.u|=1;
- current.uu|=1;
delayslot_alloc(¤t,i);
current.isconst=0;
}
else
{
current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
- current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
// Alloc the branch condition registers
if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
- if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
- {
- if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
- if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
- }
}
memcpy(&branch_regs[i-1],¤t,sizeof(current));
branch_regs[i-1].isconst=0;
// The delay slot overwrote the branch condition
// Delay slot goes after the test (in order)
current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
- current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
- if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
current.u|=1;
- current.uu|=1;
delayslot_alloc(¤t,i);
current.isconst=0;
}
else
{
current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
- current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
// Alloc the branch condition register
alloc_reg(¤t,i-1,rs1[i-1]);
- if(!(current.is32>>rs1[i-1]&1))
- {
- alloc_reg64(¤t,i-1,rs1[i-1]);
- }
}
memcpy(&branch_regs[i-1],¤t,sizeof(current));
branch_regs[i-1].isconst=0;
{
memcpy(&branch_regs[i-1],¤t,sizeof(current));
branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
- branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
- if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
alloc_cc(&branch_regs[i-1],i);
dirty_reg(&branch_regs[i-1],CCREG);
delayslot_alloc(&branch_regs[i-1],i);
{
memcpy(&branch_regs[i-1],¤t,sizeof(current));
branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
- branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
- if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
alloc_cc(&branch_regs[i-1],i);
dirty_reg(&branch_regs[i-1],CCREG);
delayslot_alloc(&branch_regs[i-1],i);
// The delay slot overwrote the branch condition
// Delay slot goes after the test (in order)
current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
- current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
- if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
current.u|=1;
- current.uu|=1;
delayslot_alloc(¤t,i);
current.isconst=0;
}
else
{
current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
- current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
// Alloc the branch condition register
alloc_reg(¤t,i-1,rs1[i-1]);
- if(!(current.is32>>rs1[i-1]&1))
- {
- alloc_reg64(¤t,i-1,rs1[i-1]);
- }
}
memcpy(&branch_regs[i-1],¤t,sizeof(current));
branch_regs[i-1].isconst=0;
{
memcpy(&branch_regs[i-1],¤t,sizeof(current));
branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
- branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
- if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
alloc_cc(&branch_regs[i-1],i);
dirty_reg(&branch_regs[i-1],CCREG);
delayslot_alloc(&branch_regs[i-1],i);
if(opcode2[i-1]&0x10) { // BxxZAL
alloc_reg(&branch_regs[i-1],i-1,31);
dirty_reg(&branch_regs[i-1],31);
- branch_regs[i-1].is32|=1LL<<31;
- }
- break;
- case FJUMP:
- if(likely[i-1]==0) // BC1F/BC1T
- {
- alloc_cc(¤t,i-1);
- dirty_reg(¤t,CCREG);
- if(itype[i]==FCOMP) {
- // The delay slot overwrote the branch condition
- // Delay slot goes after the test (in order)
- delayslot_alloc(¤t,i);
- current.isconst=0;
- }
- else
- {
- current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
- current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
- // Alloc the branch condition register
- alloc_reg(¤t,i-1,FSREG);
- }
- memcpy(&branch_regs[i-1],¤t,sizeof(current));
- memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
- }
- else // BC1FL/BC1TL
- {
- // Alloc the delay slot in case the branch is taken
- memcpy(&branch_regs[i-1],¤t,sizeof(current));
- branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
- branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
- if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
- alloc_cc(&branch_regs[i-1],i);
- dirty_reg(&branch_regs[i-1],CCREG);
- delayslot_alloc(&branch_regs[i-1],i);
- branch_regs[i-1].isconst=0;
- alloc_reg(¤t,i,CCREG); // Not taken path
- dirty_reg(¤t,CCREG);
- memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
}
break;
}
if(rt1[i-1]==31) // JAL/JALR
{
// Subroutine call will return here, don't alloc any registers
- current.is32=1;
current.dirty=0;
clear_all_regs(current.regmap);
alloc_reg(¤t,i,CCREG);
else if(i+1<slen)
{
// Internal branch will jump here, match registers to caller
- current.is32=0x3FFFFFFFFLL;
current.dirty=0;
clear_all_regs(current.regmap);
alloc_reg(¤t,i,CCREG);
{
if(ba[j]==start+i*4+4) {
memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
- current.is32=branch_regs[j].is32;
current.dirty=branch_regs[j].dirty;
break;
}
if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
current.regmap[hr]=-1;
}
- current.is32&=branch_regs[j].is32;
current.dirty&=branch_regs[j].dirty;
}
}
// Count cycles in between branches
ccadj[i]=cc;
- if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
+ if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
{
cc=0;
}
cc++;
}
- flush_dirty_uppers(¤t);
if(!is_ds[i]) {
- regs[i].is32=current.is32;
regs[i].dirty=current.dirty;
regs[i].isconst=current.isconst;
memcpy(constmap[i],current_constmap,sizeof(current_constmap));
for (i=slen-1;i>=0;i--)
{
int hr;
- if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
+ if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
{
if(ba[i]<start || ba[i]>=(start+slen*4))
{
if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
}
- if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
- if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
- if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
- if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
- if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
- if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
- if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
- }
- if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
- if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
- if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
- }
if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
// Source registers are needed
- if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
- if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
- if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
- if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
- if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
- if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
- if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
- }
- if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
- if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
- if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
- }
if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
// But do so if this is a branch target, otherwise we
// might have to load the register before the branch.
if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
- if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
- (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
+ if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
}
- if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
- (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
+ if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
}
}
}
// Cycle count is needed at branches. Assume it is needed at the target too.
- if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
+ if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==SPAN) {
if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
}
}
}
}
- if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
+ if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
{
- int d1=0,d2=0,map=0,temp=0;
- if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
- {
- d1=dep1[i+1];
- d2=dep2[i+1];
- }
+ int map=0,temp=0;
if(itype[i+1]==STORE || itype[i+1]==STORELR ||
(opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
map=INVCP;
if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
(regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
(regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
- (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
- (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
(regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
(branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
(branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
- (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
- (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
(branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
// Non-branch
if(i>0)
{
- int d1=0,d2=0,map=-1,temp=-1;
- if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
- {
- d1=dep1[i];
- d2=dep2[i];
- }
+ int map=-1,temp=-1;
if(itype[i]==STORE || itype[i]==STORELR ||
(opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
map=INVCP;
itype[i]==C1LS || itype[i]==C2LS)
temp=FTEMP;
if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
- (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
- (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
(regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
(itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
{
if(i<slen-1&&!is_ds[i]) {
- if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
+ assert(regs[i].regmap[hr]<64);
+ if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
- if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
{
SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
}
}
}
- }
- }
+ } // if needed
+ } // for hr
}
/* Pass 5 - Pre-allocate registers */
clear_all_regs(f_regmap);
for(i=0;i<slen-1;i++)
{
- if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
+ if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
{
if(ba[i]>=start && ba[i]<(start+i*4))
if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
- ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
- ||itype[i+1]==FCOMP||itype[i+1]==FCONV
+ ||itype[i+1]==SHIFT||itype[i+1]==COP1
||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
{
int t=(ba[i]-start)>>2;
- if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
+ if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP)) // loop_preload can't handle jumps into delay slots
if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
for(hr=0;hr<HOST_REGS;hr++)
{
- if(regs[i].regmap[hr]>64) {
- if(!((regs[i].dirty>>hr)&1))
- f_regmap[hr]=regs[i].regmap[hr];
- else f_regmap[hr]=-1;
- }
- else if(regs[i].regmap[hr]>=0) {
+ if(regs[i].regmap[hr]>=0) {
if(f_regmap[hr]!=regs[i].regmap[hr]) {
// dealloc old register
int n;
f_regmap[hr]=regs[i].regmap[hr];
}
}
- if(branch_regs[i].regmap[hr]>64) {
- if(!((branch_regs[i].dirty>>hr)&1))
- f_regmap[hr]=branch_regs[i].regmap[hr];
- else f_regmap[hr]=-1;
- }
- else if(branch_regs[i].regmap[hr]>=0) {
+ if(branch_regs[i].regmap[hr]>=0) {
if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
// dealloc old register
int n;
{
//printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
if(r<34&&((unneeded_reg[j]>>r)&1)) break;
- if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
- if(r>63) {
- // NB This can exclude the case where the upper-half
- // register is lower numbered than the lower-half
- // register. Not sure if it's worth fixing...
- if(get_reg(regs[j].regmap,r&63)<0) break;
- if(get_reg(regs[j].regmap_entry,r&63)<0) break;
- if(regs[j].is32&(1LL<<(r&63))) break;
- }
+ assert(r < 64);
if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
//printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
int k;
//printf("no-match due to different register\n");
break;
}
- if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
+ if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP) {
//printf("no-match due to branch\n");
break;
}
if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
break;
}
- if(r>63) {
- // NB This can exclude the case where the upper-half
- // register is lower numbered than the lower-half
- // register. Not sure if it's worth fixing...
- if(get_reg(regs[k-1].regmap,r&63)<0) break;
- if(regs[k-1].is32&(1LL<<(r&63))) break;
- }
+ assert(r < 64);
k--;
}
- if(i<slen-1) {
- if((regs[k].is32&(1LL<<f_regmap[hr]))!=
- (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
- //printf("bad match after branch\n");
- break;
- }
- }
if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
//printf("Extend r%d, %x ->\n",hr,start+k*4);
while(k<i) {
regmap_pre[i+2][hr]=f_regmap[hr];
regs[i+2].wasdirty&=~(1<<hr);
regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
- assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
- (regs[i+2].was32&(1LL<<f_regmap[hr])));
}
}
}
regs[k].dirty&=~(1<<hr);
regs[k].wasconst&=~(1<<hr);
regs[k].isconst&=~(1<<hr);
- if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
+ if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP) {
branch_regs[k].regmap_entry[hr]=f_regmap[hr];
branch_regs[k].regmap[hr]=f_regmap[hr];
branch_regs[k].dirty&=~(1<<hr);
if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
regmap_pre[k+2][hr]=f_regmap[hr];
regs[k+2].wasdirty&=~(1<<hr);
- assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
- (regs[k+2].was32&(1LL<<f_regmap[hr])));
}
}
else
//printf("no-match due to different register\n");
break;
}
- if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
- //printf("32/64 mismatch %x %d\n",start+j*4,hr);
- break;
- }
if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
{
// Stop on unconditional branch
break;
}
- if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
+ if(itype[j]==CJUMP||itype[j]==SJUMP)
{
if(ooo[j]) {
if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
//printf("No free regs for store %x\n",start+j*4);
break;
}
- if(f_regmap[hr]>=64) {
- if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
- break;
- }
- else
- {
- if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
- break;
- }
- }
- }
+ assert(f_regmap[hr]<64);
}
}
}
for(hr=0;hr<HOST_REGS;hr++)
{
if(hr!=EXCLUDE_REG) {
- if(regs[i].regmap[hr]>64) {
- if(!((regs[i].dirty>>hr)&1))
- f_regmap[hr]=regs[i].regmap[hr];
- }
- else if(regs[i].regmap[hr]>=0) {
+ if(regs[i].regmap[hr]>=0) {
if(f_regmap[hr]!=regs[i].regmap[hr]) {
// dealloc old register
int n;
}
if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
- itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
- itype[i]!=FCONV&&itype[i]!=FCOMP)
+ itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1)
{
memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
}
// to use, which can avoid a load-use penalty on certain CPUs.
for(i=0;i<slen-1;i++)
{
- if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
+ if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP))
{
if(!bt[i+1])
{
/* Pass 7 - Identify 32-bit registers */
for (i=slen-1;i>=0;i--)
{
- if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
+ if(itype[i]==CJUMP||itype[i]==SJUMP)
{
// Conditional branch
if((source[i]>>16)!=0x1000&&i<slen-2) {
#ifdef __arm__
printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
#endif
+ #if defined(__i386__) || defined(__x86_64__)
printf("needs: ");
if(needed_reg[i]&1) printf("eax ");
if((needed_reg[i]>>1)&1) printf("ecx ");
if((needed_reg[i]>>6)&1) printf("esi ");
if((needed_reg[i]>>7)&1) printf("edi ");
printf("\n");
- #if defined(__i386__) || defined(__x86_64__)
printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
printf("dirty: ");
if(regs[i].wasdirty&1) printf("eax ");
if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
#endif
- #ifdef __arm__
+ #if defined(__arm__) || defined(__aarch64__)
int r;
for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
if ((regs[i].isconst >> r) & 1)
#endif
printf("\n");
}
- if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
+ if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
#if defined(__i386__) || defined(__x86_64__)
printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
if(branch_regs[i].dirty&1) printf("eax ");
/* Pass 8 - Assembly */
linkcount=0;stubcount=0;
ds=0;is_delayslot=0;
- cop1_usable=0;
- uint64_t is32_pre=0;
u_int dirty_pre=0;
void *beginning=start_block();
if((u_int)addr&1) {
void *instr_addr0_override = NULL;
if (start == 0x80030000) {
- // nasty hack for fastbios thing
+ // nasty hack for the fastbios thing
// override block entry to this code
instr_addr0_override = out;
emit_movimm(start,0);
emit_writeword(0,&pcaddr);
emit_writeword(0,&address);
emit_cmp(0,1);
+ #ifdef __aarch64__
+ emit_jeq(out + 4*2);
+ emit_jmp(new_dyna_leave);
+ #else
emit_jne(new_dyna_leave);
+ #endif
}
for(i=0;i<slen;i++)
{
#ifndef DESTRUCTIVE_WRITEBACK
if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
{
- wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
- unneeded_reg[i],unneeded_reg_upper[i]);
+ wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
}
- if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
- is32_pre=branch_regs[i].is32;
+ if((itype[i]==CJUMP||itype[i]==SJUMP)&&!likely[i]) {
dirty_pre=branch_regs[i].dirty;
}else{
- is32_pre=regs[i].is32;
dirty_pre=regs[i].dirty;
}
#endif
// write back
if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
{
- wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
- unneeded_reg[i],unneeded_reg_upper[i]);
+ wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
loop_preload(regmap_pre[i],regs[i].regmap_entry);
}
// branch target entry point
// load regs
if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
- wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
- load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
+ wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
+ load_regs(regs[i].regmap_entry,regs[i].regmap,rs1[i],rs2[i]);
address_generation(i,®s[i],regs[i].regmap_entry);
- load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
- if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
+ load_consts(regmap_pre[i],regs[i].regmap,i);
+ if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
{
// Load the delay slot registers if necessary
if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
- load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
+ load_regs(regs[i].regmap_entry,regs[i].regmap,rs1[i+1],rs1[i+1]);
if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
- load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
+ load_regs(regs[i].regmap_entry,regs[i].regmap,rs2[i+1],rs2[i+1]);
if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
- load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
+ load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
}
else if(i+1<slen)
{
// Preload registers for following instruction
if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
- load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
+ load_regs(regs[i].regmap_entry,regs[i].regmap,rs1[i+1],rs1[i+1]);
if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
- load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
+ load_regs(regs[i].regmap_entry,regs[i].regmap,rs2[i+1],rs2[i+1]);
}
// TODO: if(is_ooo(i)) address_generation(i+1);
- if(itype[i]==CJUMP||itype[i]==FJUMP)
- load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
+ if(itype[i]==CJUMP)
+ load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
- load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
- if(bt[i]) cop1_usable=0;
+ load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
// assemble
switch(itype[i]) {
case ALU:
c2ls_assemble(i,®s[i]);break;
case C2OP:
c2op_assemble(i,®s[i]);break;
- case FCONV:
- fconv_assemble(i,®s[i]);break;
- case FLOAT:
- float_assemble(i,®s[i]);break;
- case FCOMP:
- fcomp_assemble(i,®s[i]);break;
case MULTDIV:
multdiv_assemble(i,®s[i]);break;
case MOV:
cjump_assemble(i,®s[i]);ds=1;break;
case SJUMP:
sjump_assemble(i,®s[i]);ds=1;break;
- case FJUMP:
- fjump_assemble(i,®s[i]);ds=1;break;
case SPAN:
pagespan_assemble(i,®s[i]);break;
}
// add a jump to the next instruction.
if(i>1) {
if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
- assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
+ assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP);
assert(i==slen);
- if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
- store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
+ if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP) {
+ store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
emit_loadreg(CCREG,HOST_CCREG);
emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
}
else if(!likely[i-2])
{
- store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
+ store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
}
else
{
- store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
+ store_regs_bt(regs[i-2].regmap,regs[i-2].dirty,start+i*4);
assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
}
add_to_linker(out,start+i*4,0);
else
{
assert(i>0);
- assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
- store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
+ assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP);
+ store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
emit_loadreg(CCREG,HOST_CCREG);
emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
break;
case 3:
// Clear jump_out
- #ifdef __arm__
+ #if defined(__arm__) || defined(__aarch64__)
if((expirep&2047)==0)
do_clear_cache();
#endif
notaz.gp2x.de / pcsx_rearmed.git / blobdiff