{
#ifdef FORCE32
return get_addr(vaddr);
-#endif
+#else
//printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
EntryHi=BadVAddr&0xFFFFE000;
return get_addr_ht(0x80000000);
+#endif
}
void clear_all_regs(signed char regmap[])
if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
get_bounds((int)head->addr,&start,&end);
//printf("start: %x end: %x\n",start,end);
- if(page<2048&&start>=0x80000000&&end<0x80800000) {
+ if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
u_int i;
u_int inv=0;
get_bounds((int)head->addr,&start,&end);
- if(start-(u_int)rdram<0x800000) {
+ if(start-(u_int)rdram<RAM_SIZE) {
for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
inv|=invalid_code[i];
}
//printf("addr=%x start=%x end=%x\n",addr,start,end);
if(addr<start||addr>=end) inv=1;
}
- else if((signed int)head->vaddr>=(signed int)0x80800000) {
+ else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
inv=1;
}
if(!inv) {
if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
if(s>=0) {
c=(i_regs->wasconst>>s)&1;
- memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
+ memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
}
//printf("load_assemble: c=%d\n",c);
//if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
// FIXME: Even if the load is a NOP, we should check for pagefaults...
#ifdef PCSX
- if(tl<0) {
- if(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80) {
+ if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
+ ||rt1[i]==0) {
// could be FIFO, must perform the read
+ // ||dummy read
assem_debug("(forced read)\n");
tl=get_reg(i_regs->regmap,-1);
assert(tl>=0);
- }
}
+#endif
if(offset||s<0||c) addr=tl;
else addr=s;
-#endif
if(tl>=0) {
//assert(tl>=0);
//assert(rt1[i]);
//#define R29_HACK 1
#ifdef R29_HACK
// Strmnnrmn's speed hack
- if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
+ if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
#endif
{
- emit_cmpimm(addr,0x800000);
+ emit_cmpimm(addr,RAM_SIZE);
jaddr=(int)out;
#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
// Hint to branch predictor that the branch is unlikely to be taken
offset=imm[i];
if(s>=0) {
c=(i_regs->wasconst>>s)&1;
- memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
+ memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
}
assert(tl>=0);
#ifdef R29_HACK
// Strmnnrmn's speed hack
memtarget=1;
- if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
+ if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
#endif
- emit_cmpimm(addr,0x800000);
+ emit_cmpimm(addr,RAM_SIZE);
#ifdef DESTRUCTIVE_SHIFT
if(s==addr) emit_mov(s,temp);
#endif
#ifdef R29_HACK
- if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
+ if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
#endif
{
jaddr=(int)out;
offset=imm[i];
if(s>=0) {
c=(i_regs->isconst>>s)&1;
- memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
+ memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
}
assert(tl>=0);
assert(temp>=0);
if(!using_tlb) {
if(!c) {
- emit_cmpimm(s<0||offset?temp:s,0x800000);
+ emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
if(!offset&&s!=temp) emit_mov(s,temp);
jaddr=(int)out;
emit_jno(0);
// Generate address + offset
if(!using_tlb) {
if(!c)
- emit_cmpimm(offset||c||s<0?ar:s,0x800000);
+ emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
}
else
{
jaddr2=(int)out;
emit_jno(0);
}
- else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
+ else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
jaddr2=(int)out;
emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
}
int s,tl;
int ar;
int offset;
- int c=0;
+ int memtarget=0,c=0;
int jaddr,jaddr2=0,jaddr3,type;
int agr=AGEN1+(i&1);
u_int hr,reglist=0;
} else { // LWC2
ar=tl;
}
+ if(s>=0) c=(i_regs->wasconst>>s)&1;
+ memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
if (!offset&&!c&&s>=0) ar=s;
assert(ar>=0);
if (opcode[i]==0x3a) { // SWC2
cop2_get_dreg(copr,tl,HOST_TEMPREG);
+ type=STOREW_STUB;
}
- if(s>=0) c=(i_regs->wasconst>>s)&1;
- if(!c) {
- emit_cmpimm(offset||c||s<0?ar:s,0x800000);
- jaddr2=(int)out;
- emit_jno(0);
- }
- else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
- jaddr2=(int)out;
- emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
- }
- if (opcode[i]==0x32) { // LWC2
- #ifdef HOST_IMM_ADDR32
- if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
- else
- #endif
- emit_readword_indexed(0,ar,tl);
+ else
type=LOADW_STUB;
+
+ if(c&&!memtarget) {
+ jaddr2=(int)out;
+ emit_jmp(0); // inline_readstub/inline_writestub?
}
- if (opcode[i]==0x3a) { // SWC2
-#ifdef DESTRUCTIVE_SHIFT
- if(!offset&&!c&&s>=0) emit_mov(s,ar);
-#endif
- emit_writeword_indexed(tl,0,ar);
- type=STOREW_STUB;
+ else {
+ if(!c) {
+ emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
+ jaddr2=(int)out;
+ emit_jno(0);
+ }
+ if (opcode[i]==0x32) { // LWC2
+ #ifdef HOST_IMM_ADDR32
+ if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
+ else
+ #endif
+ emit_readword_indexed(0,ar,tl);
+ }
+ if (opcode[i]==0x3a) { // SWC2
+ #ifdef DESTRUCTIVE_SHIFT
+ if(!offset&&!c&&s>=0) emit_mov(s,ar);
+ #endif
+ emit_writeword_indexed(tl,0,ar);
+ }
}
if(jaddr2)
add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
{
//if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
//if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
- assert(rt1[i]>0);
+ //assert(rt1[i]>0);
if(rt1[i]) {
signed char sh,sl,th,tl;
th=get_reg(i_regs->regmap,rt1[i]|64);
if(itype[i]==C1LS||itype[i]==C2LS) {
if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
ra=get_reg(i_regs->regmap,FTEMP);
- else { // SWC1/SDC1
+ else { // SWC1/SDC1/SWC2/SDC2
ra=get_reg(i_regs->regmap,agr);
if(ra<0) ra=get_reg(i_regs->regmap,-1);
}
// Stores to memory go thru the mapper to detect self-modifying
// code, loads don't.
if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
- (unsigned int)(constmap[i][rs]+offset)<0x80800000 )
+ (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
generate_map_const(constmap[i][rs]+offset,rm);
}else{
if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
// Stores to memory go thru the mapper to detect self-modifying
// code, loads don't.
if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
- (unsigned int)(constmap[i+1][rs]+offset)<0x80800000 )
+ (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
generate_map_const(constmap[i+1][rs]+offset,ra);
}else{
if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
#endif
//if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
- assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
+ //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
if(ooo)
if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))
// First test branch condition, then execute delay slot, then branch
ooo=0;
}
- // TODO: Conditional branches w/link must execute in-order so that
- // condition test and write to r31 occur before cycle count test
+ assert(opcode2[i]<0x10||ooo); // FIXME (BxxZALL)
if(ooo) {
s1l=get_reg(branch_regs[i].regmap,rs1[i]);
if(!only32)
{
assert(s1h>=0);
- if(opcode2[i]==0) // BLTZ
+ if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
{
emit_test(s1h,s1h);
if(invert){
emit_js(0);
}
}
- if(opcode2[i]==1) // BGEZ
+ if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
{
emit_test(s1h,s1h);
if(invert){
else
{
assert(s1l>=0);
- if(opcode2[i]==0) // BLTZ
+ if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
{
emit_test(s1l,s1l);
if(invert){
emit_js(0);
}
}
- if(opcode2[i]==1) // BGEZ
+ if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
{
emit_test(s1l,s1l);
if(invert){
{
uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
}
- if(start>0x80000400&&start<0x80800000) {
+ if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
if(itype[i]==UJUMP&&rt1[i]==31)
{
//uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
case FJUMP:
printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
case RJUMP:
- if (rt1[i]!=31)
+ if (opcode[i]==0x9&&rt1[i]!=31)
printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
else
printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
start = (u_int)addr&~3;
//assert(((u_int)addr&1)==0);
#ifdef PCSX
- if (Config.HLE && start == 0x80001000) {
+ if (Config.HLE && start == 0x80001000) // hlecall
+ {
// XXX: is this enough? Maybe check hleSoftCall?
u_int beginning=(u_int)out;
u_int page=get_page(start);
- ll_add(jump_in+page,start,out);
invalid_code[start>>12]=0;
emit_movimm(start,0);
emit_writeword(0,(int)&pcaddr);
#ifdef __arm__
__clear_cache((void *)beginning,out);
#endif
+ ll_add(jump_in+page,start,(void *)beginning);
return 0;
}
- else if ((u_int)addr < 0x00200000) {
+ else if ((u_int)addr < 0x00200000 ||
+ (0xa0000000 <= addr && addr < 0xa0200000)) {
// used for BIOS calls mostly?
- source = (u_int *)((u_int)rdram+start-0);
- pagelimit = 0x00200000;
+ source = (u_int *)((u_int)rdram+(start&0x1fffff));
+ pagelimit = (addr&0xa0000000)|0x00200000;
+ }
+ else if (!Config.HLE && (
+/* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
+ (0xbfc00000 <= addr && addr < 0xbfc80000))) {
+ // BIOS
+ source = (u_int *)((u_int)psxR+(start&0x7ffff));
+ pagelimit = (addr&0xfff00000)|0x80000;
}
else
#endif
}
else
#endif
- if ((int)addr >= 0x80000000 && (int)addr < 0x80800000) {
+ if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
source = (u_int *)((u_int)rdram+start-0x80000000);
- pagelimit = 0x80800000;
+ pagelimit = 0x80000000+RAM_SIZE;
}
#ifndef DISABLE_TLB
else if ((signed int)addr >= (signed int)0xC0000000) {
else {
assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
//assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
- return 1; // Caller will invoke exception handler
+ return -1; // Caller will invoke exception handler
}
//printf("source= %x\n",(int)source);
}
case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
+#ifdef PCSX
+ case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
+#else
case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
+#endif
}
}
break;
case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
+#ifndef FORCE32
case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
+#endif
case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
+#ifndef FORCE32
case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
+#endif
case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
case 0x30: strcpy(insn[i],"LL"); type=NI; break;
case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
+#ifndef FORCE32
case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
+#endif
case 0x38: strcpy(insn[i],"SC"); type=NI; break;
case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
+#ifndef FORCE32
case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
+#endif
#ifdef PCSX
case 0x12: strcpy(insn[i],"COP2"); type=NI;
op2=(source[i]>>21)&0x1f;
case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
#endif
default: strcpy(insn[i],"???"); type=NI;
- printf("NI %08x @%08x\n", source[i], addr + i*4);
+ printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
break;
}
itype[i]=type;
// Don't get too close to the limit
if(i>MAXBLOCK/2) done=1;
}
- if(i>0&&itype[i-1]==SYSCALL&&stop_after_jal) done=1;
- if(itype[i-1]==HLECALL) done=1;
- assert(i<MAXBLOCK-1);
+ if(itype[i]==SYSCALL&&stop_after_jal) done=1;
+ if(itype[i]==HLECALL) done=1;
+ //assert(i<MAXBLOCK-1);
if(start+i*4==pagelimit-4) done=1;
assert(start+i*4<pagelimit);
if (i==MAXBLOCK-1) done=1;
ds=1;
pagespan_ds();
}
+ u_int instr_addr0_override=0;
+
+#ifdef PCSX
+ if (start == 0x80030000) {
+ // nasty hack for fastbios thing
+ instr_addr0_override=(u_int)out;
+ emit_movimm(start,0);
+ emit_readword((int)&pcaddr,1);
+ emit_writeword(0,(int)&pcaddr);
+ emit_cmp(0,1);
+ emit_jne((int)new_dyna_leave);
+ }
+#endif
for(i=0;i<slen;i++)
{
//if(ds) printf("ds: ");
}
}
+ if (instr_addr0_override)
+ instr_addr[0] = instr_addr0_override;
+
/* Pass 9 - Linker */
for(i=0;i<linkcount;i++)
{
notaz.gp2x.de / pcsx_rearmed.git / blobdiff