*/
#include <stdio.h>
-#include <sys/mman.h>
#include "../psxhw.h"
#include "../cdrom.h"
#include "../mdec.h"
+#include "../gpu.h"
+#include "../psxmem_map.h"
#include "emu_if.h"
#include "pcsxmem.h"
+#ifdef __thumb__
+#error the dynarec is incompatible with Thumb functions,
+#error please add -marm to compile flags
+#endif
+
//#define memprintf printf
#define memprintf(...)
-static u8 unmapped_mem[0x1000];
+static u32 *mem_readtab;
+static u32 *mem_writetab;
+static u32 mem_iortab[(1+2+4) * 0x1000 / 4];
+static u32 mem_iowtab[(1+2+4) * 0x1000 / 4];
+static u32 mem_ffwtab[(1+2+4) * 0x1000 / 4];
+//static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4];
+static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4];
+
+// When this is called in a loop, and 'h' is a function pointer, clang will crash.
+#ifdef __clang__
+static __attribute__ ((noinline)) void map_item(u32 *out, const void *h, u32 flag)
+#else
+static void map_item(u32 *out, const void *h, u32 flag)
+#endif
+{
+ u32 hv = (u32)h;
+ if (hv & 1) {
+ SysPrintf("FATAL: %p has LSB set\n", h);
+ abort();
+ }
+ *out = (hv >> 1) | (flag << 31);
+}
+
+// size must be power of 2, at least 4k
+#define map_l1_mem(tab, i, addr, size, base) \
+ map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0)
+
+#define IOMEM32(a) (((a) & 0xfff) / 4)
+#define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
+#define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
+
+u8 zero_mem[0x1000];
u32 read_mem_dummy()
{
sioWrite8((unsigned char)(value >> 24));
}
+#ifndef DRC_DBG
+
+static void map_rcnt_rcount0(u32 mode)
+{
+ if (mode & 0x100) { // pixel clock
+ map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
+ map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
+ }
+ else {
+ map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
+ map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
+ }
+}
+
+static void map_rcnt_rcount1(u32 mode)
+{
+ if (mode & 0x100) { // hcnt
+ map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
+ map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
+ }
+ else {
+ map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
+ map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
+ }
+}
+
+static void map_rcnt_rcount2(u32 mode)
+{
+ if (mode & 0x01) { // gate
+ map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
+ map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
+ }
+ else if (mode & 0x200) { // clk/8
+ map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
+ map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
+ }
+ else {
+ map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
+ map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
+ }
+}
+
+#else
+#define map_rcnt_rcount0(mode)
+#define map_rcnt_rcount1(mode)
+#define map_rcnt_rcount2(mode)
+#endif
+
#define make_rcnt_funcs(i) \
static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \
static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \
static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \
-static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); } \
+static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
make_rcnt_funcs(0)
static void io_write_ireg16(u32 value)
{
- if (Config.Sio) psxHu16ref(0x1070) |= 0x80;
+ //if (Config.Sio) psxHu16ref(0x1070) |= 0x80;
if (Config.SpuIrq) psxHu16ref(0x1070) |= 0x200;
- psxHu16ref(0x1070) &= psxHu16(0x1074) & value;
+ psxHu16ref(0x1070) &= value;
}
static void io_write_imask16(u32 value)
static void io_write_ireg32(u32 value)
{
- if (Config.Sio) psxHu32ref(0x1070) |= 0x80;
+ //if (Config.Sio) psxHu32ref(0x1070) |= 0x80;
if (Config.SpuIrq) psxHu32ref(0x1070) |= 0x200;
- psxHu32ref(0x1070) &= psxHu32(0x1074) & value;
+ psxHu32ref(0x1070) &= value;
}
static void io_write_imask32(u32 value)
static void io_spu_write16(u32 value)
{
// meh
- SPU_writeRegister(address, value);
+ SPU_writeRegister(address, value, psxRegs.cycle);
}
static void io_spu_write32(u32 value)
SPUwriteRegister wfunc = SPU_writeRegister;
u32 a = address;
- wfunc(a, value & 0xffff);
- wfunc(a + 2, value >> 16);
+ wfunc(a, value & 0xffff, psxRegs.cycle);
+ wfunc(a + 2, value >> 16, psxRegs.cycle);
}
-static u32 *mem_readtab;
-static u32 *mem_writetab;
-static u32 mem_iortab[(1+2+4) * 0x1000 / 4];
-static u32 mem_iowtab[(1+2+4) * 0x1000 / 4];
-static u32 mem_ffwtab[(1+2+4) * 0x1000 / 4];
-//static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4];
-static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4];
-
-static void map_item(u32 *out, const void *h, u32 flag)
+static u32 io_gpu_read_status(void)
{
- u32 hv = (u32)h;
- if (hv & 1)
- fprintf(stderr, "%p has LSB set\n", h);
- *out = (hv >> 1) | (flag << 31);
-}
+ u32 v;
-// size must be power of 2, at least 4k
-#define map_l1_mem(tab, i, addr, size, base) \
- map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0)
+ // meh2, syncing for img bit, might want to avoid it..
+ gpuSyncPluginSR();
+ v = HW_GPU_STATUS;
-#define IOMEM32(a) (((a) & 0xfff) / 4)
-#define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
-#define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
+ // XXX: because of large timeslices can't use hSyncCount, using rough
+ // approximization instead. Perhaps better use hcounter code here or something.
+ if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
+ v |= PSXGPU_LCF & (psxRegs.cycle << 20);
+ return v;
+}
+
+static void io_gpu_write_status(u32 value)
+{
+ GPU_writeStatus(value);
+ gpuSyncPluginSR();
+}
static void map_ram_write(void)
{
}
}
+void new_dyna_pcsx_mem_load_state(void)
+{
+ map_rcnt_rcount0(rcnts[0].mode);
+ map_rcnt_rcount1(rcnts[1].mode);
+ map_rcnt_rcount2(rcnts[2].mode);
+}
+
+int pcsxmem_is_handler_dynamic(u_int addr)
+{
+ if ((addr & 0xfffff000) != 0x1f801000)
+ return 0;
+
+ addr &= 0xffff;
+ return addr == 0x1100 || addr == 0x1110 || addr == 0x1120;
+}
+
void new_dyna_pcsx_mem_init(void)
{
int i;
// have to map these further to keep tcache close to .text
- mem_readtab = mmap((void *)0x08000000, 0x200000 * 4, PROT_READ | PROT_WRITE,
- MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
- if (mem_readtab == MAP_FAILED) {
- fprintf(stderr, "failed to map mem tables\n");
+ mem_readtab = psxMap(0x08000000, 0x200000 * 4, 0, MAP_TAG_LUTS);
+ if (mem_readtab == NULL) {
+ SysPrintf("failed to map mem tables\n");
exit(1);
}
mem_writetab = mem_readtab + 0x100000;
// default/unmapped memhandlers
for (i = 0; i < 0x100000; i++) {
//map_item(&mem_readtab[i], mem_unmrtab, 1);
- map_l1_mem(mem_readtab, i, 0, 0x1000, unmapped_mem);
+ map_l1_mem(mem_readtab, i, 0, 0x1000, zero_mem);
map_item(&mem_writetab[i], mem_unmwtab, 1);
}
// scratchpad
map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
+ map_l1_mem(mem_readtab, 0, 0x9f800000, 0x1000, psxH);
map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
+ map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH);
// I/O
map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
+ map_item(&mem_readtab[0x9f801000 >> 12], mem_iortab, 1);
+ map_item(&mem_readtab[0xbf801000 >> 12], mem_iortab, 1);
map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);
+ map_item(&mem_writetab[0x9f801000 >> 12], mem_iowtab, 1);
+ map_item(&mem_writetab[0xbf801000 >> 12], mem_iowtab, 1);
// L2
// unmapped tables
map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
// map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
-// map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1);
+ map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1);
map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
// map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
-// map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1);
+ map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1);
map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
mem_rtab = mem_readtab;
mem_wtab = mem_writetab;
+
+ new_dyna_pcsx_mem_load_state();
}
void new_dyna_pcsx_mem_reset(void)
// plugins might change so update the pointers
map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
- map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1);
for (i = 0x1c00; i < 0x1e00; i += 2)
map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);
map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
- map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1);
+}
+
+void new_dyna_pcsx_mem_shutdown(void)
+{
+ psxUnmap(mem_readtab, 0x200000 * 4, MAP_TAG_LUTS);
+ mem_writetab = mem_readtab = NULL;
}
notaz.gp2x.de / pcsx_rearmed.git / blobdiff