psx_gpu: partial interlace mode support

[pcsx_rearmed.git] / plugins / gpu_neon / gpu.c

diff --git a/plugins/gpu_neon/gpu.c b/plugins/gpu_neon/gpu.c
index 7f5a8a9..02dd372 100644 (file)
--- a/plugins/gpu_neon/gpu.c
+++ b/plugins/gpu_neon/gpu.c
@@ -24,7 +24,7 @@
 //#define log_anomaly gpu_log
 #define log_anomaly(...)
 
-struct psx_gpu gpu __attribute__((aligned(64)));
+struct psx_gpu gpu __attribute__((aligned(2048)));
 
 static noinline void do_reset(void)
 {
@@ -59,14 +59,32 @@ static noinline void update_height(void)
 
 static noinline void decide_frameskip(void)
 {
-  gpu.frameskip.frame_ready = !gpu.frameskip.active;
+  if (gpu.frameskip.active)
+    gpu.frameskip.cnt++;
+  else {
+    gpu.frameskip.cnt = 0;
+    gpu.frameskip.frame_ready = 1;
+  }
 
-  if (!gpu.frameskip.active && (*gpu.frameskip.advice || gpu.frameskip.set == 1))
+  if (!gpu.frameskip.active && *gpu.frameskip.advice)
+    gpu.frameskip.active = 1;
+  else if (gpu.frameskip.set > 0 && gpu.frameskip.cnt < gpu.frameskip.set)
     gpu.frameskip.active = 1;
   else
     gpu.frameskip.active = 0;
 }
 
+static noinline void decide_frameskip_allow(uint32_t cmd_e3)
+{
+  // no frameskip if it decides to draw to display area,
+  // but not for interlace since it'll most likely always do that
+  uint32_t x = cmd_e3 & 0x3ff;
+  uint32_t y = (cmd_e3 >> 10) & 0x3ff;
+  gpu.frameskip.allow = gpu.status.interlace ||
+    (uint32_t)(x - gpu.screen.x) >= (uint32_t)gpu.screen.w ||
+    (uint32_t)(y - gpu.screen.y) >= (uint32_t)gpu.screen.h;
+}
+
 static noinline void get_gpu_info(uint32_t data)
 {
   switch (data & 0x0f) {
@@ -132,8 +150,13 @@ void GPUwriteStatus(uint32_t data)
     case 0x05:
       gpu.screen.x = data & 0x3ff;
       gpu.screen.y = (data >> 10) & 0x3ff;
-      if (gpu.frameskip.set)
-        decide_frameskip();
+      if (gpu.frameskip.set) {
+        decide_frameskip_allow(gpu.ex_regs[3]);
+        if (gpu.frameskip.last_flip_frame != *gpu.state.frame_count) {
+          decide_frameskip();
+          gpu.frameskip.last_flip_frame = *gpu.state.frame_count;
+        }
+      }
       break;
     case 0x06:
       gpu.screen.x1 = data & 0xfff;
@@ -247,10 +270,15 @@ static void start_vram_transfer(uint32_t pos_word, uint32_t size_word, int is_re
   gpu.dma.h = size_word >> 16;
   gpu.dma.offset = 0;
 
-  if (is_read)
+  renderer_flush_queues();
+  if (is_read) {
     gpu.status.img = 1;
-  else
+    // XXX: wrong for width 1
+    memcpy(&gpu.gp0, VRAM_MEM_XY(gpu.dma.x, gpu.dma.y), 4);
+  }
+  else {
     renderer_invalidate_caches(gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h);
+  }
 
   log_io("start_vram_transfer %c (%d, %d) %dx%d\n", is_read ? 'r' : 'w',
     gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h);
@@ -283,25 +311,17 @@ static int check_cmd(uint32_t *data, int count)
       //printf("  %3d: %02x %d\n", pos, cmd, len);
       if ((cmd & 0xf4) == 0x24) {
         // flat textured prim
-        gpu.status.reg &= ~0x1ff;
-        gpu.status.reg |= list[4] & 0x1ff;
+        gpu.ex_regs[1] &= ~0x1ff;
+        gpu.ex_regs[1] |= list[4] & 0x1ff;
       }
       else if ((cmd & 0xf4) == 0x34) {
         // shaded textured prim
-        gpu.status.reg &= ~0x1ff;
-        gpu.status.reg |= list[5] & 0x1ff;
-      }
-      else switch (cmd)
-      {
-        case 0xe1:
-          gpu.status.reg &= ~0x7ff;
-          gpu.status.reg |= list[0] & 0x7ff;
-          break;
-        case 0xe6:
-          gpu.status.reg &= ~0x1800;
-          gpu.status.reg |= (list[0] & 3) << 11;
-          break;
+        gpu.ex_regs[1] &= ~0x1ff;
+        gpu.ex_regs[1] |= list[5] & 0x1ff;
       }
+      else if (cmd == 0xe3)
+        decide_frameskip_allow(list[0]);
+
       if (2 <= cmd && cmd < 0xc0)
         vram_dirty = 1;
       else if ((cmd & 0xf8) == 0xe0)
@@ -317,7 +337,7 @@ static int check_cmd(uint32_t *data, int count)
     }
 
     if (pos - start > 0) {
-      if (!gpu.frameskip.active)
+      if (!gpu.frameskip.active || !gpu.frameskip.allow)
         do_cmd_list(data + start, pos - start);
       start = pos;
     }
@@ -331,6 +351,10 @@ static int check_cmd(uint32_t *data, int count)
       break;
   }
 
+  gpu.status.reg &= ~0x1fff;
+  gpu.status.reg |= gpu.ex_regs[1] & 0x7ff;
+  gpu.status.reg |= (gpu.ex_regs[6] & 3) << 11;
+
   if (gpu.frameskip.active)
     renderer_sync_ecmds(gpu.ex_regs);
   gpu.state.fb_dirty |= vram_dirty;
@@ -338,7 +362,7 @@ static int check_cmd(uint32_t *data, int count)
   return count - pos;
 }
 
-static void flush_cmd_buffer(void)
+void flush_cmd_buffer(void)
 {
   int left = check_cmd(gpu.cmd_buffer, gpu.cmd_len);
   if (left > 0)
@@ -373,7 +397,7 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
   uint32_t addr, *list;
   uint32_t *llist_entry = NULL;
   int len, left, count;
-  long dma_words = 0;
+  long cpu_cycles = 0;
 
   if (unlikely(gpu.cmd_len > 0))
     flush_cmd_buffer();
@@ -381,7 +405,7 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
   // ff7 sends it's main list twice, detect this
   if (*gpu.state.frame_count == gpu.state.last_list.frame &&
       *gpu.state.hcnt - gpu.state.last_list.hcnt <= 1 &&
-       gpu.state.last_list.words > 1024)
+       gpu.state.last_list.cycles > 2048)
   {
     llist_entry = rambase + (gpu.state.last_list.addr & 0x1fffff) / 4;
     *llist_entry |= 0x800000;
@@ -394,7 +418,9 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
     list = rambase + (addr & 0x1fffff) / 4;
     len = list[0] >> 24;
     addr = list[0] & 0xffffff;
-    dma_words += 1 + len;
+    cpu_cycles += 10;
+    if (len > 0)
+      cpu_cycles += 5 + len;
 
     log_io(".chain %08x #%d\n", (list - rambase) * 4, len);
 
@@ -425,10 +451,10 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
 
   gpu.state.last_list.frame = *gpu.state.frame_count;
   gpu.state.last_list.hcnt = *gpu.state.hcnt;
-  gpu.state.last_list.words = dma_words;
+  gpu.state.last_list.cycles = cpu_cycles;
   gpu.state.last_list.addr = start_addr;
 
-  return dma_words;
+  return cpu_cycles;
 }
 
 void GPUreadDataMem(uint32_t *mem, int count)
@@ -444,15 +470,17 @@ void GPUreadDataMem(uint32_t *mem, int count)
 
 uint32_t GPUreadData(void)
 {
-  log_io("gpu_read\n");
+  uint32_t ret;
 
   if (unlikely(gpu.cmd_len > 0))
     flush_cmd_buffer();
 
+  ret = gpu.gp0;
   if (gpu.dma.h)
-    do_vram_io(&gpu.gp0, 1, 1);
+    do_vram_io(&ret, 1, 1);
 
-  return gpu.gp0;
+  log_io("gpu_read %08x\n", ret);
+  return ret;
 }
 
 uint32_t GPUreadStatus(void)
@@ -467,15 +495,15 @@ uint32_t GPUreadStatus(void)
   return ret;
 }
 
-typedef struct GPUFREEZETAG
+struct GPUFreeze
 {
   uint32_t ulFreezeVersion;      // should be always 1 for now (set by main emu)
   uint32_t ulStatus;             // current gpu status
   uint32_t ulControl[256];       // latest control register values
   unsigned char psxVRam[1024*1024*2]; // current VRam image (full 2 MB for ZN)
-} GPUFreeze_t;
+};
 
-long GPUfreeze(uint32_t type, GPUFreeze_t *freeze)
+long GPUfreeze(uint32_t type, struct GPUFreeze *freeze)
 {
   int i;
 
@@ -505,4 +533,8 @@ long GPUfreeze(uint32_t type, GPUFreeze_t *freeze)
   return 1;
 }
 
+void GPUvBlank(int is_vblank, int lcf)
+{
+}
+
 // vim:shiftwidth=2:expandtab