update build for OABI

[pcsx_rearmed.git] / plugins / gpu_neon / gpu.c

diff --git a/plugins/gpu_neon/gpu.c b/plugins/gpu_neon/gpu.c
index c7807f6..c275d83 100644 (file)
--- a/plugins/gpu_neon/gpu.c
+++ b/plugins/gpu_neon/gpu.c
@@ -16,9 +16,13 @@
 #define unlikely(x) __builtin_expect((x), 0)
 #define noinline __attribute__((noinline))
 
-//#define log_io printf
+#define gpu_log(fmt, ...) \
+  printf("%d:%03d: " fmt, gpu.state.frame_count, *gpu.state.hcnt, ##__VA_ARGS__)
+
+//#define log_io gpu_log
 #define log_io(...)
-#define log_anomaly printf
+//#define log_anomaly gpu_log
+#define log_anomaly(...)
 
 struct psx_gpu gpu __attribute__((aligned(64)));
 
@@ -57,7 +61,7 @@ static noinline void decide_frameskip(void)
 {
   gpu.frameskip.frame_ready = !gpu.frameskip.active;
 
-  if (!gpu.frameskip.active && *gpu.frameskip.advice)
+  if (!gpu.frameskip.active && (*gpu.frameskip.advice || gpu.frameskip.set == 1))
     gpu.frameskip.active = 1;
   else
     gpu.frameskip.active = 0;
@@ -86,9 +90,14 @@ static noinline void get_gpu_info(uint32_t data)
 
 long GPUinit(void)
 {
-  int ret = vout_init();
-  do_reset();
+  int ret;
+  ret  = vout_init();
+  ret |= renderer_init();
+
   gpu.lcf_hc = &gpu.zero;
+  gpu.state.frame_count = 0;
+  gpu.state.hcnt = &gpu.zero;
+  do_reset();
   return ret;
 }
 
@@ -104,7 +113,7 @@ void GPUwriteStatus(uint32_t data)
   uint32_t cmd = data >> 24;
 
   if (cmd < ARRAY_SIZE(gpu.regs)) {
-    if (cmd != 0 && gpu.regs[cmd] == data)
+    if (cmd != 0 && cmd != 5 && gpu.regs[cmd] == data)
       return;
     gpu.regs[cmd] = data;
   }
@@ -124,7 +133,7 @@ void GPUwriteStatus(uint32_t data)
     case 0x05:
       gpu.screen.x = data & 0x3ff;
       gpu.screen.y = (data >> 10) & 0x3ff;
-      if (gpu.frameskip.enabled)
+      if (gpu.frameskip.set)
         decide_frameskip();
       break;
     case 0x06:
@@ -144,8 +153,9 @@ void GPUwriteStatus(uint32_t data)
       update_width();
       update_height();
       break;
-    case 0x10 ... 0x1f:
-      get_gpu_info(data);
+    default:
+      if ((cmd & 0xf0) == 0x10)
+        get_gpu_info(data);
       break;
   }
 }
@@ -240,6 +250,8 @@ static void start_vram_transfer(uint32_t pos_word, uint32_t size_word, int is_re
 
   if (is_read)
     gpu.status.img = 1;
+  else
+    renderer_invalidate_caches(gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h);
 
   log_io("start_vram_transfer %c (%d, %d) %dx%d\n", is_read ? 'r' : 'w',
     gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h);
@@ -316,11 +328,12 @@ static int check_cmd(uint32_t *data, int count)
       start_vram_transfer(data[pos + 1], data[pos + 2], cmd == 0xc0);
       pos += len;
     }
-
-    if (cmd == -1)
+    else if (cmd == -1)
       break;
   }
 
+  if (gpu.frameskip.active)
+    renderer_sync_ecmds(gpu.ex_regs);
   gpu.state.fb_dirty |= vram_dirty;
 
   return count - pos;
@@ -359,20 +372,32 @@ void GPUwriteData(uint32_t data)
 long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
 {
   uint32_t addr, *list;
+  uint32_t *llist_entry = NULL;
   int len, left, count;
+  long dma_words = 0;
 
   if (unlikely(gpu.cmd_len > 0))
     flush_cmd_buffer();
 
+  // ff7 sends it's main list twice, detect this
+  if (gpu.state.frame_count == gpu.state.last_list.frame &&
+     *gpu.state.hcnt - gpu.state.last_list.hcnt <= 1 &&
+      gpu.state.last_list.words > 1024)
+  {
+    llist_entry = rambase + (gpu.state.last_list.addr & 0x1fffff) / 4;
+    *llist_entry |= 0x800000;
+  }
+
   log_io("gpu_dma_chain\n");
   addr = start_addr & 0xffffff;
   for (count = 0; addr != 0xffffff; count++)
   {
-    log_io(".chain %08x\n", addr);
-
     list = rambase + (addr & 0x1fffff) / 4;
     len = list[0] >> 24;
     addr = list[0] & 0xffffff;
+    dma_words += 1 + len;
+
+    log_io(".chain %08x #%d\n", (list - rambase) * 4, len);
 
     // loop detection marker
     // (bit23 set causes DMA error on real machine, so
@@ -382,7 +407,7 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
     if (len) {
       left = check_cmd(list + 1, len);
       if (left)
-        log_anomaly("GPUwriteDataMem: discarded %d/%d words\n", left, len);
+        log_anomaly("GPUdmaChain: discarded %d/%d words\n", left, len);
     }
 
     if (addr & 0x800000)
@@ -396,8 +421,15 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
     addr = list[0] & 0x1fffff;
     list[0] &= ~0x800000;
   }
+  if (llist_entry)
+    *llist_entry &= ~0x800000;
+
+  gpu.state.last_list.frame = gpu.state.frame_count;
+  gpu.state.last_list.hcnt = *gpu.state.hcnt;
+  gpu.state.last_list.words = dma_words;
+  gpu.state.last_list.addr = start_addr;
 
-  return 0;
+  return dma_words;
 }
 
 void GPUreadDataMem(uint32_t *mem, int count)
@@ -458,6 +490,7 @@ long GPUfreeze(uint32_t type, GPUFreeze_t *freeze)
       freeze->ulStatus = gpu.status.reg;
       break;
     case 0: // load
+      renderer_invalidate_caches(0, 0, 1024, 512);
       memcpy(gpu.vram, freeze->psxVRam, sizeof(gpu.vram));
       memcpy(gpu.regs, freeze->ulControl, sizeof(gpu.regs));
       memcpy(gpu.ex_regs, freeze->ulControl + 0xe0, sizeof(gpu.ex_regs));
@@ -466,6 +499,7 @@ long GPUfreeze(uint32_t type, GPUFreeze_t *freeze)
         gpu.regs[i] ^= 1; // avoid reg change detection
         GPUwriteStatus((i << 24) | (gpu.regs[i] ^ 1));
       }
+      renderer_sync_ecmds(gpu.ex_regs);
       break;
   }
 
@@ -484,6 +518,10 @@ void GPUvBlank(int val, uint32_t *hcnt)
     if (!val)
       gpu.lcf_hc = hcnt;
   }
+  if (!val)
+    gpu.state.frame_count++;
+
+  gpu.state.hcnt = hcnt;
 }
 
 // vim:shiftwidth=2:expandtab