X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fassem_arm.c;h=2b0ef9cc0a4768d7e1468d1feefb0eb5e0849ac6;hp=56b0c1aa58502df455f09674fabbb7faf471e969;hb=ea3d2e6e638ffd02aee0be8bdd27d8a9babd179f;hpb=fca1aef29ed173264919b7a0b35f92dbe0d4e521 diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c index 56b0c1aa..2b0ef9cc 100644 --- a/libpcsxcore/new_dynarec/assem_arm.c +++ b/libpcsxcore/new_dynarec/assem_arm.c @@ -1,6 +1,6 @@ /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Mupen64plus - assem_arm.c * - * Copyright (C) 2009-2010 Ari64 * + * Copyright (C) 2009-2011 Ari64 * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -66,8 +66,41 @@ const u_int jump_vaddr_reg[16] = { 0, 0}; +void invalidate_addr_r0(); +void invalidate_addr_r1(); +void invalidate_addr_r2(); +void invalidate_addr_r3(); +void invalidate_addr_r4(); +void invalidate_addr_r5(); +void invalidate_addr_r6(); +void invalidate_addr_r7(); +void invalidate_addr_r8(); +void invalidate_addr_r9(); +void invalidate_addr_r10(); +void invalidate_addr_r12(); + +const u_int invalidate_addr_reg[16] = { + (int)invalidate_addr_r0, + (int)invalidate_addr_r1, + (int)invalidate_addr_r2, + (int)invalidate_addr_r3, + (int)invalidate_addr_r4, + (int)invalidate_addr_r5, + (int)invalidate_addr_r6, + (int)invalidate_addr_r7, + (int)invalidate_addr_r8, + (int)invalidate_addr_r9, + (int)invalidate_addr_r10, + 0, + (int)invalidate_addr_r12, + 0, + 0, + 0}; + #include "fpu.h" +unsigned int needs_clear_cache[1<<(TARGET_SIZE_2-17)]; + /* Linker */ void set_jump_target(int addr,u_int target) @@ -812,7 +845,8 @@ u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift) } u_int genimm(u_int imm,u_int *encoded) { - if(imm==0) {*encoded=0;return 1;} + *encoded=0; + if(imm==0) return 1; int i=32; while(i>0) { @@ -914,12 +948,63 @@ void emit_zeroreg(int rt) output_w32(0xe3a00000|rd_rn_rm(rt,0,0)); } +void emit_loadlp(u_int imm,u_int rt) +{ + add_literal((int)out,imm); + assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm); + output_w32(0xe5900000|rd_rn_rm(rt,15,0)); +} +void emit_movw(u_int imm,u_int rt) +{ + assert(imm<65536); + assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm); + output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000)); +} +void emit_movt(u_int imm,u_int rt) +{ + assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000); + output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000)); +} +void emit_movimm(u_int imm,u_int rt) +{ + u_int armval; + if(genimm(imm,&armval)) { + assem_debug("mov %s,#%d\n",regname[rt],imm); + output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval); + }else if(genimm(~imm,&armval)) { + assem_debug("mvn %s,#%d\n",regname[rt],imm); + output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval); + }else if(imm<65536) { + #ifdef ARMv5_ONLY + assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00); + output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8)); + assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF); + output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0)); + #else + emit_movw(imm,rt); + #endif + }else{ + #ifdef ARMv5_ONLY + emit_loadlp(imm,rt); + #else + emit_movw(imm&0x0000FFFF,rt); + emit_movt(imm&0xFFFF0000,rt); + #endif + } +} +void emit_pcreladdr(u_int rt) +{ + assem_debug("add %s,pc,#?\n",regname[rt]); + output_w32(0xe2800000|rd_rn_rm(rt,15,0)); +} + void emit_loadreg(int r, int hr) { #ifdef FORCE32 if(r&64) { printf("64bit load in 32bit mode!\n"); - exit(1); + assert(0); + return; } #endif if((r&63)==0) @@ -943,7 +1028,8 @@ void emit_storereg(int r, int hr) #ifdef FORCE32 if(r&64) { printf("64bit store in 32bit mode!\n"); - exit(1); + assert(0); + return; } #endif int addr=((int)reg)+((r&63)<>4); @@ -1008,6 +1094,15 @@ void emit_or_and_set_flags(int rs1,int rs2,int rt) output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2)); } +void emit_orrshl_imm(u_int rs,u_int imm,u_int rt) +{ + assert(rs<16); + assert(rt<16); + assert(imm<32); + assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs],imm); + output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|(imm<<7)); +} + void emit_orrshr_imm(u_int rs,u_int imm,u_int rt) { assert(rs<16); @@ -1023,56 +1118,6 @@ void emit_xor(u_int rs1,u_int rs2,u_int rt) output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2)); } -void emit_loadlp(u_int imm,u_int rt) -{ - add_literal((int)out,imm); - assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm); - output_w32(0xe5900000|rd_rn_rm(rt,15,0)); -} -void emit_movw(u_int imm,u_int rt) -{ - assert(imm<65536); - assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm); - output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000)); -} -void emit_movt(u_int imm,u_int rt) -{ - assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000); - output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000)); -} -void emit_movimm(u_int imm,u_int rt) -{ - u_int armval; - if(genimm(imm,&armval)) { - assem_debug("mov %s,#%d\n",regname[rt],imm); - output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval); - }else if(genimm(~imm,&armval)) { - assem_debug("mvn %s,#%d\n",regname[rt],imm); - output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval); - }else if(imm<65536) { - #ifdef ARMv5_ONLY - assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00); - output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8)); - assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF); - output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0)); - #else - emit_movw(imm,rt); - #endif - }else{ - #ifdef ARMv5_ONLY - emit_loadlp(imm,rt); - #else - emit_movw(imm&0x0000FFFF,rt); - emit_movt(imm&0xFFFF0000,rt); - #endif - } -} -void emit_pcreladdr(u_int rt) -{ - assem_debug("add %s,pc,#?\n",regname[rt]); - output_w32(0xe2800000|rd_rn_rm(rt,15,0)); -} - void emit_addimm(u_int rs,int imm,u_int rt) { assert(rs<16); @@ -1193,7 +1238,9 @@ void emit_sbb(int rs1,int rs2) void emit_andimm(int rs,int imm,int rt) { u_int armval; - if(genimm(imm,&armval)) { + if(imm==0) { + emit_zeroreg(rt); + }else if(genimm(imm,&armval)) { assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm); output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval); }else if(genimm(~imm,&armval)) { @@ -1227,7 +1274,9 @@ void emit_andimm(int rs,int imm,int rt) void emit_orimm(int rs,int imm,int rt) { u_int armval; - if(genimm(imm,&armval)) { + if(imm==0) { + if(rs!=rt) emit_mov(rs,rt); + }else if(genimm(imm,&armval)) { assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm); output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval); }else{ @@ -1242,7 +1291,9 @@ void emit_orimm(int rs,int imm,int rt) void emit_xorimm(int rs,int imm,int rt) { u_int armval; - if(genimm(imm,&armval)) { + if(imm==0) { + if(rs!=rt) emit_mov(rs,rt); + }else if(genimm(imm,&armval)) { assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm); output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval); }else{ @@ -2178,6 +2229,13 @@ void emit_addsr12(int rs1,int rs2,int rt) output_w32(0xe0800620|rd_rn_rm(rt,rs1,rs2)); } +void emit_callne(int a) +{ + assem_debug("blne %x\n",a); + u_int offset=genjmp(a); + output_w32(0x1b000000|offset); +} + // Used to preload hash table entries void emit_prefetch(void *addr) { @@ -2547,6 +2605,10 @@ emit_extjump_ds(int addr, int target) emit_extjump2(addr, target, (int)dyna_linker_ds); } +#ifdef PCSX +#include "pcsxmem_inline.c" +#endif + do_readstub(int n) { assem_debug("do_readstub %x\n",start+stubs[n][3]*4); @@ -2570,9 +2632,7 @@ do_readstub(int n) } assert(rs>=0); if(addr<0) addr=rt; - if(addr<0) - // assume dummy read, no alloced reg - addr=get_reg(i_regmap,-1); + if(addr<0&&itype[i]!=C1LS&&itype[i]!=C2LS&&itype[i]!=LOADLR) addr=get_reg(i_regmap,-1); assert(addr>=0); int ftable=0; if(type==LOADB_STUB||type==LOADBU_STUB) @@ -2589,12 +2649,14 @@ do_readstub(int n) emit_writeword(rs,(int)&address); //emit_pusha(); save_regs(reglist); +#ifndef PCSX ds=i_regs!=®s[i]; int real_rs=(itype[i]==LOADLR)?-1:get_reg(i_regmap,rs1[i]); u_int cmask=ds?-1:(0x100f|~i_regs->wasconst); if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<>rs1[i])&1)<<1)+ds,3); +#endif //emit_readword((int)&last_count,temp); //emit_add(cc,temp,cc); //emit_writeword(cc,(int)&Count); @@ -2610,6 +2674,7 @@ do_readstub(int n) emit_call((int)&indirect_jump_indexed); //emit_callreg(rs); //emit_readword_dualindexedx4(rs,HOST_TEMPREG,15); +#ifndef PCSX // We really shouldn't need to update the count here, // but not doing so causes random crashes... emit_readword((int)&Count,HOST_TEMPREG); @@ -2620,6 +2685,7 @@ do_readstub(int n) if(cc<0) { emit_storereg(CCREG,HOST_TEMPREG); } +#endif //emit_popa(); restore_regs(reglist); //if((cc=get_reg(regmap,CCREG))>=0) { @@ -2650,8 +2716,8 @@ inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, i int rs=get_reg(regmap,target); int rth=get_reg(regmap,target|64); int rt=get_reg(regmap,target); + if(rs<0) rs=get_reg(regmap,-1); assert(rs>=0); - assert(rt>=0); int ftable=0; if(type==LOADB_STUB||type==LOADBU_STUB) ftable=(int)readmemb; @@ -2664,9 +2730,27 @@ inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, i ftable=(int)readmemd; #endif assert(ftable!=0); +#ifdef PCSX + if(pcsx_direct_read(type,addr,target?rs:-1,rt)) + return; +#endif + if(target==0) + emit_movimm(addr,rs); emit_writeword(rs,(int)&address); //emit_pusha(); save_regs(reglist); +#ifndef PCSX + if((signed int)addr>=(signed int)0xC0000000) { + // Theoretically we can have a pagefault here, if the TLB has never + // been enabled and the address is outside the range 80000000..BFFFFFFF + // Write out the registers so the pagefault can be handled. This is + // a very rare case and likely represents a bug. + int ds=regmap!=regs[i].regmap; + if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i); + if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty); + else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty); + } +#endif //emit_shrimm(rs,16,1); int cc=get_reg(regmap,CCREG); if(cc<0) { @@ -2676,15 +2760,18 @@ inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, i emit_movimm(((u_int *)ftable)[addr>>16],0); //emit_readword((int)&last_count,12); emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2); +#ifndef PCSX if((signed int)addr>=(signed int)0xC0000000) { // Pagefault address int ds=regmap!=regs[i].regmap; emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3); } +#endif //emit_add(12,2,2); //emit_writeword(2,(int)&Count); //emit_call(((u_int *)ftable)[addr>>16]); emit_call((int)&indirect_jump); +#ifndef PCSX // We really shouldn't need to update the count here, // but not doing so causes random crashes... emit_readword((int)&Count,HOST_TEMPREG); @@ -2695,21 +2782,24 @@ inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, i if(cc<0) { emit_storereg(CCREG,HOST_TEMPREG); } +#endif //emit_popa(); restore_regs(reglist); - if(type==LOADB_STUB) - emit_movsbl((int)&readmem_dword,rt); - if(type==LOADBU_STUB) - emit_movzbl((int)&readmem_dword,rt); - if(type==LOADH_STUB) - emit_movswl((int)&readmem_dword,rt); - if(type==LOADHU_STUB) - emit_movzwl((int)&readmem_dword,rt); - if(type==LOADW_STUB) - emit_readword((int)&readmem_dword,rt); - if(type==LOADD_STUB) { - emit_readword((int)&readmem_dword,rt); - if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth); + if(rt>=0) { + if(type==LOADB_STUB) + emit_movsbl((int)&readmem_dword,rt); + if(type==LOADBU_STUB) + emit_movzbl((int)&readmem_dword,rt); + if(type==LOADH_STUB) + emit_movswl((int)&readmem_dword,rt); + if(type==LOADHU_STUB) + emit_movzwl((int)&readmem_dword,rt); + if(type==LOADW_STUB) + emit_readword((int)&readmem_dword,rt); + if(type==LOADD_STUB) { + emit_readword((int)&readmem_dword,rt); + if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth); + } } } @@ -2769,12 +2859,14 @@ do_writestub(int n) } //emit_pusha(); save_regs(reglist); +#ifndef PCSX ds=i_regs!=®s[i]; int real_rs=get_reg(i_regmap,rs1[i]); u_int cmask=ds?-1:(0x100f|~i_regs->wasconst); if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<>rs1[i])&1)<<1)+ds,3); +#endif //emit_readword((int)&last_count,temp); //emit_addimm(cc,2*stubs[n][5]+2,cc); //emit_add(cc,temp,cc); @@ -2812,6 +2906,10 @@ inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int rt=get_reg(regmap,target); assert(rs>=0); assert(rt>=0); +#ifdef PCSX + if(pcsx_direct_write(type,addr,rs,rt,regmap)) + return; +#endif int ftable=0; if(type==STOREB_STUB) ftable=(int)writememb; @@ -2843,6 +2941,19 @@ inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, } //emit_pusha(); save_regs(reglist); +#ifndef PCSX + // rearmed note: load_all_consts prevents BIOS boot, some bug? + if((signed int)addr>=(signed int)0xC0000000) { + // Theoretically we can have a pagefault here, if the TLB has never + // been enabled and the address is outside the range 80000000..BFFFFFFF + // Write out the registers so the pagefault can be handled. This is + // a very rare case and likely represents a bug. + int ds=regmap!=regs[i].regmap; + if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i); + if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty); + else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty); + } +#endif //emit_shrimm(rs,16,1); int cc=get_reg(regmap,CCREG); if(cc<0) { @@ -2852,11 +2963,13 @@ inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, emit_movimm(((u_int *)ftable)[addr>>16],0); //emit_readword((int)&last_count,12); emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2); +#ifndef PCSX if((signed int)addr>=(signed int)0xC0000000) { // Pagefault address int ds=regmap!=regs[i].regmap; emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3); } +#endif //emit_add(12,2,2); //emit_writeword(2,(int)&Count); //emit_call(((u_int *)ftable)[addr>>16]); @@ -2898,12 +3011,14 @@ do_unalignedwritestub(int n) emit_writeword(temp2,(int)&address); save_regs(reglist); +#ifndef PCSX ds=i_regs!=®s[i]; real_rs=get_reg(i_regmap,rs1[i]); u_int cmask=ds?-1:(0x100f|~i_regs->wasconst); if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<>rs1[i])&1)<<1)+ds,3); // XXX: can be rm'd? +#ifndef PCSX + // pagefault address + emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3); +#endif emit_call((int)&indirect_jump_indexed); restore_regs(reglist); @@ -3238,7 +3356,7 @@ void loadlr_assemble_arm(int i,struct regstat *i_regs) int s,th,tl,temp,temp2,addr,map=-1; int offset; int jaddr=0; - int memtarget,c=0; + int memtarget=0,c=0; u_int hr,reglist=0; th=get_reg(i_regs->regmap,rt1[i]|64); tl=get_reg(i_regs->regmap,rt1[i]); @@ -3256,60 +3374,66 @@ void loadlr_assemble_arm(int i,struct regstat *i_regs) else addr=s; if(s>=0) { c=(i_regs->wasconst>>s)&1; - memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; - if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1; - } - if(tl>=0) { - //assert(tl>=0); - //assert(rt1[i]); - if(!using_tlb) { - if(!c) { - emit_shlimm(addr,3,temp); - if (opcode[i]==0x22||opcode[i]==0x26) { - emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR - }else{ - emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR - } - emit_cmpimm(addr,RAM_SIZE); - jaddr=(int)out; - emit_jno(0); - } - else { - if (opcode[i]==0x22||opcode[i]==0x26) { - emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR - }else{ - emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR - } - } - }else{ // using tlb - int a; - if(c) { - a=-1; - }else if (opcode[i]==0x22||opcode[i]==0x26) { - a=0xFFFFFFFC; // LWL/LWR + if(c) { + memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; + if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1; + } + } + if(!using_tlb) { + if(!c) { + #ifdef RAM_OFFSET + map=get_reg(i_regs->regmap,ROREG); + if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG); + #endif + emit_shlimm(addr,3,temp); + if (opcode[i]==0x22||opcode[i]==0x26) { + emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR }else{ - a=0xFFFFFFF8; // LDL/LDR + emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR } - map=get_reg(i_regs->regmap,TLREG); - assert(map>=0); - map=do_tlb_r(addr,temp2,map,0,a,c?-1:temp,c,constmap[i][s]+offset); - if(c) { - if (opcode[i]==0x22||opcode[i]==0x26) { - emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR - }else{ - emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR - } + emit_cmpimm(addr,RAM_SIZE); + jaddr=(int)out; + emit_jno(0); + } + else { + if (opcode[i]==0x22||opcode[i]==0x26) { + emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR + }else{ + emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR } - do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr); } - if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR - if(!c||memtarget) { - //emit_readword_indexed((int)rdram-0x80000000,temp2,temp2); - emit_readword_indexed_tlb((int)rdram-0x80000000,temp2,map,temp2); - if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist); + }else{ // using tlb + int a; + if(c) { + a=-1; + }else if (opcode[i]==0x22||opcode[i]==0x26) { + a=0xFFFFFFFC; // LWL/LWR + }else{ + a=0xFFFFFFF8; // LDL/LDR + } + map=get_reg(i_regs->regmap,TLREG); + assert(map>=0); + reglist&=~(1<regmap,FTEMP,ccadj[i],reglist); + } + do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr); + } + if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR + if(!c||memtarget) { + //emit_readword_indexed((int)rdram-0x80000000,temp2,temp2); + emit_readword_indexed_tlb(0,temp2,map,temp2); + if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist); + } + else + inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist); + if(rt1[i]) { + assert(tl>=0); emit_andimm(temp,24,temp); #ifdef BIG_ENDIAN_MIPS if (opcode[i]==0x26) // LWR @@ -3326,19 +3450,23 @@ void loadlr_assemble_arm(int i,struct regstat *i_regs) emit_bic_lsl(tl,HOST_TEMPREG,temp,tl); } emit_or(temp2,tl,tl); - //emit_storereg(rt1[i],tl); // DEBUG } - if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR - // FIXME: little endian - int temp2h=get_reg(i_regs->regmap,FTEMP|64); - if(!c||memtarget) { - //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h); - //emit_readword_indexed((int)rdram-0x7FFFFFFC,temp2,temp2); - emit_readdword_indexed_tlb((int)rdram-0x80000000,temp2,map,temp2h,temp2); - if(jaddr) add_stub(LOADD_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist); - } - else - inline_readstub(LOADD_STUB,i,(constmap[i][s]+offset)&0xFFFFFFF8,i_regs->regmap,FTEMP,ccadj[i],reglist); + //emit_storereg(rt1[i],tl); // DEBUG + } + if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR + // FIXME: little endian + int temp2h=get_reg(i_regs->regmap,FTEMP|64); + if(!c||memtarget) { + //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h); + //emit_readword_indexed((int)rdram-0x7FFFFFFC,temp2,temp2); + emit_readdword_indexed_tlb(0,temp2,map,temp2h,temp2); + if(jaddr) add_stub(LOADD_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist); + } + else + inline_readstub(LOADD_STUB,i,(constmap[i][s]+offset)&0xFFFFFFF8,i_regs->regmap,FTEMP,ccadj[i],reglist); + if(rt1[i]) { + assert(th>=0); + assert(tl>=0); emit_testimm(temp,32); emit_andimm(temp,24,temp); if (opcode[i]==0x1A) { // LDL @@ -3540,25 +3668,22 @@ static void cop2_get_dreg(u_int copr,signed char tl,signed char temp) emit_writeword(tl,(int)®_cop2d[copr]); break; case 28: - case 30: - emit_movimm(0,tl); - break; case 29: emit_readword((int)®_cop2d[9],temp); emit_testimm(temp,0x8000); // do we need this? emit_andimm(temp,0xf80,temp); emit_andne_imm(temp,0,temp); - emit_shr(temp,7,tl); + emit_shrimm(temp,7,tl); emit_readword((int)®_cop2d[10],temp); emit_testimm(temp,0x8000); emit_andimm(temp,0xf80,temp); emit_andne_imm(temp,0,temp); - emit_orrshr(temp,2,tl); + emit_orrshr_imm(temp,2,tl); emit_readword((int)®_cop2d[11],temp); emit_testimm(temp,0x8000); emit_andimm(temp,0xf80,temp); emit_andne_imm(temp,0,temp); - emit_orrshl(temp,3,tl); + emit_orrshl_imm(temp,3,tl); emit_writeword(tl,(int)®_cop2d[copr]); break; default: @@ -3580,13 +3705,13 @@ static void cop2_put_dreg(u_int copr,signed char sl,signed char temp) break; case 28: emit_andimm(sl,0x001f,temp); - emit_shl(temp,7,temp); + emit_shlimm(temp,7,temp); emit_writeword(temp,(int)®_cop2d[9]); emit_andimm(sl,0x03e0,temp); - emit_shl(temp,2,temp); + emit_shlimm(temp,2,temp); emit_writeword(temp,(int)®_cop2d[10]); emit_andimm(sl,0x7c00,temp); - emit_shr(temp,3,temp); + emit_shrimm(temp,3,temp); emit_writeword(temp,(int)®_cop2d[11]); emit_writeword(sl,(int)®_cop2d[28]); break; @@ -3597,8 +3722,6 @@ static void cop2_put_dreg(u_int copr,signed char sl,signed char temp) emit_writeword(sl,(int)®_cop2d[30]); emit_writeword(temp,(int)®_cop2d[31]); break; - case 7: - case 29: case 31: break; default: @@ -3671,10 +3794,11 @@ void c2op_assemble(int i,struct regstat *i_regs) if (gte_handlers[c2op]!=NULL) { int cc=get_reg(i_regs->regmap,CCREG); - emit_movimm(source[i],temp); // opcode + emit_movimm(source[i],1); // opcode if (cc>=0&>e_cycletab[c2op]) - emit_addimm(cc,gte_cycletab[c2op]/2,cc); // XXX: cound just adjust ccadj? - emit_writeword(temp,(int)&psxRegs.code); + emit_addimm(cc,gte_cycletab[c2op]/2,cc); // XXX: could just adjust ccadj? + emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0); // cop2 regs + emit_writeword(1,(int)&psxRegs.code); emit_call((int)gte_handlers[c2op]); } @@ -4765,6 +4889,38 @@ void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint #define wb_invalidate wb_invalidate_arm */ +// Clearing the cache is rather slow on ARM Linux, so mark the areas +// that need to be cleared, and then only clear these areas once. +void do_clear_cache() +{ + int i,j; + for (i=0;i<(1<<(TARGET_SIZE_2-17));i++) + { + u_int bitmap=needs_clear_cache[i]; + if(bitmap) { + u_int start,end; + for(j=0;j<32;j++) + { + if(bitmap&(1<