X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fassem_arm.c;h=4bddd8c5fd0902ddf9cf3d2766bf3020dafdca06;hp=4af1566d2db08464feca06a0256c9da6cc54e3f2;hb=822b27d12f2c2a66f8de4ff7109f452048c5d899;hpb=e80343e2eb43452aa1518f78a5cc62f7ac55b163

diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c
index 4af1566d..4bddd8c5 100644
--- a/libpcsxcore/new_dynarec/assem_arm.c
+++ b/libpcsxcore/new_dynarec/assem_arm.c
@@ -205,7 +205,7 @@ int verify_dirty(int addr)
   #endif
   if((*ptr&0xFF000000)!=0xeb000000) ptr++;
   assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
-  u_int verifier=(int)ptr+((*ptr<<8)>>6)+8; // get target of bl
+  u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
   if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
     unsigned int page=source>>12;
     unsigned int map_value=memory_map[page];
@@ -258,7 +258,7 @@ void get_bounds(int addr,u_int *start,u_int *end)
   #endif
   if((*ptr&0xFF000000)!=0xeb000000) ptr++;
   assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
-  u_int verifier=(int)ptr+((*ptr<<8)>>6)+8; // get target of bl
+  u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
   if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
     if(memory_map[source>>12]>=0x80000000) source = 0;
     else source = source+(memory_map[source>>12]<<2);
@@ -2416,10 +2416,12 @@ void wb_consts(signed char i_regmap[],uint64_t i_is32,u_int i_dirty,int i)
             emit_movimm(value,HOST_TEMPREG);
           }
           emit_storereg(i_regmap[hr],HOST_TEMPREG);
+#ifndef FORCE32
           if((i_is32>>i_regmap[hr])&1) {
             if(value!=-1&&value!=0) emit_sarimm(HOST_TEMPREG,31,HOST_TEMPREG);
             emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
           }
+#endif
         }
       }
     }
@@ -2466,7 +2468,7 @@ emit_extjump2(int addr, int target, int linker)
   assert((ptr[3]&0x0e)==0xa);
   emit_loadlp(target,0);
   emit_loadlp(addr,1);
-  assert(addr>=0x7000000&&addr<0x7FFFFFF);
+  assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
   //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
 //DEBUG >
 #ifdef DEBUG_CYCLE_COUNT
@@ -2522,8 +2524,11 @@ do_readstub(int n)
     ftable=(int)readmemh;
   if(type==LOADW_STUB)
     ftable=(int)readmem;
+#ifndef FORCE32
   if(type==LOADD_STUB)
     ftable=(int)readmemd;
+#endif
+  assert(ftable!=0);
   emit_writeword(rs,(int)&address);
   //emit_pusha();
   save_regs(reglist);
@@ -2594,8 +2599,11 @@ inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, i
     ftable=(int)readmemh;
   if(type==LOADW_STUB)
     ftable=(int)readmem;
+#ifndef FORCE32
   if(type==LOADD_STUB)
     ftable=(int)readmemd;
+#endif
+  assert(ftable!=0);
   emit_writeword(rs,(int)&address);
   //emit_pusha();
   save_regs(reglist);
@@ -2677,8 +2685,11 @@ do_writestub(int n)
     ftable=(int)writememh;
   if(type==STOREW_STUB)
     ftable=(int)writemem;
+#ifndef FORCE32
   if(type==STORED_STUB)
     ftable=(int)writememd;
+#endif
+  assert(ftable!=0);
   emit_writeword(rs,(int)&address);
   //emit_shrimm(rs,16,rs);
   //emit_movmem_indexedx4(ftable,rs,rs);
@@ -2748,8 +2759,11 @@ inline_writestub(int type, int i, u_int addr, signed char regmap[], int target,
     ftable=(int)writememh;
   if(type==STOREW_STUB)
     ftable=(int)writemem;
+#ifndef FORCE32
   if(type==STORED_STUB)
     ftable=(int)writememd;
+#endif
+  assert(ftable!=0);
   emit_writeword(rs,(int)&address);
   //emit_shrimm(rs,16,rs);
   //emit_movmem_indexedx4(ftable,rs,rs);
@@ -3160,7 +3174,12 @@ void loadlr_assemble_arm(int i,struct regstat *i_regs)
       else
         inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
       emit_andimm(temp,24,temp);
-      if (opcode[i]==0x26) emit_xorimm(temp,24,temp); // LWR
+#ifdef BIG_ENDIAN_MIPS
+      if (opcode[i]==0x26) // LWR
+#else
+      if (opcode[i]==0x22) // LWL
+#endif
+        emit_xorimm(temp,24,temp);
       emit_movimm(-1,HOST_TEMPREG);
       if (opcode[i]==0x26) {
         emit_shr(temp2,temp,temp2);
@@ -3173,6 +3192,7 @@ void loadlr_assemble_arm(int i,struct regstat *i_regs)
       //emit_storereg(rt1[i],tl); // DEBUG
     }
     if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
+      // FIXME: little endian
       int temp2h=get_reg(i_regs->regmap,FTEMP|64);
       if(!c||memtarget) {
         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
@@ -3222,12 +3242,11 @@ void cop0_assemble(int i,struct regstat *i_regs)
     char copr=(source[i]>>11)&0x1f;
     //assert(t>=0); // Why does this happen?  OOT is weird
     if(t>=0) {
-#ifdef MUPEN64 /// FIXME
+#ifdef MUPEN64
       emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
       emit_movimm((source[i]>>11)&0x1f,1);
       emit_writeword(0,(int)&PC);
       emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
-#endif
       if(copr==9) {
         emit_readword((int)&last_count,ECX);
         emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
@@ -3237,6 +3256,9 @@ void cop0_assemble(int i,struct regstat *i_regs)
       }
       emit_call((int)MFC0);
       emit_readword((int)&readmem_dword,t);
+#else
+      emit_readword((int)&reg_cop0+copr*4,t);
+#endif
     }
   }
   else if(opcode2[i]==4) // MTC0
@@ -3252,7 +3274,11 @@ void cop0_assemble(int i,struct regstat *i_regs)
     emit_writeword(0,(int)&PC);
     emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
 #endif
-    if(copr==9||copr==11||copr==12) {
+#ifdef PCSX
+    emit_movimm(source[i],0);
+    emit_writeword(0,(int)&psxRegs.code);
+#endif
+    if(copr==9||copr==11||copr==12||copr==13) {
       emit_readword((int)&last_count,ECX);
       emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
       emit_add(HOST_CCREG,ECX,HOST_CCREG);
@@ -3263,7 +3289,7 @@ void cop0_assemble(int i,struct regstat *i_regs)
     // so needs a special case to handle a pending interrupt.
     // The interrupt must be taken immediately, because a subsequent
     // instruction might disable interrupts again.
-    if(copr==12&&!is_delayslot) {
+    if(copr==12||copr==13) {
       emit_movimm(start+i*4+4,0);
       emit_movimm(0,1);
       emit_writeword(0,(int)&pcaddr);
@@ -3272,7 +3298,7 @@ void cop0_assemble(int i,struct regstat *i_regs)
     //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
     //else
     emit_call((int)MTC0);
-    if(copr==9||copr==11||copr==12) {
+    if(copr==9||copr==11||copr==12||copr==13) {
       emit_readword((int)&Count,HOST_CCREG);
       emit_readword((int)&next_interupt,ECX);
       emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
@@ -3280,14 +3306,14 @@ void cop0_assemble(int i,struct regstat *i_regs)
       emit_writeword(ECX,(int)&last_count);
       emit_storereg(CCREG,HOST_CCREG);
     }
-    if(copr==12) {
+    if(copr==12||copr==13) {
       assert(!is_delayslot);
       emit_readword((int)&pending_exception,14);
     }
     emit_loadreg(rs1[i],s);
     if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
       emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
-    if(copr==12) {
+    if(copr==12||copr==13) {
       emit_test(14,14);
       emit_jne((int)&do_interrupt);
     }
@@ -4288,6 +4314,7 @@ void do_miniht_insert(u_int return_address,int rt,int temp) {
 // as a 64-bit value later.
 void wb_sx(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32_pre,uint64_t is32,uint64_t u,uint64_t uu)
 {
+#ifndef FORCE32
   if(is32_pre==is32) return;
   int hr,reg;
   for(hr=0;hr<HOST_REGS;hr++) {
@@ -4304,6 +4331,7 @@ void wb_sx(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32_pr
       //}
     }
   }
+#endif
 }
 
 void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)