X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fassem_arm.c;h=55eef842a51c00325f2fc9b8847c2d2b5eb73538;hp=ed89bb05afb786c745dfee6aa9f623baaa0e8bcc;hb=20d507ba0e7695190b32b3a06d8024e3ab81d158;hpb=535d208a8473e9255919b1e5bfe0b5aa88f6992a diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c index ed89bb05..55eef842 100644 --- a/libpcsxcore/new_dynarec/assem_arm.c +++ b/libpcsxcore/new_dynarec/assem_arm.c @@ -1,6 +1,6 @@ /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Mupen64plus - assem_arm.c * - * Copyright (C) 2009-2010 Ari64 * + * Copyright (C) 2009-2011 Ari64 * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -66,8 +66,41 @@ const u_int jump_vaddr_reg[16] = { 0, 0}; +void invalidate_addr_r0(); +void invalidate_addr_r1(); +void invalidate_addr_r2(); +void invalidate_addr_r3(); +void invalidate_addr_r4(); +void invalidate_addr_r5(); +void invalidate_addr_r6(); +void invalidate_addr_r7(); +void invalidate_addr_r8(); +void invalidate_addr_r9(); +void invalidate_addr_r10(); +void invalidate_addr_r12(); + +const u_int invalidate_addr_reg[16] = { + (int)invalidate_addr_r0, + (int)invalidate_addr_r1, + (int)invalidate_addr_r2, + (int)invalidate_addr_r3, + (int)invalidate_addr_r4, + (int)invalidate_addr_r5, + (int)invalidate_addr_r6, + (int)invalidate_addr_r7, + (int)invalidate_addr_r8, + (int)invalidate_addr_r9, + (int)invalidate_addr_r10, + 0, + (int)invalidate_addr_r12, + 0, + 0, + 0}; + #include "fpu.h" +unsigned int needs_clear_cache[1<<(TARGET_SIZE_2-17)]; + /* Linker */ void set_jump_target(int addr,u_int target) @@ -812,7 +845,8 @@ u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift) } u_int genimm(u_int imm,u_int *encoded) { - if(imm==0) {*encoded=0;return 1;} + *encoded=0; + if(imm==0) return 1; int i=32; while(i>0) { @@ -969,7 +1003,8 @@ void emit_loadreg(int r, int hr) #ifdef FORCE32 if(r&64) { printf("64bit load in 32bit mode!\n"); - exit(1); + assert(0); + return; } #endif if((r&63)==0) @@ -993,7 +1028,8 @@ void emit_storereg(int r, int hr) #ifdef FORCE32 if(r&64) { printf("64bit store in 32bit mode!\n"); - exit(1); + assert(0); + return; } #endif int addr=((int)reg)+((r&63)<>4); @@ -2193,6 +2229,13 @@ void emit_addsr12(int rs1,int rs2,int rt) output_w32(0xe0800620|rd_rn_rm(rt,rs1,rs2)); } +void emit_callne(int a) +{ + assem_debug("blne %x\n",a); + u_int offset=genjmp(a); + output_w32(0x1b000000|offset); +} + // Used to preload hash table entries void emit_prefetch(void *addr) { @@ -2562,6 +2605,10 @@ emit_extjump_ds(int addr, int target) emit_extjump2(addr, target, (int)dyna_linker_ds); } +#ifdef PCSX +#include "pcsxmem_inline.c" +#endif + do_readstub(int n) { assem_debug("do_readstub %x\n",start+stubs[n][3]*4); @@ -2602,12 +2649,14 @@ do_readstub(int n) emit_writeword(rs,(int)&address); //emit_pusha(); save_regs(reglist); +#ifndef PCSX ds=i_regs!=®s[i]; int real_rs=(itype[i]==LOADLR)?-1:get_reg(i_regmap,rs1[i]); u_int cmask=ds?-1:(0x100f|~i_regs->wasconst); if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<>rs1[i])&1)<<1)+ds,3); +#endif //emit_readword((int)&last_count,temp); //emit_add(cc,temp,cc); //emit_writeword(cc,(int)&Count); @@ -2623,6 +2674,7 @@ do_readstub(int n) emit_call((int)&indirect_jump_indexed); //emit_callreg(rs); //emit_readword_dualindexedx4(rs,HOST_TEMPREG,15); +#ifndef PCSX // We really shouldn't need to update the count here, // but not doing so causes random crashes... emit_readword((int)&Count,HOST_TEMPREG); @@ -2633,6 +2685,7 @@ do_readstub(int n) if(cc<0) { emit_storereg(CCREG,HOST_TEMPREG); } +#endif //emit_popa(); restore_regs(reglist); //if((cc=get_reg(regmap,CCREG))>=0) { @@ -2677,6 +2730,10 @@ inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, i ftable=(int)readmemd; #endif assert(ftable!=0); +#ifdef PCSX + if(pcsx_direct_read(type,addr,target?rs:-1,rt)) + return; +#endif if(target==0) emit_movimm(addr,rs); emit_writeword(rs,(int)&address); @@ -2691,15 +2748,18 @@ inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, i emit_movimm(((u_int *)ftable)[addr>>16],0); //emit_readword((int)&last_count,12); emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2); +#ifndef PCSX if((signed int)addr>=(signed int)0xC0000000) { // Pagefault address int ds=regmap!=regs[i].regmap; emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3); } +#endif //emit_add(12,2,2); //emit_writeword(2,(int)&Count); //emit_call(((u_int *)ftable)[addr>>16]); emit_call((int)&indirect_jump); +#ifndef PCSX // We really shouldn't need to update the count here, // but not doing so causes random crashes... emit_readword((int)&Count,HOST_TEMPREG); @@ -2710,6 +2770,7 @@ inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, i if(cc<0) { emit_storereg(CCREG,HOST_TEMPREG); } +#endif //emit_popa(); restore_regs(reglist); if(rt>=0) { @@ -2786,12 +2847,14 @@ do_writestub(int n) } //emit_pusha(); save_regs(reglist); +#ifndef PCSX ds=i_regs!=®s[i]; int real_rs=get_reg(i_regmap,rs1[i]); u_int cmask=ds?-1:(0x100f|~i_regs->wasconst); if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<>rs1[i])&1)<<1)+ds,3); +#endif //emit_readword((int)&last_count,temp); //emit_addimm(cc,2*stubs[n][5]+2,cc); //emit_add(cc,temp,cc); @@ -2829,6 +2894,10 @@ inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int rt=get_reg(regmap,target); assert(rs>=0); assert(rt>=0); +#ifdef PCSX + if(pcsx_direct_write(type,addr,rs,rt,regmap)) + return; +#endif int ftable=0; if(type==STOREB_STUB) ftable=(int)writememb; @@ -2869,11 +2938,13 @@ inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, emit_movimm(((u_int *)ftable)[addr>>16],0); //emit_readword((int)&last_count,12); emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2); +#ifndef PCSX if((signed int)addr>=(signed int)0xC0000000) { // Pagefault address int ds=regmap!=regs[i].regmap; emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3); } +#endif //emit_add(12,2,2); //emit_writeword(2,(int)&Count); //emit_call(((u_int *)ftable)[addr>>16]); @@ -2915,12 +2986,14 @@ do_unalignedwritestub(int n) emit_writeword(temp2,(int)&address); save_regs(reglist); +#ifndef PCSX ds=i_regs!=®s[i]; real_rs=get_reg(i_regmap,rs1[i]); u_int cmask=ds?-1:(0x100f|~i_regs->wasconst); if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<>rs1[i])&1)<<1)+ds,3); // XXX: can be rm'd? +#ifndef PCSX + // pagefault address + emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3); +#endif emit_call((int)&indirect_jump_indexed); restore_regs(reglist); @@ -3255,7 +3331,7 @@ void loadlr_assemble_arm(int i,struct regstat *i_regs) int s,th,tl,temp,temp2,addr,map=-1; int offset; int jaddr=0; - int memtarget,c=0; + int memtarget=0,c=0; u_int hr,reglist=0; th=get_reg(i_regs->regmap,rt1[i]|64); tl=get_reg(i_regs->regmap,rt1[i]); @@ -3273,8 +3349,10 @@ void loadlr_assemble_arm(int i,struct regstat *i_regs) else addr=s; if(s>=0) { c=(i_regs->wasconst>>s)&1; - memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; - if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1; + if(c) { + memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; + if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1; + } } if(!using_tlb) { if(!c) { @@ -3690,10 +3768,11 @@ void c2op_assemble(int i,struct regstat *i_regs) if (gte_handlers[c2op]!=NULL) { int cc=get_reg(i_regs->regmap,CCREG); - emit_movimm(source[i],temp); // opcode + emit_movimm(source[i],1); // opcode if (cc>=0&>e_cycletab[c2op]) - emit_addimm(cc,gte_cycletab[c2op]/2,cc); // XXX: cound just adjust ccadj? - emit_writeword(temp,(int)&psxRegs.code); + emit_addimm(cc,gte_cycletab[c2op]/2,cc); // XXX: could just adjust ccadj? + emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0); // cop2 regs + emit_writeword(1,(int)&psxRegs.code); emit_call((int)gte_handlers[c2op]); } @@ -4784,6 +4863,38 @@ void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint #define wb_invalidate wb_invalidate_arm */ +// Clearing the cache is rather slow on ARM Linux, so mark the areas +// that need to be cleared, and then only clear these areas once. +void do_clear_cache() +{ + int i,j; + for (i=0;i<(1<<(TARGET_SIZE_2-17));i++) + { + u_int bitmap=needs_clear_cache[i]; + if(bitmap) { + u_int start,end; + for(j=0;j<32;j++) + { + if(bitmap&(1<