X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fassem_arm.c;h=b6b856a698f0de6997d879f23a5692d92b927565;hp=cd3429f95037e1c1ea61829b30beafb32a1308af;hb=f18c0f46b9aabbbb7fc71cdbd308b6523adcb759;hpb=5bf843dc7ca2eb95430607b49c0dde6798950317 diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c index cd3429f9..b6b856a6 100644 --- a/libpcsxcore/new_dynarec/assem_arm.c +++ b/libpcsxcore/new_dynarec/assem_arm.c @@ -142,7 +142,7 @@ add_literal(int addr,int val) literalcount++; } -void kill_pointer(void *stub) +void *kill_pointer(void *stub) { int *ptr=(int *)(stub+4); assert((*ptr&0x0ff00000)==0x05900000); @@ -150,6 +150,7 @@ void kill_pointer(void *stub) int **l_ptr=(void *)ptr+offset+8; int *i_ptr=*l_ptr; set_jump_target((int)i_ptr,(int)stub); + return i_ptr; } int get_pointer(void *stub) @@ -1002,6 +1003,15 @@ void emit_or_and_set_flags(int rs1,int rs2,int rt) output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2)); } +void emit_orrshr_imm(u_int rs,u_int imm,u_int rt) +{ + assert(rs<16); + assert(rt<16); + assert(imm<32); + assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm); + output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7)); +} + void emit_xor(u_int rs1,u_int rs2,u_int rt) { assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]); @@ -1937,7 +1947,7 @@ void emit_writebyte(int rt, int addr) { u_int offset = addr-(u_int)&dynarec_local; assert(offset<4096); - assem_debug("str %s,fp+%d\n",regname[rt],offset); + assem_debug("strb %s,fp+%d\n",regname[rt],offset); output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset); } void emit_writeword_imm(int imm, int addr) @@ -2553,14 +2563,11 @@ do_readstub(int n) rth=get_reg(i_regmap,rt1[i]|64); rt=get_reg(i_regmap,rt1[i]); } -#ifdef PCSX - if(rt<0) - // assume forced dummy read - rt=get_reg(i_regmap,-1); -#endif assert(rs>=0); - assert(rt>=0); if(addr<0) addr=rt; + if(addr<0) + // assume dummy read, no alloced reg + addr=get_reg(i_regmap,-1); assert(addr>=0); int ftable=0; if(type==LOADB_STUB||type==LOADBU_STUB) @@ -2613,19 +2620,22 @@ do_readstub(int n) //if((cc=get_reg(regmap,CCREG))>=0) { // emit_loadreg(CCREG,cc); //} - if(type==LOADB_STUB) - emit_movsbl((int)&readmem_dword,rt); - if(type==LOADBU_STUB) - emit_movzbl((int)&readmem_dword,rt); - if(type==LOADH_STUB) - emit_movswl((int)&readmem_dword,rt); - if(type==LOADHU_STUB) - emit_movzwl((int)&readmem_dword,rt); - if(type==LOADW_STUB) - emit_readword((int)&readmem_dword,rt); - if(type==LOADD_STUB) { - emit_readword((int)&readmem_dword,rt); - if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth); + if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) { + assert(rt>=0); + if(type==LOADB_STUB) + emit_movsbl((int)&readmem_dword,rt); + if(type==LOADBU_STUB) + emit_movzbl((int)&readmem_dword,rt); + if(type==LOADH_STUB) + emit_movswl((int)&readmem_dword,rt); + if(type==LOADHU_STUB) + emit_movzwl((int)&readmem_dword,rt); + if(type==LOADW_STUB) + emit_readword((int)&readmem_dword,rt); + if(type==LOADD_STUB) { + emit_readword((int)&readmem_dword,rt); + if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth); + } } emit_jmp(stubs[n][2]); // return address } @@ -2860,8 +2870,81 @@ inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, do_unalignedwritestub(int n) { + assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4); + literal_pool(256); set_jump_target(stubs[n][1],(int)out); - output_w32(0xef000000); + + int i=stubs[n][3]; + struct regstat *i_regs=(struct regstat *)stubs[n][4]; + int addr=stubs[n][5]; + u_int reglist=stubs[n][7]; + signed char *i_regmap=i_regs->regmap; + int temp2=get_reg(i_regmap,FTEMP); + int rt; + int ds, real_rs; + rt=get_reg(i_regmap,rs2[i]); + assert(rt>=0); + assert(addr>=0); + assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented + reglist|=(1<wasconst); + if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<>rs1[i])&1)<<1)+ds,3); // XXX: can be rm'd? + emit_call((int)&indirect_jump_indexed); + restore_regs(reglist); + + emit_readword((int)&readmem_dword,temp2); + int temp=addr; //hmh + emit_shlimm(addr,3,temp); + emit_andimm(temp,24,temp); +#ifdef BIG_ENDIAN_MIPS + if (opcode[i]==0x2e) // SWR +#else + if (opcode[i]==0x2a) // SWL +#endif + emit_xorimm(temp,24,temp); + emit_movimm(-1,HOST_TEMPREG); + if (opcode[i]==0x2a) { // SWL + emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2); + emit_orrshr(rt,temp,temp2); + }else{ + emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2); + emit_orrshl(rt,temp,temp2); + } + emit_readword((int)&address,addr); + emit_writeword(temp2,(int)&word); + //save_regs(reglist); // don't need to, no state changes + emit_shrimm(addr,16,1); + emit_movimm((u_int)writemem,0); + //emit_call((int)&indirect_jump_indexed); + emit_mov(15,14); + emit_readword_dualindexedx4(0,1,15); + emit_readword((int)&Count,HOST_TEMPREG); + emit_readword((int)&next_interupt,2); + emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG); + emit_writeword(2,(int)&last_count); + emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc); + if(cc<0) { + emit_storereg(CCREG,HOST_TEMPREG); + } + restore_regs(reglist); emit_jmp(stubs[n][2]); // return address } @@ -2885,15 +2968,19 @@ do_invstub(int n) int do_dirty_stub(int i) { assem_debug("do_dirty_stub %x\n",start+i*4); + u_int addr=(int)start<(int)0xC0000000?(u_int)source:(u_int)start; + #ifdef PCSX + addr=(u_int)source; + #endif // Careful about the code output here, verify_dirty needs to parse it. #ifdef ARMv5_ONLY - emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1); + emit_loadlp(addr,1); emit_loadlp((int)copy,2); emit_loadlp(slen*4,3); #else - emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1); + emit_movw(addr&0x0000FFFF,1); emit_movw(((u_int)copy)&0x0000FFFF,2); - emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1); + emit_movt(addr&0xFFFF0000,1); emit_movt(((u_int)copy)&0xFFFF0000,2); emit_movw(slen*4,3); #endif @@ -3164,7 +3251,7 @@ void loadlr_assemble_arm(int i,struct regstat *i_regs) else addr=s; if(s>=0) { c=(i_regs->wasconst>>s)&1; - memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000; + memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1; } if(tl>=0) { @@ -3178,7 +3265,7 @@ void loadlr_assemble_arm(int i,struct regstat *i_regs) }else{ emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR } - emit_cmpimm(addr,0x800000); + emit_cmpimm(addr,RAM_SIZE); jaddr=(int)out; emit_jno(0); } @@ -3385,6 +3472,16 @@ void cop0_assemble(int i,struct regstat *i_regs) if((source[i]&0x3f)==0x08) // TLBP emit_call((int)TLBP); #endif +#ifdef PCSX + if((source[i]&0x3f)==0x10) // RFE + { + emit_readword((int)&Status,0); + emit_andimm(0,0x3c,1); + emit_andimm(0,~0xf,0); + emit_orrshr_imm(1,2,0); + emit_writeword(0,(int)&Status); + } +#else if((source[i]&0x3f)==0x18) // ERET { int count=ccadj[i]; @@ -3392,6 +3489,7 @@ void cop0_assemble(int i,struct regstat *i_regs) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*count,HOST_CCREG); // TODO: Should there be an extra cycle here? emit_jmp((int)jump_eret); } +#endif } }