X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fassem_arm.h;h=7ed8caff4f949bcde015ae37efe4d8cda4a36c22;hp=93066a24fa0a071a271dbf6973b8a180e3a61c19;hb=bdeade4633d41d76e0c22b3810241bbf7cb5a8a3;hpb=57871462a0b157066bbc4a763c59b61085436609

diff --git a/libpcsxcore/new_dynarec/assem_arm.h b/libpcsxcore/new_dynarec/assem_arm.h
index 93066a24..7ed8caff 100644
--- a/libpcsxcore/new_dynarec/assem_arm.h
+++ b/libpcsxcore/new_dynarec/assem_arm.h
@@ -8,6 +8,29 @@
 #define CORTEX_A8_BRANCH_PREDICTION_HACK 1
 #define USE_MINI_HT 1
 //#define REG_PREFETCH 1
+#define HAVE_CONDITIONAL_CALL 1
+#define DISABLE_TLB 1
+//#define MUPEN64
+#define FORCE32 1
+#define DISABLE_COP1 1
+#define PCSX 1
+#define RAM_SIZE 0x200000
+
+#ifndef __ARM_ARCH_7A__
+#define ARMv5_ONLY
+//#undef CORTEX_A8_BRANCH_PREDICTION_HACK
+//#undef USE_MINI_HT
+#endif
+
+#ifndef __ANDROID__
+#define BASE_ADDR_FIXED 1
+#endif
+
+#ifdef FORCE32
+#define REG_SHIFT 2
+#else
+#define REG_SHIFT 3
+#endif
 
 /* ARM calling convention:
    r0-r3, r12: caller-save
@@ -35,8 +58,16 @@
 
 extern char *invc_ptr;
 
-#define BASE_ADDR 0x7000000 // Code generator target address
 #define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
 
+// Code generator target address
+#ifdef BASE_ADDR_FIXED
+// "round" address helpful for debug
+#define BASE_ADDR 0x1000000
+#else
+extern char translation_cache[1 << TARGET_SIZE_2];
+#define BASE_ADDR translation_cache
+#endif
+
 // This is defined in linkage_arm.s, but gcc -O3 likes this better
 #define rdram ((unsigned int *)0x80000000)