X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fassem_arm.h;h=9b3a1e10b837bd66b67d047ccf03d38c66e9c23e;hp=7ed8caff4f949bcde015ae37efe4d8cda4a36c22;hb=81dbbf4cbb16fc6c9a82a5b91e102c8005c5726a;hpb=bdeade4633d41d76e0c22b3810241bbf7cb5a8a3

diff --git a/libpcsxcore/new_dynarec/assem_arm.h b/libpcsxcore/new_dynarec/assem_arm.h
index 7ed8caff..9b3a1e10 100644
--- a/libpcsxcore/new_dynarec/assem_arm.h
+++ b/libpcsxcore/new_dynarec/assem_arm.h
@@ -5,42 +5,12 @@
 
 #define HOST_IMM8 1
 #define HAVE_CMOV_IMM 1
-#define CORTEX_A8_BRANCH_PREDICTION_HACK 1
-#define USE_MINI_HT 1
-//#define REG_PREFETCH 1
 #define HAVE_CONDITIONAL_CALL 1
-#define DISABLE_TLB 1
-//#define MUPEN64
-#define FORCE32 1
-#define DISABLE_COP1 1
-#define PCSX 1
-#define RAM_SIZE 0x200000
-
-#ifndef __ARM_ARCH_7A__
-#define ARMv5_ONLY
-//#undef CORTEX_A8_BRANCH_PREDICTION_HACK
-//#undef USE_MINI_HT
-#endif
-
-#ifndef __ANDROID__
-#define BASE_ADDR_FIXED 1
-#endif
-
-#ifdef FORCE32
-#define REG_SHIFT 2
-#else
-#define REG_SHIFT 3
-#endif
 
 /* ARM calling convention:
    r0-r3, r12: caller-save
    r4-r11: callee-save */
 
-#define ARG1_REG 0
-#define ARG2_REG 1
-#define ARG3_REG 2
-#define ARG4_REG 3
-
 /* GCC register naming convention:
    r10 = sl (base)
    r11 = fp (frame pointer)
@@ -60,14 +30,8 @@ extern char *invc_ptr;
 
 #define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
 
-// Code generator target address
-#ifdef BASE_ADDR_FIXED
-// "round" address helpful for debug
-#define BASE_ADDR 0x1000000
-#else
-extern char translation_cache[1 << TARGET_SIZE_2];
-#define BASE_ADDR translation_cache
-#endif
+struct tramp_insns
+{
+  u_int ldrpc;
+};
 
-// This is defined in linkage_arm.s, but gcc -O3 likes this better
-#define rdram ((unsigned int *)0x80000000)