X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fassem_arm.h;h=bbaf5b9e952eb387da6cebdbc92c7f8447faed75;hp=f9c9b84c71dfec263c7aad73393eceb3f5636c24;hb=7c3a5182da4384e21a6ace037583fae399de5a02;hpb=7139f3c8070e9aa14fd36c2451d7f10079caa37a

diff --git a/libpcsxcore/new_dynarec/assem_arm.h b/libpcsxcore/new_dynarec/assem_arm.h
index f9c9b84c..bbaf5b9e 100644
--- a/libpcsxcore/new_dynarec/assem_arm.h
+++ b/libpcsxcore/new_dynarec/assem_arm.h
@@ -5,30 +5,13 @@
 
 #define HOST_IMM8 1
 #define HAVE_CMOV_IMM 1
-#define CORTEX_A8_BRANCH_PREDICTION_HACK 1
-#define USE_MINI_HT 1
-//#define REG_PREFETCH 1
-#define DISABLE_TLB 1
-//#define MUPEN64
-#define FORCE32 1
-#define DISABLE_COP1 1
-#define PCSX 1
-
-#ifdef FORCE32
-#define REG_SHIFT 2
-#else
-#define REG_SHIFT 3
-#endif
+#define HAVE_CONDITIONAL_CALL 1
+#define RAM_SIZE 0x200000
 
 /* ARM calling convention:
    r0-r3, r12: caller-save
    r4-r11: callee-save */
 
-#define ARG1_REG 0
-#define ARG2_REG 1
-#define ARG3_REG 2
-#define ARG4_REG 3
-
 /* GCC register naming convention:
    r10 = sl (base)
    r11 = fp (frame pointer)
@@ -46,8 +29,20 @@
 
 extern char *invc_ptr;
 
-#define BASE_ADDR 0x1000000 // Code generator target address
 #define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
 
-// This is defined in linkage_arm.s, but gcc -O3 likes this better
-#define rdram ((unsigned int *)0x80000000)
+// Code generator target address
+#if   defined(BASE_ADDR_FIXED)
+  // "round" address helpful for debug
+  // this produces best code, but not many platforms allow it,
+  // only use if you are sure this range is always free
+  #define BASE_ADDR_ 0x1000000
+  #define translation_cache (u_char *)BASE_ADDR_
+#elif defined(BASE_ADDR_DYNAMIC)
+  // for platforms that can't just use .bss buffer, like vita
+  // otherwise better to use the next option for closer branches
+  extern u_char *translation_cache;
+#else
+  // using a static buffer in .bss
+  extern u_char translation_cache[1 << TARGET_SIZE_2];
+#endif