X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Femu_if.h;h=90781505677af691e588e592f5090382ca9c73d7;hp=f5e4b5531eeb358ef6cea8f57f69765d28ef773b;hb=b1be1eeee94d3547c20719acfa6b0082404897f1;hpb=f95a77f74f9608f9c63780fee20fcc5255042ac3

diff --git a/libpcsxcore/new_dynarec/emu_if.h b/libpcsxcore/new_dynarec/emu_if.h
index f5e4b553..90781505 100644
--- a/libpcsxcore/new_dynarec/emu_if.h
+++ b/libpcsxcore/new_dynarec/emu_if.h
@@ -1,3 +1,4 @@
+#include "new_dynarec.h"
 #include "../r3000a.h"
 
 extern char invalid_code[0x100000];
@@ -13,35 +14,58 @@ extern int reg[];
 extern int hi, lo;
 
 /* same as psxRegs.CP0.n.* */
+extern int reg_cop0[];
 #define Status   psxRegs.CP0.n.Status
 #define Cause    psxRegs.CP0.n.Cause
 #define EPC      psxRegs.CP0.n.EPC
 #define BadVAddr psxRegs.CP0.n.BadVAddr
 #define Context  psxRegs.CP0.n.Context
 #define EntryHi  psxRegs.CP0.n.EntryHi
-#define Count    psxRegs.CP0.n.Count
+#define Count    psxRegs.cycle // psxRegs.CP0.n.Count
+
+/* COP2/GTE */
+extern int reg_cop2d[], reg_cop2c[];
+extern void *gte_handlers[64];
+extern void *gte_handlers_nf[64];
+extern const char *gte_regnames[64];
+extern const char gte_cycletab[64];
 
 /* dummy */
 extern int FCR0, FCR31;
 
 /* mem */
-extern void (*readmem[0x10000])();
-extern void (*readmemb[0x10000])();
-extern void (*readmemh[0x10000])();
-extern void (*writemem[0x10000])();
-extern void (*writememb[0x10000])();
-extern void (*writememh[0x10000])();
+extern void *mem_rtab;
+extern void *mem_wtab;
+
+void jump_handler_read8(u32 addr, u32 *table, u32 cycles);
+void jump_handler_read16(u32 addr, u32 *table, u32 cycles);
+void jump_handler_read32(u32 addr, u32 *table, u32 cycles);
+void jump_handler_write8(u32 addr, u32 data, u32 cycles, u32 *table);
+void jump_handler_write16(u32 addr, u32 data, u32 cycles, u32 *table);
+void jump_handler_write32(u32 addr, u32 data, u32 cycles, u32 *table);
+void jump_handler_write_h(u32 addr, u32 data, u32 cycles, void *handler);
+void jump_handle_swl(u32 addr, u32 data, u32 cycles);
+void jump_handle_swr(u32 addr, u32 data, u32 cycles);
+void rcnt0_read_count_m0(u32 addr, u32, u32 cycles);
+void rcnt0_read_count_m1(u32 addr, u32, u32 cycles);
+void rcnt1_read_count_m0(u32 addr, u32, u32 cycles);
+void rcnt1_read_count_m1(u32 addr, u32, u32 cycles);
+void rcnt2_read_count_m0(u32 addr, u32, u32 cycles);
+void rcnt2_read_count_m1(u32 addr, u32, u32 cycles);
 
 extern unsigned int address;
-extern unsigned int readmem_word; /* same as readmem_dword */
-extern unsigned int word;	/* write */
-extern unsigned short hword;
-extern unsigned char byte;
+extern void *psxH_ptr;
+
+// same as invalid_code, just a region for ram write checks (inclusive)
+extern u32 inv_code_start, inv_code_end;
 
-/* cycles */
+/* cycles/irqs */
 extern unsigned int next_interupt;
+extern int pending_exception;
 
 /* called by drc */
-void MFC0();
-void MTC0();
+void pcsx_mtc0(u32 reg, u32 val);
+void pcsx_mtc0_ds(u32 reg, u32 val);
 
+/* misc */
+extern void (*psxHLEt[])();