X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Flinkage_arm.s;h=b22d491fe2c05547011e3d71aa3db6b92fcd6975;hp=8744608f71d93dbb58f137163dd974e92899b67f;hb=eba830cd5dc35bc900ea60d8c06ee582178280a4;hpb=018f9fea66b5ec11e4e7037d34f289e357b4873f diff --git a/libpcsxcore/new_dynarec/linkage_arm.s b/libpcsxcore/new_dynarec/linkage_arm.s index 8744608f..b22d491f 100644 --- a/libpcsxcore/new_dynarec/linkage_arm.s +++ b/libpcsxcore/new_dynarec/linkage_arm.s @@ -1,6 +1,6 @@ /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * linkage_arm.s for PCSX * - * Copyright (C) 2009-2010 Ari64 * + * Copyright (C) 2009-2011 Ari64 * * Copyright (C) 2010-2011 Gražvydas "notaz" Ignotas * * * * This program is free software; you can redistribute it and/or modify * @@ -203,6 +203,15 @@ memory_map = restore_candidate + 512 .size memory_map, 4194304 dynarec_local_end = memory_map + 4194304 +.macro load_var_adr reg var +.if HAVE_ARMV7 + movw \reg, #:lower16:\var + movt \reg, #:upper16:\var +.else + ldr \reg, =\var +.endif +.endm + .text .align 2 .global dyna_linker @@ -210,14 +219,16 @@ dynarec_local_end = memory_map + 4194304 dyna_linker: /* r0 = virtual target address */ /* r1 = instruction to patch */ - mov r12, r0 - mov r6, #4096 - mov r2, #0x80000 ldr r3, .jiptr + /* get_page */ + lsr r2, r0, #12 + mov r6, #4096 + bic r2, r2, #0xe0000 sub r6, r6, #1 + cmp r2, #0x1000 ldr r7, [r1] - eor r2, r2, r12, lsr #12 - and r6, r6, r12, lsr #12 + biclt r2, #0x0e00 + and r6, r6, r2 cmp r2, #2048 add r12, r7, #2 orrcs r2, r6, #2048 @@ -328,14 +339,16 @@ exec_pagefault: dyna_linker_ds: /* r0 = virtual target address */ /* r1 = instruction to patch */ - mov r12, r0 - mov r6, #4096 - mov r2, #0x80000 ldr r3, .jiptr + /* get_page */ + lsr r2, r0, #12 + mov r6, #4096 + bic r2, r2, #0xe0000 sub r6, r6, #1 + cmp r2, #0x1000 ldr r7, [r1] - eor r2, r2, r12, lsr #12 - and r6, r6, r12, lsr #12 + biclt r2, #0x0e00 + and r6, r6, r2 cmp r2, #2048 add r12, r7, #2 orrcs r2, r6, #2048 @@ -747,18 +760,116 @@ indirect_jump: .size indirect_jump, .-indirect_jump .size indirect_jump_indexed, .-indirect_jump_indexed + .align 2 + .global invalidate_addr_r0 + .type invalidate_addr_r0, %function +invalidate_addr_r0: + stmia fp, {r0, r1, r2, r3, r12, lr} + lsr r0, r0, #12 + b invalidate_addr_call + .size invalidate_addr_r0, .-invalidate_addr_r0 + .align 2 + .global invalidate_addr_r1 + .type invalidate_addr_r1, %function +invalidate_addr_r1: + stmia fp, {r0, r1, r2, r3, r12, lr} + lsr r0, r1, #12 + b invalidate_addr_call + .size invalidate_addr_r1, .-invalidate_addr_r1 + .align 2 + .global invalidate_addr_r2 + .type invalidate_addr_r2, %function +invalidate_addr_r2: + stmia fp, {r0, r1, r2, r3, r12, lr} + lsr r0, r2, #12 + b invalidate_addr_call + .size invalidate_addr_r2, .-invalidate_addr_r2 + .align 2 + .global invalidate_addr_r3 + .type invalidate_addr_r3, %function +invalidate_addr_r3: + stmia fp, {r0, r1, r2, r3, r12, lr} + lsr r0, r3, #12 + b invalidate_addr_call + .size invalidate_addr_r3, .-invalidate_addr_r3 + .align 2 + .global invalidate_addr_r4 + .type invalidate_addr_r4, %function +invalidate_addr_r4: + stmia fp, {r0, r1, r2, r3, r12, lr} + lsr r0, r4, #12 + b invalidate_addr_call + .size invalidate_addr_r4, .-invalidate_addr_r4 + .align 2 + .global invalidate_addr_r5 + .type invalidate_addr_r5, %function +invalidate_addr_r5: + stmia fp, {r0, r1, r2, r3, r12, lr} + lsr r0, r5, #12 + b invalidate_addr_call + .size invalidate_addr_r5, .-invalidate_addr_r5 + .align 2 + .global invalidate_addr_r6 + .type invalidate_addr_r6, %function +invalidate_addr_r6: + stmia fp, {r0, r1, r2, r3, r12, lr} + lsr r0, r6, #12 + b invalidate_addr_call + .size invalidate_addr_r6, .-invalidate_addr_r6 + .align 2 + .global invalidate_addr_r7 + .type invalidate_addr_r7, %function +invalidate_addr_r7: + stmia fp, {r0, r1, r2, r3, r12, lr} + lsr r0, r7, #12 + b invalidate_addr_call + .size invalidate_addr_r7, .-invalidate_addr_r7 + .align 2 + .global invalidate_addr_r8 + .type invalidate_addr_r8, %function +invalidate_addr_r8: + stmia fp, {r0, r1, r2, r3, r12, lr} + lsr r0, r8, #12 + b invalidate_addr_call + .size invalidate_addr_r8, .-invalidate_addr_r8 + .align 2 + .global invalidate_addr_r9 + .type invalidate_addr_r9, %function +invalidate_addr_r9: + stmia fp, {r0, r1, r2, r3, r12, lr} + lsr r0, r9, #12 + b invalidate_addr_call + .size invalidate_addr_r9, .-invalidate_addr_r9 + .align 2 + .global invalidate_addr_r10 + .type invalidate_addr_r10, %function +invalidate_addr_r10: + stmia fp, {r0, r1, r2, r3, r12, lr} + lsr r0, r10, #12 + b invalidate_addr_call + .size invalidate_addr_r10, .-invalidate_addr_r10 + .align 2 + .global invalidate_addr_r12 + .type invalidate_addr_r12, %function +invalidate_addr_r12: + stmia fp, {r0, r1, r2, r3, r12, lr} + lsr r0, r12, #12 + .size invalidate_addr_r12, .-invalidate_addr_r12 + .align 2 + .global invalidate_addr_call + .type invalidate_addr_call, %function +invalidate_addr_call: + bl invalidate_block + ldmia fp, {r0, r1, r2, r3, r12, pc} + .size invalidate_addr_call, .-invalidate_addr_call + .align 2 .global new_dyna_start .type new_dyna_start, %function new_dyna_start: /* ip is stored to conform EABI alignment */ stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr} -.if HAVE_ARMV7 - movw fp, #:lower16:dynarec_local - movt fp, #:upper16:dynarec_local -.else - ldr fp, .dlptr -.endif + load_var_adr fp, dynarec_local ldr r0, [fp, #pcaddr-dynarec_local] bl get_addr_ht ldr r1, [fp, #next_interupt-dynarec_local] @@ -766,8 +877,6 @@ new_dyna_start: str r1, [fp, #last_count-dynarec_local] sub r10, r10, r1 mov pc, r0 -.dlptr: - .word dynarec_local .size new_dyna_start, .-new_dyna_start /* --------------------------------------- */ @@ -785,6 +894,7 @@ new_dyna_start: .global ari_write_ram_mirror8 .global ari_write_ram_mirror16 .global ari_write_ram_mirror32 +.global ari_write_ram_mirror_ro32 .global ari_read_bios8 .global ari_read_bios16 .global ari_read_bios32 @@ -877,6 +987,14 @@ ari_write_ram_mirror16: ari_write_ram_mirror32: ari_write_ram_mirror (3<<11), word, +ari_write_ram_mirror_ro32: + load_var_adr r0, pcsx_ram_is_ro + ldr r0, [r0] + tst r0, r0 + movne pc, lr + nop + b ari_write_ram_mirror32 + .macro ari_read_bios_mirror bic_const op ldr r0, [fp, #address-dynarec_local]