X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fnew_dynarec.c;h=641c673dcda5c1b98e31b8da869033e77ea9a19f;hp=00b23ee0b82ffd9d10a5283fe000a1db893fb772;hb=268690946c1b0883963cdeb85a4278a034bb9b72;hpb=c7abc8640c52f63f655ba38585b37c8548527b63 diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index 00b23ee0..641c673d 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -309,7 +309,14 @@ static void tlb_hacks() static u_int get_page(u_int vaddr) { +#ifndef PCSX u_int page=(vaddr^0x80000000)>>12; +#else + u_int page=vaddr&~0xe0000000; + if (page < 0x1000000) + page &= ~0x0e00000; // RAM mirrors + page>>=12; +#endif #ifndef DISABLE_TLB if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12; #endif @@ -1783,16 +1790,17 @@ void cop1_alloc(struct regstat *current,int i) alloc_reg(current,i,CSREG); // Load status if(opcode2[i]<3) // MFC1/DMFC1/CFC1 { - assert(rt1[i]); - clear_const(current,rt1[i]); - if(opcode2[i]==1) { - alloc_reg64(current,i,rt1[i]); // DMFC1 - current->is32&=~(1LL<is32|=1LL<is32&=~(1LL<is32|=1LL<3) // MTC1/DMTC1/CTC1 @@ -5643,14 +5651,17 @@ void sjump_assemble(int i,struct regstat *i_regs) //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL) //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL) - if(ooo) + if(ooo) { if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) - { - // Write-after-read dependency prevents out of order execution - // First test branch condition, then execute delay slot, then branch - ooo=0; + { + // Write-after-read dependency prevents out of order execution + // First test branch condition, then execute delay slot, then branch + ooo=0; + } + if(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31)) + // BxxZAL $ra is available to delay insn, so do it in order + ooo=0; } - assert(opcode2[i]<0x10||ooo); // FIXME (BxxZALL) if(ooo) { s1l=get_reg(branch_regs[i].regmap,rs1[i]); @@ -5692,8 +5703,6 @@ void sjump_assemble(int i,struct regstat *i_regs) load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG); if(rt1[i]==31) { int rt,return_address; - assert(rt1[i+1]!=31); - assert(rt2[i+1]!=31); rt=get_reg(branch_regs[i].regmap,31); assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); if(rt>=0) { @@ -5837,18 +5846,30 @@ void sjump_assemble(int i,struct regstat *i_regs) // In-order execution (branch first) //printf("IOE\n"); int nottaken=0; + if(rt1[i]==31) { + int rt,return_address; + rt=get_reg(branch_regs[i].regmap,31); + if(rt>=0) { + // Save the PC even if the branch is not taken + return_address=start+i*4+8; + emit_movimm(return_address,rt); // PC into link register + #ifdef IMM_PREFETCH + emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]); + #endif + } + } if(!unconditional) { //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); if(!only32) { assert(s1h>=0); - if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL + if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL { emit_test(s1h,s1h); nottaken=(int)out; emit_jns(1); } - if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL + if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL { emit_test(s1h,s1h); nottaken=(int)out; @@ -5858,13 +5879,13 @@ void sjump_assemble(int i,struct regstat *i_regs) else { assert(s1l>=0); - if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL + if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL { emit_test(s1l,s1l); nottaken=(int)out; emit_jns(1); } - if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL + if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL { emit_test(s1l,s1l); nottaken=(int)out; @@ -8084,11 +8105,11 @@ int new_recompile_block(int addr) break; } break; +#ifndef FORCE32 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break; case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break; case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break; case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break; -#ifndef FORCE32 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break; case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break; case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break; @@ -8398,6 +8419,17 @@ int new_recompile_block(int addr) else ba[i]=-1; /* Is this the end of the block? */ if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) { +#ifdef PCSX + // check for link register access in delay slot + int rt1_=rt1[i-1]; + if(rt1_!=0&&(rs1[i]==rt1_||rs2[i]==rt1_||rt1[i]==rt1_||rt2[i]==rt1_)) { + printf("link access in delay slot @%08x (%08x)\n", addr + i*4, addr); + ba[i-1]=-1; + itype[i-1]=INTCALL; + done=2; + } + else +#endif if(rt1[i-1]==0) { // Continue past subroutine call (JAL) done=2; } @@ -8722,7 +8754,7 @@ int new_recompile_block(int addr) if (rt1[i]==31) { alloc_reg(¤t,i,31); dirty_reg(¤t,31); - //assert(rs1[i+1]!=31&&rs2[i+1]!=31); + assert(rs1[i+1]!=31&&rs2[i+1]!=31); assert(rt1[i+1]!=rt1[i]); #ifdef REG_PREFETCH alloc_reg(¤t,i,PTEMP); @@ -8747,7 +8779,7 @@ int new_recompile_block(int addr) if (rt1[i]!=0) { alloc_reg(¤t,i,rt1[i]); dirty_reg(¤t,rt1[i]); - //assert(rs1[i+1]!=31&&rs2[i+1]!=31); + assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]); assert(rt1[i+1]!=rt1[i]); #ifdef REG_PREFETCH alloc_reg(¤t,i,PTEMP); @@ -8892,7 +8924,6 @@ int new_recompile_block(int addr) if (rt1[i]==31) { // BLTZAL/BGEZAL alloc_reg(¤t,i,31); dirty_reg(¤t,31); - assert(rs1[i+1]!=31&&rs2[i+1]!=31); //#ifdef REG_PREFETCH //alloc_reg(¤t,i,PTEMP); //#endif