X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fnew_dynarec.c;h=66e3dd67c35860834f8ec3d32ee545d67f42bbdd;hp=f81c98536f0cfe9c56cb05c4c8b91e7a20fda5af;hb=93c0345be944a8f53a06433c3c59cfa9c23cd16b;hpb=3d680478922d5f28e3dbe471308cc27a70e31fdf diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index f81c9853..66e3dd67 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -29,16 +29,13 @@ #ifdef _3DS #include <3ds_utils.h> #endif -#ifdef VITA -#include -static int sceBlock; -#endif #include "new_dynarec_config.h" #include "../psxhle.h" #include "../psxinterpreter.h" #include "../gte.h" #include "emu_if.h" // emulator interface +#include "arm_features.h" #define noinline __attribute__((noinline,noclone)) #ifndef ARRAY_SIZE @@ -53,6 +50,7 @@ static int sceBlock; //#define DISASM //#define ASSEM_PRINT +//#define STAT_PRINT #ifdef ASSEM_PRINT #define assem_debug printf @@ -78,10 +76,24 @@ static int sceBlock; #define RAM_SIZE 0x200000 #define MAXBLOCK 4096 #define MAX_OUTPUT_BLOCK_SIZE 262144 +#define EXPIRITY_OFFSET (MAX_OUTPUT_BLOCK_SIZE * 2) +#define PAGE_COUNT 1024 + +#if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) +#define INVALIDATE_USE_COND_CALL +#endif + +#ifdef VITA +// apparently Vita has a 16MB limit, so either we cut tc in half, +// or use this hack (it's a hack because tc size was designed to be power-of-2) +#define TC_REDUCE_BYTES 4096 +#else +#define TC_REDUCE_BYTES 0 +#endif struct ndrc_mem { - u_char translation_cache[1 << TARGET_SIZE_2]; + u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES]; struct { struct tramp_insns ops[2048 / sizeof(struct tramp_insns)]; @@ -114,6 +126,11 @@ enum stub_type { INVCODE_STUB = 14, }; +// regmap_pre[i] - regs before [i] insn starts; dirty things here that +// don't match .regmap will be written back +// [i].regmap_entry - regs that must be set up if someone jumps here +// [i].regmap - regs [i] insn will read/(over)write +// branch_regs[i].* - same as above but for branches, takes delay slot into account struct regstat { signed char regmap_entry[HOST_REGS]; @@ -121,8 +138,8 @@ struct regstat uint64_t wasdirty; uint64_t dirty; uint64_t u; - u_int wasconst; - u_int isconst; + u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true + u_int isconst; // ... but isconst is false when r2 is known u_int loadedconst; // host regs that have constants loaded u_int waswritten; // MIPS regs that were used as store base before }; @@ -131,7 +148,6 @@ struct regstat struct ll_entry { u_int vaddr; - u_int reg_sv_flags; void *addr; struct ll_entry *next; }; @@ -158,30 +174,52 @@ struct link_entry { void *addr; u_int target; - u_int ext; + u_int internal; }; - // used by asm: - u_char *out; - struct ht_entry hash_table[65536] __attribute__((aligned(16))); - struct ll_entry *jump_in[4096] __attribute__((aligned(16))); - struct ll_entry *jump_dirty[4096]; +struct block_info +{ + struct block_info *next; + const void *source; + const void *copy; + u_int start; // vaddr of the block start + u_int len; // of the whole block source + u_int tc_offs; + //u_int tc_len; + u_int reg_sv_flags; + u_short is_dirty; + u_short jump_in_cnt; + struct { + u_int vaddr; + void *addr; + } jump_in[0]; +}; - static struct ll_entry *jump_out[4096]; +static struct decoded_insn +{ + u_char itype; + u_char opcode; + u_char opcode2; + u_char rs1; + u_char rs2; + u_char rt1; + u_char rt2; + u_char use_lt1:1; + u_char bt:1; + u_char ooo:1; + u_char is_ds:1; + u_char is_jump:1; + u_char is_ujump:1; + u_char is_load:1; + u_char is_store:1; +} dops[MAXBLOCK]; + + static u_char *out; + static struct ht_entry hash_table[65536]; + static struct block_info *blocks[PAGE_COUNT]; + static struct ll_entry *jump_out[PAGE_COUNT]; static u_int start; static u_int *source; - static char insn[MAXBLOCK][10]; - static u_char itype[MAXBLOCK]; - static u_char opcode[MAXBLOCK]; - static u_char opcode2[MAXBLOCK]; - static u_char bt[MAXBLOCK]; - static u_char rs1[MAXBLOCK]; - static u_char rs2[MAXBLOCK]; - static u_char rt1[MAXBLOCK]; - static u_char rt2[MAXBLOCK]; - static u_char dep1[MAXBLOCK]; - static u_char dep2[MAXBLOCK]; - static u_char lt1[MAXBLOCK]; static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs static uint64_t gte_rt[MAXBLOCK]; static uint64_t gte_unneeded[MAXBLOCK]; @@ -192,12 +230,10 @@ struct link_entry static u_int smrv_weak_next; static int imm[MAXBLOCK]; static u_int ba[MAXBLOCK]; - static char likely[MAXBLOCK]; - static char is_ds[MAXBLOCK]; - static char ooo[MAXBLOCK]; static uint64_t unneeded_reg[MAXBLOCK]; static uint64_t branch_unneeded_reg[MAXBLOCK]; - static signed char regmap_pre[MAXBLOCK][HOST_REGS]; // pre-instruction i? + // see 'struct regstat' for a description + static signed char regmap_pre[MAXBLOCK][HOST_REGS]; // contains 'real' consts at [i] insn, but may differ from what's actually // loaded in host reg as 'final' value is always loaded, see get_final_value() static uint32_t current_constmap[HOST_REGS]; @@ -205,9 +241,6 @@ struct link_entry static struct regstat regs[MAXBLOCK]; static struct regstat branch_regs[MAXBLOCK]; static signed char minimum_free_regs[MAXBLOCK]; - static u_int needed_reg[MAXBLOCK]; - static u_int wont_dirty[MAXBLOCK]; - static u_int will_dirty[MAXBLOCK]; static int ccadj[MAXBLOCK]; static int slen; static void *instr_addr[MAXBLOCK]; @@ -220,12 +253,28 @@ struct link_entry static int is_delayslot; static char shadow[1048576] __attribute__((aligned(16))); static void *copy; - static int expirep; + static u_int expirep; static u_int stop_after_jal; -#ifndef RAM_FIXED - static uintptr_t ram_offset; + static u_int f1_hack; +#ifdef STAT_PRINT + static int stat_bc_direct; + static int stat_bc_pre; + static int stat_bc_restore; + static int stat_ht_lookups; + static int stat_jump_in_lookups; + static int stat_restore_tries; + static int stat_restore_compares; + static int stat_inv_addr_calls; + static int stat_inv_hits; + static int stat_blocks; + static int stat_links; + #define stat_inc(s) s++ + #define stat_dec(s) s-- + #define stat_clear(s) s = 0 #else - static const uintptr_t ram_offset=0; + #define stat_inc(s) + #define stat_dec(s) + #define stat_clear(s) #endif int new_dynarec_hacks; @@ -240,8 +289,8 @@ struct link_entry extern int pcaddr; extern int pending_exception; extern int branch_target; + extern uintptr_t ram_offset; extern uintptr_t mini_ht[32][2]; - extern u_char restore_candidate[512]; /* registers that may be allocated */ /* 1-31 gpr */ @@ -252,7 +301,7 @@ struct link_entry #define CCREG 36 // Cycle count #define INVCP 37 // Pointer to invalid_code //#define MMREG 38 // Pointer to memory_map -//#define ROREG 39 // ram offset (if rdram!=0x80000000) +#define ROREG 39 // ram offset (if rdram!=0x80000000) #define TEMPREG 40 #define FTEMP 40 // FPU temporary register #define PTEMP 41 // Prefetch temporary register @@ -290,9 +339,9 @@ struct link_entry //#define FLOAT 19 // Floating point unit //#define FCONV 20 // Convert integer to float //#define FCOMP 21 // Floating point compare (sets FSREG) -#define SYSCALL 22// SYSCALL +#define SYSCALL 22// SYSCALL,BREAK #define OTHER 23 // Other -#define SPAN 24 // Branch/delay slot spans 2 pages +//#define SPAN 24 // Branch/delay slot spans 2 pages #define NI 25 // Not implemented #define HLECALL 26// PCSX fake opcodes for HLE #define COP2 27 // Coprocessor 2 move @@ -309,40 +358,44 @@ struct link_entry #define DJT_2 (void *)2l // asm linkage -int new_recompile_block(u_int addr); -void *get_addr_ht(u_int vaddr); -void invalidate_block(u_int block); -void invalidate_addr(u_int addr); -void remove_hash(int vaddr); void dyna_linker(); -void dyna_linker_ds(); -void verify_code(); -void verify_code_ds(); void cc_interrupt(); void fp_exception(); void fp_exception_ds(); +void jump_syscall (u_int u0, u_int u1, u_int pc); +void jump_syscall_ds(u_int u0, u_int u1, u_int pc); +void jump_break (u_int u0, u_int u1, u_int pc); +void jump_break_ds(u_int u0, u_int u1, u_int pc); void jump_to_new_pc(); void call_gteStall(); void new_dyna_leave(); +void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile); +void *ndrc_get_addr_ht(u_int vaddr); +void ndrc_invalidate_addr(u_int addr); +void ndrc_add_jump_out(u_int vaddr, void *src); + +static int new_recompile_block(u_int addr); +static void invalidate_block(struct block_info *block); + // Needed by assembler -static void wb_register(signed char r,signed char regmap[],uint64_t dirty); -static void wb_dirtys(signed char i_regmap[],uint64_t i_dirty); -static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr); -static void load_all_regs(signed char i_regmap[]); -static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]); +static void wb_register(signed char r, const signed char regmap[], uint64_t dirty); +static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty); +static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr); +static void load_all_regs(const signed char i_regmap[]); +static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]); static void load_regs_entry(int t); -static void load_all_consts(signed char regmap[],u_int dirty,int i); +static void load_all_consts(const signed char regmap[], u_int dirty, int i); static u_int get_host_reglist(const signed char *regmap); -static int verify_dirty(const u_int *ptr); static int get_final_value(int hr, int i, int *value); static void add_stub(enum stub_type type, void *addr, void *retaddr, u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e); static void add_stub_r(enum stub_type type, void *addr, void *retaddr, int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist); static void add_to_linker(void *addr, u_int target, int ext); -static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override); +static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs, + int addr, int *offset_reg, int *addr_reg_override); static void *get_direct_memhandler(void *table, u_int addr, enum stub_type type, uintptr_t *addr_host); static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist); @@ -350,6 +403,14 @@ static void pass_args(int a0, int a1); static void emit_far_jump(const void *f); static void emit_far_call(const void *f); +#ifdef VITA +#include +static int sceBlock; +// note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c +extern int getVMBlock(); +int _newlib_vm_size_user = sizeof(*ndrc); +#endif + static void mprotect_w_x(void *start, void *end, int is_x) { #ifdef NO_WRITE_EXEC @@ -441,13 +502,13 @@ static void do_clear_cache(void) for (j = 0; j < 32; j++) { u_char *start, *end; - if (!(bitmap & (1<translation_cache + i*131072 + j*4096; end = start + 4095; for (j++; j < 32; j++) { - if (!(bitmap & (1<>31)|1; + int m = cycle_multiplier_active; + int s = (x >> 31) | 1; return (x * m + s * 50) / 100; } -// is the op an unconditional jump? -static int is_ujump(int i) +static int ds_writes_rjump_rs(int i) { - return itype[i] == UJUMP || itype[i] == RJUMP - || (source[i] >> 16) == 0x1000; // beq r0, r0, offset // b offset + return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2); } -static int is_jump(int i) +// psx addr mirror masking (for invalidation) +static u_int pmmask(u_int vaddr) { - return itype[i] == RJUMP || itype[i] == UJUMP || itype[i] == CJUMP || itype[i] == SJUMP; + vaddr &= ~0xe0000000; + if (vaddr < 0x01000000) + vaddr &= ~0x00e00000; // RAM mirrors + return vaddr; } static u_int get_page(u_int vaddr) { - u_int page=vaddr&~0xe0000000; - if (page < 0x1000000) - page &= ~0x0e00000; // RAM mirrors - page>>=12; - if(page>2048) page=2048+(page&2047); + u_int page = pmmask(vaddr) >> 12; + if (page >= PAGE_COUNT / 2) + page = PAGE_COUNT / 2 + (page & (PAGE_COUNT / 2 - 1)); return page; } -// no virtual mem in PCSX -static u_int get_vpage(u_int vaddr) +// get a page for looking for a block that has vaddr +// (needed because the block may start in previous page) +static u_int get_page_prev(u_int vaddr) { - return get_page(vaddr); + assert(MAXBLOCK <= (1 << 12)); + u_int page = get_page(vaddr); + if (page & 511) + page--; + return page; } static struct ht_entry *hash_table_get(u_int vaddr) @@ -506,95 +572,191 @@ static struct ht_entry *hash_table_get(u_int vaddr) return &hash_table[((vaddr>>16)^vaddr)&0xFFFF]; } -static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr) +static void hash_table_add(u_int vaddr, void *tcaddr) { + struct ht_entry *ht_bin = hash_table_get(vaddr); + assert(tcaddr); ht_bin->vaddr[1] = ht_bin->vaddr[0]; ht_bin->tcaddr[1] = ht_bin->tcaddr[0]; ht_bin->vaddr[0] = vaddr; ht_bin->tcaddr[0] = tcaddr; } -// some messy ari64's code, seems to rely on unsigned 32bit overflow -static int doesnt_expire_soon(void *tcaddr) +static void hash_table_remove(int vaddr) +{ + //printf("remove hash: %x\n",vaddr); + struct ht_entry *ht_bin = hash_table_get(vaddr); + if (ht_bin->vaddr[1] == vaddr) { + ht_bin->vaddr[1] = -1; + ht_bin->tcaddr[1] = NULL; + } + if (ht_bin->vaddr[0] == vaddr) { + ht_bin->vaddr[0] = ht_bin->vaddr[1]; + ht_bin->tcaddr[0] = ht_bin->tcaddr[1]; + ht_bin->vaddr[1] = -1; + ht_bin->tcaddr[1] = NULL; + } +} + +static void mark_invalid_code(u_int vaddr, u_int len, char invalid) +{ + u_int i, j; + vaddr &= 0x1fffffff; + for (i = vaddr & ~0xfff; i < vaddr + len; i += 0x1000) { + // ram mirrors, but should not hurt bios + for (j = 0; j < 0x800000; j += 0x200000) { + invalid_code[(i|j) >> 12] = + invalid_code[(i|j|0x80000000u) >> 12] = + invalid_code[(i|j|0xa0000000u) >> 12] = invalid; + } + } + if (!invalid && vaddr + len > inv_code_start && vaddr <= inv_code_end) + inv_code_start = inv_code_end = ~0; +} + +static int doesnt_expire_soon(u_char *tcaddr) +{ + u_int diff = (u_int)(tcaddr - out) & ((1u << TARGET_SIZE_2) - 1u); + return diff > EXPIRITY_OFFSET + MAX_OUTPUT_BLOCK_SIZE; +} + +static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page) { - u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2); - return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2))); + void *found_clean = NULL; + u_int i, page; + + stat_inc(stat_restore_tries); + for (page = start_page; page <= end_page; page++) { + struct block_info *block; + for (block = blocks[page]; block != NULL; block = block->next) { + if (vaddr < block->start) + break; + if (!block->is_dirty || vaddr >= block->start + block->len) + continue; + for (i = 0; i < block->jump_in_cnt; i++) + if (block->jump_in[i].vaddr == vaddr) + break; + if (i == block->jump_in_cnt) + continue; + assert(block->source && block->copy); + stat_inc(stat_restore_compares); + if (memcmp(block->source, block->copy, block->len)) + continue; + + block->is_dirty = 0; + found_clean = block->jump_in[i].addr; + hash_table_add(vaddr, found_clean); + mark_invalid_code(block->start, block->len, 0); + stat_inc(stat_bc_restore); + inv_debug("INV: restored %08x %p (%d)\n", vaddr, found_clean, block->jump_in_cnt); + return found_clean; + } + } + return NULL; } // Get address from virtual address // This is called from the recompiled JR/JALR instructions -void noinline *get_addr(u_int vaddr) +static void noinline *get_addr(u_int vaddr, int can_compile) { - u_int page=get_page(vaddr); - u_int vpage=get_vpage(vaddr); - struct ll_entry *head; - //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page); - head=jump_in[page]; - while(head!=NULL) { - if(head->vaddr==vaddr) { - //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr); - hash_table_add(hash_table_get(vaddr), vaddr, head->addr); - return head->addr; - } - head=head->next; - } - head=jump_dirty[vpage]; - while(head!=NULL) { - if(head->vaddr==vaddr) { - //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr); - // Don't restore blocks which are about to expire from the cache - if (doesnt_expire_soon(head->addr)) - if (verify_dirty(head->addr)) { - //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]); - invalid_code[vaddr>>12]=0; - inv_code_start=inv_code_end=~0; - if(vpage<2048) { - restore_candidate[vpage>>3]|=1<<(vpage&7); - } - else restore_candidate[page>>3]|=1<<(page&7); - struct ht_entry *ht_bin = hash_table_get(vaddr); - if (ht_bin->vaddr[0] == vaddr) - ht_bin->tcaddr[0] = head->addr; // Replace existing entry - else - hash_table_add(ht_bin, vaddr, head->addr); + u_int start_page = get_page_prev(vaddr); + u_int i, page, end_page = get_page(vaddr); + void *found_clean = NULL; - return head->addr; - } + stat_inc(stat_jump_in_lookups); + for (page = start_page; page <= end_page; page++) { + const struct block_info *block; + for (block = blocks[page]; block != NULL; block = block->next) { + if (vaddr < block->start) + break; + if (block->is_dirty || vaddr >= block->start + block->len) + continue; + for (i = 0; i < block->jump_in_cnt; i++) + if (block->jump_in[i].vaddr == vaddr) + break; + if (i == block->jump_in_cnt) + continue; + found_clean = block->jump_in[i].addr; + hash_table_add(vaddr, found_clean); + return found_clean; } - head=head->next; } - //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr); - int r=new_recompile_block(vaddr); - if(r==0) return get_addr(vaddr); - // Execute in unmapped page, generate pagefault execption + found_clean = try_restore_block(vaddr, start_page, end_page); + if (found_clean) + return found_clean; + + if (!can_compile) + return NULL; + + int r = new_recompile_block(vaddr); + if (r == 0) + return ndrc_get_addr_ht(vaddr); + + // generate an address error Status|=2; - Cause=(vaddr<<31)|0x8; + Cause=(vaddr<<31)|(4<<2); EPC=(vaddr&1)?vaddr-5:vaddr; BadVAddr=(vaddr&~1); - Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0); - EntryHi=BadVAddr&0xFFFFE000; - return get_addr_ht(0x80000000); + return ndrc_get_addr_ht(0x80000080); } + // Look up address in hash table first -void *get_addr_ht(u_int vaddr) +void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile) { - //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr); const struct ht_entry *ht_bin = hash_table_get(vaddr); + stat_inc(stat_ht_lookups); if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0]; if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1]; - return get_addr(vaddr); + return get_addr(vaddr, can_compile); +} + +void *ndrc_get_addr_ht(u_int vaddr) +{ + return ndrc_get_addr_ht_param(vaddr, 1); +} + +static void clear_all_regs(signed char regmap[]) +{ + memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS); } -void clear_all_regs(signed char regmap[]) +// get_reg: get allocated host reg from mips reg +// returns -1 if no such mips reg was allocated +#if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11 + +extern signed char get_reg(const signed char regmap[], signed char r); + +#else + +static signed char get_reg(const signed char regmap[], signed char r) { int hr; - for (hr=0;hr host +#define RRMAP_SIZE 64 +static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE], + u_int *regs_can_change) +{ + u_int r, hr, hr_can_change = 0; + memset(rrmap, -1, RRMAP_SIZE); + for (hr = 0; hr < HOST_REGS; ) + { + r = regmap[hr]; + rrmap[r & (RRMAP_SIZE - 1)] = hr; + // only add mips $1-$31+$lo, others shifted out + hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32)); + hr++; + if (hr == EXCLUDE_REG) + hr++; + } + hr_can_change |= 1u << (rrmap[33] & 31); + hr_can_change |= 1u << (rrmap[CCREG] & 31); + hr_can_change &= ~(1u << 31); + *regs_can_change = hr_can_change; +} + +// same as get_reg, but takes rrmap +static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r) +{ + assert(0 <= r && r < RRMAP_SIZE); + return rrmap[r]; +} + +static int count_free_regs(const signed char regmap[]) { int count=0; int hr; @@ -619,70 +811,62 @@ int count_free_regs(signed char regmap[]) return count; } -void dirty_reg(struct regstat *cur,signed char reg) +static void dirty_reg(struct regstat *cur, signed char reg) { int hr; - if(!reg) return; - for (hr=0;hrregmap[hr]&63)==reg) { - cur->dirty|=1<regmap, reg); + if (hr >= 0) + cur->dirty |= 1<regmap[hr]==reg) { - cur->isconst|=1<regmap, reg); + if (hr >= 0) { + cur->isconst |= 1<regmap[hr]&63)==reg) { - cur->isconst&=~(1<regmap, reg); + if (hr >= 0) + cur->isconst &= ~(1<regmap[hr]&63)==reg) { - return (cur->isconst>>hr)&1; - } - } + if (reg < 0) return 0; + if (!reg) return 1; + hr = get_reg(cur->regmap, reg); + if (hr >= 0) + return (cur->isconst>>hr)&1; return 0; } -static uint32_t get_const(struct regstat *cur, signed char reg) +static uint32_t get_const(const struct regstat *cur, signed char reg) { int hr; - if(!reg) return 0; - for (hr=0;hrregmap[hr]==reg) { - return current_constmap[hr]; - } - } - SysPrintf("Unknown constant in r%d\n",reg); + if (!reg) return 0; + hr = get_reg(cur->regmap, reg); + if (hr >= 0) + return current_constmap[hr]; + + SysPrintf("Unknown constant in r%d\n", reg); abort(); } // Least soon needed registers // Look at the next ten instructions and see which registers // will be used. Try not to reallocate these. -void lsn(u_char hsn[], int i, int *preferred_reg) +static void lsn(u_char hsn[], int i, int *preferred_reg) { int j; int b=-1; @@ -692,7 +876,7 @@ void lsn(u_char hsn[], int i, int *preferred_reg) j=slen-i-1; break; } - if (is_ujump(i+j)) + if (dops[i+j].is_ujump) { // Don't go past an unconditonal jump j++; @@ -701,22 +885,23 @@ void lsn(u_char hsn[], int i, int *preferred_reg) } for(;j>=0;j--) { - if(rs1[i+j]) hsn[rs1[i+j]]=j; - if(rs2[i+j]) hsn[rs2[i+j]]=j; - if(rt1[i+j]) hsn[rt1[i+j]]=j; - if(rt2[i+j]) hsn[rt2[i+j]]=j; - if(itype[i+j]==STORE || itype[i+j]==STORELR) { + if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j; + if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j; + if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j; + if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j; + if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) { // Stores can allocate zero - hsn[rs1[i+j]]=j; - hsn[rs2[i+j]]=j; + hsn[dops[i+j].rs1]=j; + hsn[dops[i+j].rs2]=j; } + if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store)) + hsn[ROREG] = j; // On some architectures stores need invc_ptr #if defined(HOST_IMM8) - if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) { - hsn[INVCP]=j; - } + if (dops[i+j].is_store) + hsn[INVCP] = j; #endif - if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP)) + if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP)) { hsn[CCREG]=j; b=j; @@ -731,37 +916,37 @@ void lsn(u_char hsn[], int i, int *preferred_reg) j=7-b;if(t+j>=slen) j=slen-t-1; for(;j>=0;j--) { - if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2; - if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2; - //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2; - //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2; + if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2; + if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2; + //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2; + //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2; } } // TODO: preferred register based on backward branch } // Delay slot should preferably not overwrite branch conditions or cycle count - if (i > 0 && is_jump(i-1)) { - if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1; - if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1; + if (i > 0 && dops[i-1].is_jump) { + if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1; + if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1; hsn[CCREG]=1; // ...or hash tables hsn[RHASH]=1; hsn[RHTBL]=1; } // Coprocessor load/store needs FTEMP, even if not declared - if(itype[i]==C1LS||itype[i]==C2LS) { + if(dops[i].itype==C2LS) { hsn[FTEMP]=0; } // Load L/R also uses FTEMP as a temporary register - if(itype[i]==LOADLR) { + if(dops[i].itype==LOADLR) { hsn[FTEMP]=0; } // Also SWL/SWR/SDL/SDR - if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { + if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { hsn[FTEMP]=0; } // Don't remove the miniht registers - if(itype[i]==UJUMP||itype[i]==RJUMP) + if(dops[i].itype==UJUMP||dops[i].itype==RJUMP) { hsn[RHASH]=0; hsn[RHTBL]=0; @@ -769,13 +954,13 @@ void lsn(u_char hsn[], int i, int *preferred_reg) } // We only want to allocate registers if we're going to use them again soon -int needed_again(int r, int i) +static int needed_again(int r, int i) { int j; int b=-1; int rn=10; - if (i > 0 && is_ujump(i-1)) + if (i > 0 && dops[i-1].is_ujump) { if(ba[i-1]start+slen*4-4) return 0; // Don't need any registers if exiting the block @@ -786,46 +971,27 @@ int needed_again(int r, int i) j=slen-i-1; break; } - if (is_ujump(i+j)) + if (dops[i+j].is_ujump) { // Don't go past an unconditonal jump j++; break; } - if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d)) + if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d)) { break; } } for(;j>=1;j--) { - if(rs1[i+j]==r) rn=j; - if(rs2[i+j]==r) rn=j; + if(dops[i+j].rs1==r) rn=j; + if(dops[i+j].rs2==r) rn=j; if((unneeded_reg[i+j]>>r)&1) rn=10; - if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP)) + if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP)) { b=j; } } - /* - if(b>=0) - { - if(ba[i+b]>=start && ba[i+b]<(start+slen*4)) - { - // Follow first branch - int o=rn; - int t=(ba[i+b]-start)>>2; - j=7-b;if(t+j>=slen) j=slen-t-1; - for(;j>=0;j--) - { - if(!((unneeded_reg[t+j]>>r)&1)) { - if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2; - if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2; - } - else rn=o; - } - } - }*/ if(rn<10) return 1; (void)b; return 0; @@ -833,7 +999,7 @@ int needed_again(int r, int i) // Try to match register allocations at the end of a loop with those // at the beginning -int loop_reg(int i, int r, int hr) +static int loop_reg(int i, int r, int hr) { int j,k; for(j=0;j<9;j++) @@ -842,7 +1008,7 @@ int loop_reg(int i, int r, int hr) j=slen-i-1; break; } - if (is_ujump(i+j)) + if (dops[i+j].is_ujump) { // Don't go past an unconditonal jump j++; @@ -851,14 +1017,14 @@ int loop_reg(int i, int r, int hr) } k=0; if(i>0){ - if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP) + if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP) k--; } for(;k>r)&1) return hr; - if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP)) + if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP)) { if(ba[i+k]>=start && ba[i+k]<(start+i*4)) { @@ -875,20 +1041,20 @@ int loop_reg(int i, int r, int hr) // Allocate every register, preserving source/target regs -void alloc_all(struct regstat *cur,int i) +static void alloc_all(struct regstat *cur,int i) { int hr; for(hr=0;hrregmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&& - ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i])) + if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&& + (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2)) { cur->regmap[hr]=-1; cur->dirty&=~(1<regmap[hr]&63)==0) + if(cur->regmap[hr]==0) { cur->regmap[hr]=-1; cur->dirty&=~(1<vaddr=vaddr; - new_entry->reg_sv_flags=0; new_entry->addr=addr; new_entry->next=*head; *head=new_entry; } -void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr) -{ - ll_add(head,vaddr,addr); - (*head)->reg_sv_flags=reg_sv_flags; -} - // Check if an address is already compiled // but don't return addresses which are about to expire from the cache -void *check_addr(u_int vaddr) +static void *check_addr(u_int vaddr) { struct ht_entry *ht_bin = hash_table_get(vaddr); size_t i; for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) { if (ht_bin->vaddr[i] == vaddr) - if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE)) - if (isclean(ht_bin->tcaddr[i])) - return ht_bin->tcaddr[i]; + if (doesnt_expire_soon(ht_bin->tcaddr[i])) + return ht_bin->tcaddr[i]; } - u_int page=get_page(vaddr); - struct ll_entry *head; - head=jump_in[page]; - while (head != NULL) { - if (head->vaddr == vaddr) { - if (doesnt_expire_soon(head->addr)) { - // Update existing entry with current address - if (ht_bin->vaddr[0] == vaddr) { - ht_bin->tcaddr[0] = head->addr; - return head->addr; - } - if (ht_bin->vaddr[1] == vaddr) { - ht_bin->tcaddr[1] = head->addr; - return head->addr; - } - // Insert into hash table with low priority. - // Don't evict existing entries, as they are probably - // addresses that are being accessed frequently. - if (ht_bin->vaddr[0] == -1) { - ht_bin->vaddr[0] = vaddr; - ht_bin->tcaddr[0] = head->addr; - } - else if (ht_bin->vaddr[1] == -1) { - ht_bin->vaddr[1] = vaddr; - ht_bin->tcaddr[1] = head->addr; - } - return head->addr; + + // refactor to get_addr_nocompile? + u_int start_page = get_page_prev(vaddr); + u_int page, end_page = get_page(vaddr); + + stat_inc(stat_jump_in_lookups); + for (page = start_page; page <= end_page; page++) { + const struct block_info *block; + for (block = blocks[page]; block != NULL; block = block->next) { + if (vaddr < block->start) + break; + if (block->is_dirty || vaddr >= block->start + block->len) + continue; + if (!doesnt_expire_soon(ndrc->translation_cache + block->tc_offs)) + continue; + for (i = 0; i < block->jump_in_cnt; i++) + if (block->jump_in[i].vaddr == vaddr) + break; + if (i == block->jump_in_cnt) + continue; + + // Update existing entry with current address + void *addr = block->jump_in[i].addr; + if (ht_bin->vaddr[0] == vaddr) { + ht_bin->tcaddr[0] = addr; + return addr; + } + if (ht_bin->vaddr[1] == vaddr) { + ht_bin->tcaddr[1] = addr; + return addr; + } + // Insert into hash table with low priority. + // Don't evict existing entries, as they are probably + // addresses that are being accessed frequently. + if (ht_bin->vaddr[0] == -1) { + ht_bin->vaddr[0] = vaddr; + ht_bin->tcaddr[0] = addr; + } + else if (ht_bin->vaddr[1] == -1) { + ht_bin->vaddr[1] = vaddr; + ht_bin->tcaddr[1] = addr; } + return addr; } - head=head->next; - } - return 0; -} - -void remove_hash(int vaddr) -{ - //printf("remove hash: %x\n",vaddr); - struct ht_entry *ht_bin = hash_table_get(vaddr); - if (ht_bin->vaddr[1] == vaddr) { - ht_bin->vaddr[1] = -1; - ht_bin->tcaddr[1] = NULL; - } - if (ht_bin->vaddr[0] == vaddr) { - ht_bin->vaddr[0] = ht_bin->vaddr[1]; - ht_bin->tcaddr[0] = ht_bin->tcaddr[1]; - ht_bin->vaddr[1] = -1; - ht_bin->tcaddr[1] = NULL; } + return NULL; } -static void ll_remove_matching_addrs(struct ll_entry **head, - uintptr_t base_offs_s, int shift) +static void ll_remove_matching_addrs(struct ll_entry **head, u_int base_offs, int shift) { struct ll_entry *next; - while(*head) { - uintptr_t o1 = (u_char *)(*head)->addr - ndrc->translation_cache; - uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE; - if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) - { - inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr); - remove_hash((*head)->vaddr); - next=(*head)->next; + while (*head) { + u_int tc_offs = (u_char *)((*head)->addr) - ndrc->translation_cache; + if (((tc_offs ^ base_offs) >> shift) == 0) { + inv_debug("EXP: rm link from tc_offs %x)\n", tc_offs); + next = (*head)->next; free(*head); - *head=next; + *head = next; } else { - head=&((*head)->next); + head = &((*head)->next); } } } // Remove all entries from linked list -void ll_clear(struct ll_entry **head) +static void ll_clear(struct ll_entry **head) { struct ll_entry *cur; struct ll_entry *next; @@ -1132,177 +1284,170 @@ void ll_clear(struct ll_entry **head) } } -// Dereference the pointers and remove if it matches -static void ll_kill_pointers(struct ll_entry *head, - uintptr_t base_offs_s, int shift) +static void blocks_clear(struct block_info **head) +{ + struct block_info *cur, *next; + + if ((cur = *head)) { + *head = NULL; + while (cur) { + next = cur->next; + free(cur); + cur = next; + } + } +} + +static int blocks_remove_matching_addrs(struct block_info **head, + u_int base_offs, int shift) { - while(head) { - u_char *ptr = get_pointer(head->addr); - uintptr_t o1 = ptr - ndrc->translation_cache; - uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE; - inv_debug("EXP: Lookup pointer to %p at %p (%x)\n",ptr,head->addr,head->vaddr); - if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) + struct block_info *next; + int hit = 0; + while (*head) { + if ((((*head)->tc_offs ^ base_offs) >> shift) == 0) { + inv_debug("EXP: rm block %08x (tc_offs %zx)\n", (*head)->start, (*head)->tc_offs); + invalidate_block(*head); + next = (*head)->next; + free(*head); + *head = next; + stat_dec(stat_blocks); + hit = 1; + } + else { - inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr); - void *host_addr=find_extjump_insn(head->addr); - mark_clear_cache(host_addr); - set_jump_target(host_addr, head->addr); + head = &((*head)->next); } - head=head->next; } + return hit; } // This is called when we write to a compiled block (see do_invstub) -static void invalidate_page(u_int page) +static void unlink_jumps_range(u_int start, u_int end) { - struct ll_entry *head; - struct ll_entry *next; - head=jump_in[page]; - jump_in[page]=0; - while(head!=NULL) { - inv_debug("INVALIDATE: %x\n",head->vaddr); - remove_hash(head->vaddr); - next=head->next; - free(head); - head=next; - } - head=jump_out[page]; - jump_out[page]=0; - while(head!=NULL) { - inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr); - void *host_addr=find_extjump_insn(head->addr); - mark_clear_cache(host_addr); - set_jump_target(host_addr, head->addr); // point back to dyna_linker - next=head->next; - free(head); - head=next; - } -} - -static void invalidate_block_range(u_int block, u_int first, u_int last) -{ - u_int page=get_page(block<<12); - //printf("first=%d last=%d\n",first,last); - invalidate_page(page); - assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages) - assert(lastvaddr < start || (*head)->vaddr >= end) { + head = &((*head)->next); + continue; + } + inv_debug("INV: rm link to %08x (tc_offs %zx)\n", + (*head)->vaddr, (u_char *)((*head)->addr) - ndrc->translation_cache); + void *host_addr = find_extjump_insn((*head)->addr); + mark_clear_cache(host_addr); + set_jump_target(host_addr, (*head)->addr); // point back to dyna_linker stub + + next = (*head)->next; + free(*head); + *head = next; + stat_dec(stat_links); + } } - do_clear_cache(); +} - // Don't trap writes - invalid_code[block]=1; +static void invalidate_block(struct block_info *block) +{ + u_int i; - #ifdef USE_MINI_HT - memset(mini_ht,-1,sizeof(mini_ht)); - #endif + block->is_dirty = 1; + unlink_jumps_range(block->start, block->start + block->len); + for (i = 0; i < block->jump_in_cnt; i++) + hash_table_remove(block->jump_in[i].vaddr); } -void invalidate_block(u_int block) +static int invalidate_range(u_int start, u_int end, + u32 *inv_start_ret, u32 *inv_end_ret) { - u_int page=get_page(block<<12); - u_int vpage=get_vpage(block<<12); - inv_debug("INVALIDATE: %x (%d)\n",block<<12,page); - //inv_debug("invalid_code[block]=%d\n",invalid_code[block]); - u_int first,last; - first=last=page; - struct ll_entry *head; - head=jump_dirty[vpage]; - //printf("page=%d vpage=%d\n",page,vpage); - while(head!=NULL) { - if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision - u_char *start, *end; - get_bounds(head->addr, &start, &end); - //printf("start: %p end: %p\n", start, end); - if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) { - if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) { - if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047; - if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047; - } + u_int start_page = get_page_prev(start); + u_int end_page = get_page(end - 1); + u_int start_m = pmmask(start); + u_int end_m = pmmask(end); + u_int inv_start, inv_end; + u_int blk_start_m, blk_end_m; + u_int page; + int hit = 0; + + // additional area without code (to supplement invalid_code[]), [start, end) + // avoids excessive ndrc_invalidate_addr() calls + inv_start = start_m & ~0xfff; + inv_end = end_m | 0xfff; + + for (page = start_page; page <= end_page; page++) { + struct block_info *block; + for (block = blocks[page]; block != NULL; block = block->next) { + if (block->is_dirty) + continue; + blk_end_m = pmmask(block->start + block->len); + if (blk_end_m <= start_m) { + inv_start = max(inv_start, blk_end_m); + continue; + } + blk_start_m = pmmask(block->start); + if (end_m <= blk_start_m) { + inv_end = min(inv_end, blk_start_m - 1); + continue; } + if (!block->source) // "hack" block - leave it alone + continue; + + hit++; + invalidate_block(block); + stat_inc(stat_inv_hits); } - head=head->next; } - invalidate_block_range(block,first,last); + + if (hit) { + do_clear_cache(); +#ifdef USE_MINI_HT + memset(mini_ht, -1, sizeof(mini_ht)); +#endif + } + if (inv_start <= (start_m & ~0xfff) && inv_end >= (start_m | 0xfff)) + // the whole page is empty now + mark_invalid_code(start, 1, 1); + + if (inv_start_ret) *inv_start_ret = inv_start | (start & 0xe0000000); + if (inv_end_ret) *inv_end_ret = inv_end | (end & 0xe0000000); + return hit; +} + +void new_dynarec_invalidate_range(unsigned int start, unsigned int end) +{ + invalidate_range(start, end, NULL, NULL); } -void invalidate_addr(u_int addr) +void ndrc_invalidate_addr(u_int addr) { - //static int rhits; // this check is done by the caller //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; } - u_int page=get_vpage(addr); - if(page<2048) { // RAM - struct ll_entry *head; - u_int addr_min=~0, addr_max=0; - u_int mask=RAM_SIZE-1; - u_int addr_main=0x80000000|(addr&mask); - int pg1; - inv_code_start=addr_main&~0xfff; - inv_code_end=addr_main|0xfff; - pg1=page; - if (pg1>0) { - // must check previous page too because of spans.. - pg1--; - inv_code_start-=0x1000; - } - for(;pg1<=page;pg1++) { - for(head=jump_dirty[pg1];head!=NULL;head=head->next) { - u_char *start_h, *end_h; - u_int start, end; - get_bounds(head->addr, &start_h, &end_h); - start = (uintptr_t)start_h - ram_offset; - end = (uintptr_t)end_h - ram_offset; - if(start<=addr_main&&addr_mainaddr_max) addr_max=end; - } - else if(addr_maininv_code_start) - inv_code_start=end; - } - } - } - if (addr_min!=~0) { - inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max); - inv_code_start=inv_code_end=~0; - invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12); - return; - } - else { - inv_code_start=(addr&~mask)|(inv_code_start&mask); - inv_code_end=(addr&~mask)|(inv_code_end&mask); - inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0); - return; - } - } - invalidate_block(addr>>12); + int ret = invalidate_range(addr, addr + 4, &inv_code_start, &inv_code_end); + if (ret) + inv_debug("INV ADDR: %08x hit %d blocks\n", addr, ret); + else + inv_debug("INV ADDR: %08x miss, inv %08x-%08x\n", addr, inv_code_start, inv_code_end); + stat_inc(stat_inv_addr_calls); } // This is called when loading a save state. // Anything could have changed, so invalidate everything. -void invalidate_all_pages(void) +void new_dynarec_invalidate_all_pages(void) { + struct block_info *block; u_int page; - for(page=0;page<4096;page++) - invalidate_page(page); - for(page=0;page<1048576;page++) - if(!invalid_code[page]) { - restore_candidate[(page&2047)>>3]|=1<<(page&7); - restore_candidate[((page&2047)>>3)+256]|=1<<(page&7); + for (page = 0; page < ARRAY_SIZE(blocks); page++) { + for (block = blocks[page]; block != NULL; block = block->next) { + if (block->is_dirty) + continue; + if (!block->source) // hack block? + continue; + invalidate_block(block); } + } + #ifdef USE_MINI_HT - memset(mini_ht,-1,sizeof(mini_ht)); + memset(mini_ht, -1, sizeof(mini_ht)); #endif do_clear_cache(); } @@ -1310,73 +1455,33 @@ void invalidate_all_pages(void) static void do_invstub(int n) { literal_pool(20); - u_int reglist=stubs[n].a; + u_int reglist = stubs[n].a; set_jump_target(stubs[n].addr, out); save_regs(reglist); - if(stubs[n].b!=0) emit_mov(stubs[n].b,0); - emit_far_call(invalidate_addr); + if (stubs[n].b != 0) + emit_mov(stubs[n].b, 0); + emit_readword(&inv_code_start, 1); + emit_readword(&inv_code_end, 2); + emit_cmp(0, 1); + emit_cmpcs(2, 0); + void *jaddr = out; + emit_jc(0); + emit_far_call(ndrc_invalidate_addr); + set_jump_target(jaddr, out); restore_regs(reglist); emit_jmp(stubs[n].retaddr); // return address } // Add an entry to jump_out after making a link -// src should point to code by emit_extjump2() -void add_jump_out(u_int vaddr,void *src) +// src should point to code by emit_extjump() +void ndrc_add_jump_out(u_int vaddr,void *src) { u_int page=get_page(vaddr); - inv_debug("add_jump_out: %p -> %x (%d)\n",src,vaddr,page); + inv_debug("ndrc_add_jump_out: %p -> %x (%d)\n",src,vaddr,page); check_extjump2(src); ll_add(jump_out+page,vaddr,src); - //inv_debug("add_jump_out: to %p\n",get_pointer(src)); -} - -// If a code block was found to be unmodified (bit was set in -// restore_candidate) and it remains unmodified (bit is clear -// in invalid_code) then move the entries for that 4K page from -// the dirty list to the clean list. -void clean_blocks(u_int page) -{ - struct ll_entry *head; - inv_debug("INV: clean_blocks page=%d\n",page); - head=jump_dirty[page]; - while(head!=NULL) { - if(!invalid_code[head->vaddr>>12]) { - // Don't restore blocks which are about to expire from the cache - if (doesnt_expire_soon(head->addr)) { - if(verify_dirty(head->addr)) { - u_char *start, *end; - //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr); - u_int i; - u_int inv=0; - get_bounds(head->addr, &start, &end); - if (start - rdram < RAM_SIZE) { - for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) { - inv|=invalid_code[i]; - } - } - else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) { - inv=1; - } - if(!inv) { - void *clean_addr = get_clean_addr(head->addr); - if (doesnt_expire_soon(clean_addr)) { - u_int ppage=page; - inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr); - //printf("page=%x, addr=%x\n",page,head->vaddr); - //assert(head->vaddr>>12==(page|0x80000)); - ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr); - struct ht_entry *ht_bin = hash_table_get(head->vaddr); - if (ht_bin->vaddr[0] == head->vaddr) - ht_bin->tcaddr[0] = clean_addr; // Replace existing entry - if (ht_bin->vaddr[1] == head->vaddr) - ht_bin->tcaddr[1] = clean_addr; // Replace existing entry - } - } - } - } - } - head=head->next; - } + //inv_debug("ndrc_add_jump_out: to %p\n",get_pointer(src)); + stat_inc(stat_links); } /* Register allocation */ @@ -1386,18 +1491,19 @@ void clean_blocks(u_int page) static void alloc_reg(struct regstat *cur,int i,signed char reg) { int r,hr; - int preferred_reg = (reg&7); - if(reg==CCREG) preferred_reg=HOST_CCREG; - if(reg==PTEMP||reg==FTEMP) preferred_reg=12; + int preferred_reg = PREFERRED_REG_FIRST + + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1); + if (reg == CCREG) preferred_reg = HOST_CCREG; + if (reg == PTEMP || reg == FTEMP) preferred_reg = 12; + assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS); + assert(reg >= 0); // Don't allocate unused registers if((cur->u>>reg)&1) return; // see if it's already allocated - for(hr=0;hrregmap[hr]==reg) return; - } + if (get_reg(cur->regmap, reg) >= 0) + return; // Keep the same mapping if the register was already allocated in a loop preferred_reg = loop_reg(i,reg,preferred_reg); @@ -1432,28 +1538,47 @@ static void alloc_reg(struct regstat *cur,int i,signed char reg) if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;} } } + // Try to allocate any available register, but prefer // registers that have not been used recently. - if(i>0) { - for(hr=0;hrregmap[hr]==-1) { - if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) { + if (i > 0) { + for (hr = PREFERRED_REG_FIRST; ; ) { + if (cur->regmap[hr] < 0) { + int oldreg = regs[i-1].regmap[hr]; + if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2 + && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2)) + { cur->regmap[hr]=reg; cur->dirty&=~(1<isconst&=~(1<regmap[hr]==-1) { + for (hr = PREFERRED_REG_FIRST; ; ) { + if (cur->regmap[hr] < 0) { cur->regmap[hr]=reg; cur->dirty&=~(1<isconst&=~(1<0) { // Don't evict the cycle count at entry points, otherwise the entry // stub will have to write it. - if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2; - if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP)) hsn[CCREG]=2; + if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2; + if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2; for(j=10;j>=3;j--) { // Alloc preferred register if available if(hsn[r=cur->regmap[preferred_reg]&63]==j) { for(hr=0;hrregmap[hr]&63)==r) { + if(cur->regmap[hr]==r) { cur->regmap[hr]=-1; cur->dirty&=~(1<isconst&=~(1<regmap[hr]==r) { @@ -1573,13 +1698,13 @@ static void alloc_reg_temp(struct regstat *cur,int i,signed char reg) if(i>0) { // Don't evict the cycle count at entry points, otherwise the entry // stub will have to write it. - if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2; - if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP)) hsn[CCREG]=2; + if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2; + if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2; for(j=10;j>=3;j--) { for(r=1;r<=MAXREG;r++) { - if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) { + if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) { for(hr=0;hr2) { if(cur->regmap[hr]==r) { @@ -1615,58 +1740,57 @@ static void alloc_reg_temp(struct regstat *cur,int i,signed char reg) static void mov_alloc(struct regstat *current,int i) { - if (rs1[i] == HIREG || rs1[i] == LOREG) { - // logically this is needed but just won't work, no idea why - //alloc_cc(current,i); // for stalls - //dirty_reg(current,CCREG); + if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) { + alloc_cc(current,i); // for stalls + dirty_reg(current,CCREG); } // Note: Don't need to actually alloc the source registers - //alloc_reg(current,i,rs1[i]); - alloc_reg(current,i,rt1[i]); + //alloc_reg(current,i,dops[i].rs1); + alloc_reg(current,i,dops[i].rt1); - clear_const(current,rs1[i]); - clear_const(current,rt1[i]); - dirty_reg(current,rt1[i]); + clear_const(current,dops[i].rs1); + clear_const(current,dops[i].rt1); + dirty_reg(current,dops[i].rt1); } static void shiftimm_alloc(struct regstat *current,int i) { - if(opcode2[i]<=0x3) // SLL/SRL/SRA + if(dops[i].opcode2<=0x3) // SLL/SRL/SRA { - if(rt1[i]) { - if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); - else lt1[i]=rs1[i]; - alloc_reg(current,i,rt1[i]); - dirty_reg(current,rt1[i]); - if(is_const(current,rs1[i])) { - int v=get_const(current,rs1[i]); - if(opcode2[i]==0x00) set_const(current,rt1[i],v<>imm[i]); - if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]); + if(dops[i].rt1) { + if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); + else dops[i].use_lt1=!!dops[i].rs1; + alloc_reg(current,i,dops[i].rt1); + dirty_reg(current,dops[i].rt1); + if(is_const(current,dops[i].rs1)) { + int v=get_const(current,dops[i].rs1); + if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<>imm[i]); + if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]); } - else clear_const(current,rt1[i]); + else clear_const(current,dops[i].rt1); } } else { - clear_const(current,rs1[i]); - clear_const(current,rt1[i]); + clear_const(current,dops[i].rs1); + clear_const(current,dops[i].rt1); } - if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA + if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA { assert(0); } - if(opcode2[i]==0x3c) // DSLL32 + if(dops[i].opcode2==0x3c) // DSLL32 { assert(0); } - if(opcode2[i]==0x3e) // DSRL32 + if(dops[i].opcode2==0x3e) // DSRL32 { assert(0); } - if(opcode2[i]==0x3f) // DSRA32 + if(dops[i].opcode2==0x3f) // DSRA32 { assert(0); } @@ -1674,125 +1798,128 @@ static void shiftimm_alloc(struct regstat *current,int i) static void shift_alloc(struct regstat *current,int i) { - if(rt1[i]) { - if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV + if(dops[i].rt1) { + if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV { - if(rs1[i]) alloc_reg(current,i,rs1[i]); - if(rs2[i]) alloc_reg(current,i,rs2[i]); - alloc_reg(current,i,rt1[i]); - if(rt1[i]==rs2[i]) { + if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1); + if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2); + alloc_reg(current,i,dops[i].rt1); + if(dops[i].rt1==dops[i].rs2) { alloc_reg_temp(current,i,-1); minimum_free_regs[i]=1; } } else { // DSLLV/DSRLV/DSRAV assert(0); } - clear_const(current,rs1[i]); - clear_const(current,rs2[i]); - clear_const(current,rt1[i]); - dirty_reg(current,rt1[i]); + clear_const(current,dops[i].rs1); + clear_const(current,dops[i].rs2); + clear_const(current,dops[i].rt1); + dirty_reg(current,dops[i].rt1); } } static void alu_alloc(struct regstat *current,int i) { - if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU - if(rt1[i]) { - if(rs1[i]&&rs2[i]) { - alloc_reg(current,i,rs1[i]); - alloc_reg(current,i,rs2[i]); + if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU + if(dops[i].rt1) { + if(dops[i].rs1&&dops[i].rs2) { + alloc_reg(current,i,dops[i].rs1); + alloc_reg(current,i,dops[i].rs2); } else { - if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); - if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]); + if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); + if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2); } - alloc_reg(current,i,rt1[i]); + alloc_reg(current,i,dops[i].rt1); } } - if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU - if(rt1[i]) { - alloc_reg(current,i,rs1[i]); - alloc_reg(current,i,rs2[i]); - alloc_reg(current,i,rt1[i]); + if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU + if(dops[i].rt1) { + alloc_reg(current,i,dops[i].rs1); + alloc_reg(current,i,dops[i].rs2); + alloc_reg(current,i,dops[i].rt1); } } - if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR - if(rt1[i]) { - if(rs1[i]&&rs2[i]) { - alloc_reg(current,i,rs1[i]); - alloc_reg(current,i,rs2[i]); + if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR + if(dops[i].rt1) { + if(dops[i].rs1&&dops[i].rs2) { + alloc_reg(current,i,dops[i].rs1); + alloc_reg(current,i,dops[i].rs2); } else { - if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); - if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]); + if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); + if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2); } - alloc_reg(current,i,rt1[i]); + alloc_reg(current,i,dops[i].rt1); } } - if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU + if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU assert(0); } - clear_const(current,rs1[i]); - clear_const(current,rs2[i]); - clear_const(current,rt1[i]); - dirty_reg(current,rt1[i]); + clear_const(current,dops[i].rs1); + clear_const(current,dops[i].rs2); + clear_const(current,dops[i].rt1); + dirty_reg(current,dops[i].rt1); } static void imm16_alloc(struct regstat *current,int i) { - if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); - else lt1[i]=rs1[i]; - if(rt1[i]) alloc_reg(current,i,rt1[i]); - if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU + if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); + else dops[i].use_lt1=!!dops[i].rs1; + if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1); + if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU assert(0); } - else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU - clear_const(current,rs1[i]); - clear_const(current,rt1[i]); + else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU + clear_const(current,dops[i].rs1); + clear_const(current,dops[i].rt1); } - else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI - if(is_const(current,rs1[i])) { - int v=get_const(current,rs1[i]); - if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]); - if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]); - if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]); + else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI + if(is_const(current,dops[i].rs1)) { + int v=get_const(current,dops[i].rs1); + if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]); + if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]); + if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]); } - else clear_const(current,rt1[i]); + else clear_const(current,dops[i].rt1); } - else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU - if(is_const(current,rs1[i])) { - int v=get_const(current,rs1[i]); - set_const(current,rt1[i],v+imm[i]); + else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU + if(is_const(current,dops[i].rs1)) { + int v=get_const(current,dops[i].rs1); + set_const(current,dops[i].rt1,v+imm[i]); } - else clear_const(current,rt1[i]); + else clear_const(current,dops[i].rt1); } else { - set_const(current,rt1[i],imm[i]<<16); // LUI + set_const(current,dops[i].rt1,imm[i]<<16); // LUI } - dirty_reg(current,rt1[i]); + dirty_reg(current,dops[i].rt1); } static void load_alloc(struct regstat *current,int i) { - clear_const(current,rt1[i]); - //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt? - if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register - if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); - if(rt1[i]&&!((current->u>>rt1[i])&1)) { - alloc_reg(current,i,rt1[i]); - assert(get_reg(current->regmap,rt1[i])>=0); - if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD + clear_const(current,dops[i].rt1); + //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt? + if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register + if (needed_again(dops[i].rs1, i)) + alloc_reg(current, i, dops[i].rs1); + if (ram_offset) + alloc_reg(current, i, ROREG); + if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) { + alloc_reg(current,i,dops[i].rt1); + assert(get_reg(current->regmap,dops[i].rt1)>=0); + if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD { assert(0); } - else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR + else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR { assert(0); } - dirty_reg(current,rt1[i]); + dirty_reg(current,dops[i].rt1); // LWL/LWR need a temporary register for the old value - if(opcode[i]==0x22||opcode[i]==0x26) + if(dops[i].opcode==0x22||dops[i].opcode==0x26) { alloc_reg(current,i,FTEMP); alloc_reg_temp(current,i,-1); @@ -1803,33 +1930,35 @@ static void load_alloc(struct regstat *current,int i) { // Load to r0 or unneeded register (dummy load) // but we still need a register to calculate the address - if(opcode[i]==0x22||opcode[i]==0x26) + if(dops[i].opcode==0x22||dops[i].opcode==0x26) { alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary } alloc_reg_temp(current,i,-1); minimum_free_regs[i]=1; - if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR + if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR { assert(0); } } } -void store_alloc(struct regstat *current,int i) +static void store_alloc(struct regstat *current,int i) { - clear_const(current,rs2[i]); - if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary - if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); - alloc_reg(current,i,rs2[i]); - if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD + clear_const(current,dops[i].rs2); + if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary + if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); + alloc_reg(current,i,dops[i].rs2); + if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD assert(0); } + if (ram_offset) + alloc_reg(current, i, ROREG); #if defined(HOST_IMM8) // On CPUs without 32-bit immediates we need a pointer to invalid_code - else alloc_reg(current,i,INVCP); + alloc_reg(current, i, INVCP); #endif - if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR + if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR alloc_reg(current,i,FTEMP); } // We need a temporary register for address generation @@ -1837,33 +1966,22 @@ void store_alloc(struct regstat *current,int i) minimum_free_regs[i]=1; } -void c1ls_alloc(struct regstat *current,int i) +static void c1ls_alloc(struct regstat *current,int i) { - //clear_const(current,rs1[i]); // FIXME - clear_const(current,rt1[i]); - if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); + clear_const(current,dops[i].rt1); alloc_reg(current,i,CSREG); // Status - alloc_reg(current,i,FTEMP); - if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1 - assert(0); - } - #if defined(HOST_IMM8) - // On CPUs without 32-bit immediates we need a pointer to invalid_code - else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1 - alloc_reg(current,i,INVCP); - #endif - // We need a temporary register for address generation - alloc_reg_temp(current,i,-1); } -void c2ls_alloc(struct regstat *current,int i) +static void c2ls_alloc(struct regstat *current,int i) { - clear_const(current,rt1[i]); - if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]); + clear_const(current,dops[i].rt1); + if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); alloc_reg(current,i,FTEMP); + if (ram_offset) + alloc_reg(current, i, ROREG); #if defined(HOST_IMM8) // On CPUs without 32-bit immediates we need a pointer to invalid_code - if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2 + if (dops[i].opcode == 0x3a) // SWC2 alloc_reg(current,i,INVCP); #endif // We need a temporary register for address generation @@ -1872,7 +1990,7 @@ void c2ls_alloc(struct regstat *current,int i) } #ifndef multdiv_alloc -void multdiv_alloc(struct regstat *current,int i) +static void multdiv_alloc(struct regstat *current,int i) { // case 0x18: MULT // case 0x19: MULTU @@ -1882,19 +2000,19 @@ void multdiv_alloc(struct regstat *current,int i) // case 0x1D: DMULTU // case 0x1E: DDIV // case 0x1F: DDIVU - clear_const(current,rs1[i]); - clear_const(current,rs2[i]); + clear_const(current,dops[i].rs1); + clear_const(current,dops[i].rs2); alloc_cc(current,i); // for stalls - if(rs1[i]&&rs2[i]) + if(dops[i].rs1&&dops[i].rs2) { - if((opcode2[i]&4)==0) // 32-bit + if((dops[i].opcode2&4)==0) // 32-bit { current->u&=~(1LL<u&=~(1LL< 3) // MTC2/CTC2 + else if (dops[i].opcode2 > 3) // MTC2/CTC2 { - if(rs1[i]){ - clear_const(current,rs1[i]); - alloc_reg(current,i,rs1[i]); + if(dops[i].rs1){ + clear_const(current,dops[i].rs1); + alloc_reg(current,i,dops[i].rs1); } else { current->u&=~1LL; @@ -1976,14 +2094,14 @@ static void cop2_alloc(struct regstat *current,int i) minimum_free_regs[i]=1; } -void c2op_alloc(struct regstat *current,int i) +static void c2op_alloc(struct regstat *current,int i) { alloc_cc(current,i); // for stalls dirty_reg(current,CCREG); alloc_reg_temp(current,i,-1); } -void syscall_alloc(struct regstat *current,int i) +static void syscall_alloc(struct regstat *current,int i) { alloc_cc(current,i); dirty_reg(current,CCREG); @@ -1992,20 +2110,15 @@ void syscall_alloc(struct regstat *current,int i) current->isconst=0; } -void delayslot_alloc(struct regstat *current,int i) +static void delayslot_alloc(struct regstat *current,int i) { - switch(itype[i]) { + switch(dops[i].itype) { case UJUMP: case CJUMP: case SJUMP: case RJUMP: case SYSCALL: case HLECALL: - case SPAN: - assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort(); - SysPrintf("Disabled speculative precompilation\n"); - stop_after_jal=1; - break; case IMM16: imm16_alloc(current,i); break; @@ -2052,42 +2165,6 @@ void delayslot_alloc(struct regstat *current,int i) } } -// Special case where a branch and delay slot span two pages in virtual memory -static void pagespan_alloc(struct regstat *current,int i) -{ - current->isconst=0; - current->wasconst=0; - regs[i].wasconst=0; - minimum_free_regs[i]=HOST_REGS; - alloc_all(current,i); - alloc_cc(current,i); - dirty_reg(current,CCREG); - if(opcode[i]==3) // JAL - { - alloc_reg(current,i,31); - dirty_reg(current,31); - } - if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR - { - alloc_reg(current,i,rs1[i]); - if (rt1[i]!=0) { - alloc_reg(current,i,rt1[i]); - dirty_reg(current,rt1[i]); - } - } - if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL - { - if(rs1[i]) alloc_reg(current,i,rs1[i]); - if(rs2[i]) alloc_reg(current,i,rs2[i]); - } - else - if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL - { - if(rs1[i]) alloc_reg(current,i,rs1[i]); - } - //else ... -} - static void add_stub(enum stub_type type, void *addr, void *retaddr, u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e) { @@ -2110,12 +2187,12 @@ static void add_stub_r(enum stub_type type, void *addr, void *retaddr, } // Write out a single register -static void wb_register(signed char r,signed char regmap[],uint64_t dirty) +static void wb_register(signed char r, const signed char regmap[], uint64_t dirty) { int hr; for(hr=0;hr>hr)&1) { assert(regmap[hr]<64); emit_storereg(r,hr); @@ -2128,23 +2205,13 @@ static void wb_register(signed char r,signed char regmap[],uint64_t dirty) static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u) { //if(dirty_pre==dirty) return; - int hr,reg; - for(hr=0;hr>(reg&63))&1) { - if(reg>0) { - if(((dirty_pre&~dirty)>>hr)&1) { - if(reg>0&®<34) { - emit_storereg(reg,hr); - } - else if(reg>=64) { - assert(0); - } - } - } - } - } + int hr, r; + for (hr = 0; hr < HOST_REGS; hr++) { + r = pre[hr]; + if (r < 1 || r > 33 || ((u >> r) & 1)) + continue; + if (((dirty_pre & ~dirty) >> hr) & 1) + emit_storereg(r, hr); } } @@ -2165,71 +2232,71 @@ static void pass_args(int a0, int a1) } } -static void alu_assemble(int i,struct regstat *i_regs) +static void alu_assemble(int i, const struct regstat *i_regs) { - if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU - if(rt1[i]) { + if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU + if(dops[i].rt1) { signed char s1,s2,t; - t=get_reg(i_regs->regmap,rt1[i]); + t=get_reg(i_regs->regmap,dops[i].rt1); if(t>=0) { - s1=get_reg(i_regs->regmap,rs1[i]); - s2=get_reg(i_regs->regmap,rs2[i]); - if(rs1[i]&&rs2[i]) { + s1=get_reg(i_regs->regmap,dops[i].rs1); + s2=get_reg(i_regs->regmap,dops[i].rs2); + if(dops[i].rs1&&dops[i].rs2) { assert(s1>=0); assert(s2>=0); - if(opcode2[i]&2) emit_sub(s1,s2,t); + if(dops[i].opcode2&2) emit_sub(s1,s2,t); else emit_add(s1,s2,t); } - else if(rs1[i]) { + else if(dops[i].rs1) { if(s1>=0) emit_mov(s1,t); - else emit_loadreg(rs1[i],t); + else emit_loadreg(dops[i].rs1,t); } - else if(rs2[i]) { + else if(dops[i].rs2) { if(s2>=0) { - if(opcode2[i]&2) emit_neg(s2,t); + if(dops[i].opcode2&2) emit_neg(s2,t); else emit_mov(s2,t); } else { - emit_loadreg(rs2[i],t); - if(opcode2[i]&2) emit_neg(t,t); + emit_loadreg(dops[i].rs2,t); + if(dops[i].opcode2&2) emit_neg(t,t); } } else emit_zeroreg(t); } } } - if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU + if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU assert(0); } - if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU - if(rt1[i]) { + if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU + if(dops[i].rt1) { signed char s1l,s2l,t; { - t=get_reg(i_regs->regmap,rt1[i]); + t=get_reg(i_regs->regmap,dops[i].rt1); //assert(t>=0); if(t>=0) { - s1l=get_reg(i_regs->regmap,rs1[i]); - s2l=get_reg(i_regs->regmap,rs2[i]); - if(rs2[i]==0) // rxregmap,dops[i].rs1); + s2l=get_reg(i_regs->regmap,dops[i].rs2); + if(dops[i].rs2==0) // rx=0); emit_shrimm(s1l,31,t); } else // SLTU (unsigned can not be less than zero, 0<0) emit_zeroreg(t); } - else if(rs1[i]==0) // r0=0); - if(opcode2[i]==0x2a) // SLT + if(dops[i].opcode2==0x2a) // SLT emit_set_gz32(s2l,t); else // SLTU (set if not zero) emit_set_nz32(s2l,t); } else{ assert(s1l>=0);assert(s2l>=0); - if(opcode2[i]==0x2a) // SLT + if(dops[i].opcode2==0x2a) // SLT emit_set_if_less32(s1l,s2l,t); else // SLTU emit_set_if_carry32(s1l,s2l,t); @@ -2238,61 +2305,61 @@ static void alu_assemble(int i,struct regstat *i_regs) } } } - if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR - if(rt1[i]) { + if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR + if(dops[i].rt1) { signed char s1l,s2l,tl; - tl=get_reg(i_regs->regmap,rt1[i]); + tl=get_reg(i_regs->regmap,dops[i].rt1); { if(tl>=0) { - s1l=get_reg(i_regs->regmap,rs1[i]); - s2l=get_reg(i_regs->regmap,rs2[i]); - if(rs1[i]&&rs2[i]) { + s1l=get_reg(i_regs->regmap,dops[i].rs1); + s2l=get_reg(i_regs->regmap,dops[i].rs2); + if(dops[i].rs1&&dops[i].rs2) { assert(s1l>=0); assert(s2l>=0); - if(opcode2[i]==0x24) { // AND + if(dops[i].opcode2==0x24) { // AND emit_and(s1l,s2l,tl); } else - if(opcode2[i]==0x25) { // OR + if(dops[i].opcode2==0x25) { // OR emit_or(s1l,s2l,tl); } else - if(opcode2[i]==0x26) { // XOR + if(dops[i].opcode2==0x26) { // XOR emit_xor(s1l,s2l,tl); } else - if(opcode2[i]==0x27) { // NOR + if(dops[i].opcode2==0x27) { // NOR emit_or(s1l,s2l,tl); emit_not(tl,tl); } } else { - if(opcode2[i]==0x24) { // AND + if(dops[i].opcode2==0x24) { // AND emit_zeroreg(tl); } else - if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR - if(rs1[i]){ + if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR + if(dops[i].rs1){ if(s1l>=0) emit_mov(s1l,tl); - else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry? + else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry? } else - if(rs2[i]){ + if(dops[i].rs2){ if(s2l>=0) emit_mov(s2l,tl); - else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry? + else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry? } else emit_zeroreg(tl); } else - if(opcode2[i]==0x27) { // NOR - if(rs1[i]){ + if(dops[i].opcode2==0x27) { // NOR + if(dops[i].rs1){ if(s1l>=0) emit_not(s1l,tl); else { - emit_loadreg(rs1[i],tl); + emit_loadreg(dops[i].rs1,tl); emit_not(tl,tl); } } else - if(rs2[i]){ + if(dops[i].rs2){ if(s2l>=0) emit_not(s2l,tl); else { - emit_loadreg(rs2[i],tl); + emit_loadreg(dops[i].rs2,tl); emit_not(tl,tl); } } @@ -2305,12 +2372,12 @@ static void alu_assemble(int i,struct regstat *i_regs) } } -void imm16_assemble(int i,struct regstat *i_regs) +static void imm16_assemble(int i, const struct regstat *i_regs) { - if (opcode[i]==0x0f) { // LUI - if(rt1[i]) { + if (dops[i].opcode==0x0f) { // LUI + if(dops[i].rt1) { signed char t; - t=get_reg(i_regs->regmap,rt1[i]); + t=get_reg(i_regs->regmap,dops[i].rt1); //assert(t>=0); if(t>=0) { if(!((i_regs->isconst>>t)&1)) @@ -2318,18 +2385,18 @@ void imm16_assemble(int i,struct regstat *i_regs) } } } - if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU - if(rt1[i]) { + if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU + if(dops[i].rt1) { signed char s,t; - t=get_reg(i_regs->regmap,rt1[i]); - s=get_reg(i_regs->regmap,rs1[i]); - if(rs1[i]) { + t=get_reg(i_regs->regmap,dops[i].rt1); + s=get_reg(i_regs->regmap,dops[i].rs1); + if(dops[i].rs1) { //assert(t>=0); //assert(s>=0); if(t>=0) { if(!((i_regs->isconst>>t)&1)) { if(s<0) { - if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); + if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); emit_addimm(t,imm[i],t); }else{ if(!((i_regs->wasconst>>s)&1)) @@ -2347,13 +2414,13 @@ void imm16_assemble(int i,struct regstat *i_regs) } } } - if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU - if(rt1[i]) { + if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU + if(dops[i].rt1) { signed char sl,tl; - tl=get_reg(i_regs->regmap,rt1[i]); - sl=get_reg(i_regs->regmap,rs1[i]); + tl=get_reg(i_regs->regmap,dops[i].rt1); + sl=get_reg(i_regs->regmap,dops[i].rs1); if(tl>=0) { - if(rs1[i]) { + if(dops[i].rs1) { assert(sl>=0); emit_addimm(sl,imm[i],tl); } else { @@ -2362,18 +2429,18 @@ void imm16_assemble(int i,struct regstat *i_regs) } } } - else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU - if(rt1[i]) { - //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug + else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU + if(dops[i].rt1) { + //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug signed char sl,t; - t=get_reg(i_regs->regmap,rt1[i]); - sl=get_reg(i_regs->regmap,rs1[i]); + t=get_reg(i_regs->regmap,dops[i].rt1); + sl=get_reg(i_regs->regmap,dops[i].rs1); //assert(t>=0); if(t>=0) { - if(rs1[i]>0) { - if(opcode[i]==0x0a) { // SLTI + if(dops[i].rs1>0) { + if(dops[i].opcode==0x0a) { // SLTI if(sl<0) { - if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); + if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); emit_slti32(t,imm[i],t); }else{ emit_slti32(sl,imm[i],t); @@ -2381,7 +2448,7 @@ void imm16_assemble(int i,struct regstat *i_regs) } else { // SLTIU if(sl<0) { - if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); + if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); emit_sltiu32(t,imm[i],t); }else{ emit_sltiu32(sl,imm[i],t); @@ -2390,7 +2457,7 @@ void imm16_assemble(int i,struct regstat *i_regs) }else{ // SLTI(U) with r0 is just stupid, // nonetheless examples can be found - if(opcode[i]==0x0a) // SLTI + if(dops[i].opcode==0x0a) // SLTI if(0=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI - if(rt1[i]) { + else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI + if(dops[i].rt1) { signed char sl,tl; - tl=get_reg(i_regs->regmap,rt1[i]); - sl=get_reg(i_regs->regmap,rs1[i]); + tl=get_reg(i_regs->regmap,dops[i].rt1); + sl=get_reg(i_regs->regmap,dops[i].rs1); if(tl>=0 && !((i_regs->isconst>>tl)&1)) { - if(opcode[i]==0x0c) //ANDI + if(dops[i].opcode==0x0c) //ANDI { - if(rs1[i]) { + if(dops[i].rs1) { if(sl<0) { - if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl); + if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl); emit_andimm(tl,imm[i],tl); }else{ if(!((i_regs->wasconst>>sl)&1)) @@ -2426,11 +2493,11 @@ void imm16_assemble(int i,struct regstat *i_regs) } else { - if(rs1[i]) { + if(dops[i].rs1) { if(sl<0) { - if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl); + if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl); } - if(opcode[i]==0x0d) { // ORI + if(dops[i].opcode==0x0d) { // ORI if(sl<0) { emit_orimm(tl,imm[i],tl); }else{ @@ -2440,7 +2507,7 @@ void imm16_assemble(int i,struct regstat *i_regs) emit_movimm(constmap[i][sl]|imm[i],tl); } } - if(opcode[i]==0x0e) { // XORI + if(dops[i].opcode==0x0e) { // XORI if(sl<0) { emit_xorimm(tl,imm[i],tl); }else{ @@ -2460,33 +2527,33 @@ void imm16_assemble(int i,struct regstat *i_regs) } } -void shiftimm_assemble(int i,struct regstat *i_regs) +static void shiftimm_assemble(int i, const struct regstat *i_regs) { - if(opcode2[i]<=0x3) // SLL/SRL/SRA + if(dops[i].opcode2<=0x3) // SLL/SRL/SRA { - if(rt1[i]) { + if(dops[i].rt1) { signed char s,t; - t=get_reg(i_regs->regmap,rt1[i]); - s=get_reg(i_regs->regmap,rs1[i]); + t=get_reg(i_regs->regmap,dops[i].rt1); + s=get_reg(i_regs->regmap,dops[i].rs1); //assert(t>=0); if(t>=0&&!((i_regs->isconst>>t)&1)){ - if(rs1[i]==0) + if(dops[i].rs1==0) { emit_zeroreg(t); } else { - if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); + if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); if(imm[i]) { - if(opcode2[i]==0) // SLL + if(dops[i].opcode2==0) // SLL { emit_shlimm(s<0?t:s,imm[i],t); } - if(opcode2[i]==2) // SRL + if(dops[i].opcode2==2) // SRL { emit_shrimm(s<0?t:s,imm[i],t); } - if(opcode2[i]==3) // SRA + if(dops[i].opcode2==3) // SRA { emit_sarimm(s<0?t:s,imm[i],t); } @@ -2496,50 +2563,50 @@ void shiftimm_assemble(int i,struct regstat *i_regs) } } } - //emit_storereg(rt1[i],t); //DEBUG + //emit_storereg(dops[i].rt1,t); //DEBUG } } - if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA + if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA { assert(0); } - if(opcode2[i]==0x3c) // DSLL32 + if(dops[i].opcode2==0x3c) // DSLL32 { assert(0); } - if(opcode2[i]==0x3e) // DSRL32 + if(dops[i].opcode2==0x3e) // DSRL32 { assert(0); } - if(opcode2[i]==0x3f) // DSRA32 + if(dops[i].opcode2==0x3f) // DSRA32 { assert(0); } } #ifndef shift_assemble -static void shift_assemble(int i,struct regstat *i_regs) +static void shift_assemble(int i, const struct regstat *i_regs) { signed char s,t,shift; - if (rt1[i] == 0) + if (dops[i].rt1 == 0) return; - assert(opcode2[i]<=0x07); // SLLV/SRLV/SRAV - t = get_reg(i_regs->regmap, rt1[i]); - s = get_reg(i_regs->regmap, rs1[i]); - shift = get_reg(i_regs->regmap, rs2[i]); + assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV + t = get_reg(i_regs->regmap, dops[i].rt1); + s = get_reg(i_regs->regmap, dops[i].rs1); + shift = get_reg(i_regs->regmap, dops[i].rs2); if (t < 0) return; - if(rs1[i]==0) + if(dops[i].rs1==0) emit_zeroreg(t); - else if(rs2[i]==0) { + else if(dops[i].rs2==0) { assert(s>=0); if(s!=t) emit_mov(s,t); } else { host_tempreg_acquire(); emit_andimm(shift,31,HOST_TEMPREG); - switch(opcode2[i]) { + switch(dops[i].opcode2) { case 4: // SLLV emit_shl(s,HOST_TEMPREG,t); break; @@ -2584,11 +2651,25 @@ static int get_ptr_mem_type(u_int a) return MTYPE_8000; } -static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override) +static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free) +{ + int r = get_reg(i_regs->regmap, ROREG); + if (r < 0 && host_tempreg_free) { + host_tempreg_acquire(); + emit_loadreg(ROREG, r = HOST_TEMPREG); + } + if (r < 0) + abort(); + return r; +} + +static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs, + int addr, int *offset_reg, int *addr_reg_override) { void *jaddr = NULL; - int type=0; - int mr=rs1[i]; + int type = 0; + int mr = dops[i].rs1; + *offset_reg = -1; if(((smrv_strong|smrv_weak)>>mr)&1) { type=get_ptr_mem_type(smrv[mr]); //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type); @@ -2632,22 +2713,19 @@ static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override) } } - if(type==0) + if (type == 0) // need ram check { emit_cmpimm(addr,RAM_SIZE); - jaddr=out; + jaddr = out; #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK // Hint to branch predictor that the branch is unlikely to be taken - if(rs1[i]>=28) + if (dops[i].rs1 >= 28) emit_jno_unlikely(0); else #endif emit_jno(0); - if(ram_offset!=0) { - host_tempreg_acquire(); - emit_addimm(addr,ram_offset,HOST_TEMPREG); - addr=*addr_reg_override=HOST_TEMPREG; - } + if (ram_offset != 0) + *offset_reg = get_ro_reg(i_regs, 0); } return jaddr; @@ -2657,9 +2735,10 @@ static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override) static void *get_direct_memhandler(void *table, u_int addr, enum stub_type type, uintptr_t *addr_host) { + uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1); uintptr_t l1, l2 = 0; l1 = ((uintptr_t *)table)[addr>>12]; - if ((l1 & (1ul << (sizeof(l1)*8-1))) == 0) { + if (!(l1 & msb)) { uintptr_t v = l1 << 1; *addr_host = v + addr; return NULL; @@ -2669,10 +2748,10 @@ static void *get_direct_memhandler(void *table, u_int addr, if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB) l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)]; else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB) - l2=((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2]; + l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2]; else - l2=((uintptr_t *)l1)[(addr&0xfff)/4]; - if ((l2 & (1<<31)) == 0) { + l2 = ((uintptr_t *)l1)[(addr&0xfff)/4]; + if (!(l2 & msb)) { uintptr_t v = l2 << 1; *addr_host = v + (addr&0xfff); return NULL; @@ -2709,16 +2788,59 @@ static int reglist_find_free(u_int reglist) return __builtin_ctz(free_regs); } -static void load_assemble(int i, const struct regstat *i_regs) +static void do_load_word(int a, int rt, int offset_reg) +{ + if (offset_reg >= 0) + emit_ldr_dualindexed(offset_reg, a, rt); + else + emit_readword_indexed(0, a, rt); +} + +static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a) +{ + if (offset_reg < 0) { + emit_writeword_indexed(rt, ofs, a); + return; + } + if (ofs != 0) + emit_addimm(a, ofs, a); + emit_str_dualindexed(offset_reg, a, rt); + if (ofs != 0 && preseve_a) + emit_addimm(a, -ofs, a); +} + +static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a) +{ + if (offset_reg < 0) { + emit_writehword_indexed(rt, ofs, a); + return; + } + if (ofs != 0) + emit_addimm(a, ofs, a); + emit_strh_dualindexed(offset_reg, a, rt); + if (ofs != 0 && preseve_a) + emit_addimm(a, -ofs, a); +} + +static void do_store_byte(int a, int rt, int offset_reg) +{ + if (offset_reg >= 0) + emit_strb_dualindexed(offset_reg, a, rt); + else + emit_writebyte_indexed(rt, 0, a); +} + +static void load_assemble(int i, const struct regstat *i_regs, int ccadj_) { int s,tl,addr; int offset; void *jaddr=0; int memtarget=0,c=0; - int fastio_reg_override=-1; + int offset_reg = -1; + int fastio_reg_override = -1; u_int reglist=get_host_reglist(i_regs->regmap); - tl=get_reg(i_regs->regmap,rt1[i]); - s=get_reg(i_regs->regmap,rs1[i]); + tl=get_reg(i_regs->regmap,dops[i].rt1); + s=get_reg(i_regs->regmap,dops[i].rs1); offset=imm[i]; if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<=0) { @@ -2731,16 +2853,16 @@ static void load_assemble(int i, const struct regstat *i_regs) //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset); // FIXME: Even if the load is a NOP, we should check for pagefaults... if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)) - ||rt1[i]==0) { + ||dops[i].rt1==0) { // could be FIFO, must perform the read // ||dummy read assem_debug("(forced read)\n"); - tl=get_reg(i_regs->regmap,-1); + tl=get_reg_temp(i_regs->regmap); assert(tl>=0); } if(offset||s<0||c) addr=tl; else addr=s; - //if(tl<0) tl=get_reg(i_regs->regmap,-1); + //if(tl<0) tl=get_reg_temp(i_regs->regmap); if(tl>=0) { //printf("load_assemble: c=%d\n",c); //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset); @@ -2749,114 +2871,129 @@ static void load_assemble(int i, const struct regstat *i_regs) if(!c) { #ifdef R29_HACK // Strmnnrmn's speed hack - if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE) + if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE) #endif { - jaddr=emit_fastpath_cmp_jump(i,addr,&fastio_reg_override); + jaddr = emit_fastpath_cmp_jump(i, i_regs, addr, + &offset_reg, &fastio_reg_override); } } - else if(ram_offset&&memtarget) { - host_tempreg_acquire(); - emit_addimm(addr,ram_offset,HOST_TEMPREG); - fastio_reg_override=HOST_TEMPREG; + else if (ram_offset && memtarget) { + offset_reg = get_ro_reg(i_regs, 0); } - int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg - if (opcode[i]==0x20) { // LB + int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg + switch (dops[i].opcode) { + case 0x20: // LB if(!c||memtarget) { if(!dummy) { - { - int x=0,a=tl; - if(!c) a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; + int a = tl; + if (!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; - emit_movsbl_indexed(x,a,tl); - } + if (offset_reg >= 0) + emit_ldrsb_dualindexed(offset_reg, a, tl); + else + emit_movsbl_indexed(0, a, tl); } if(jaddr) - add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); + add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); } else - inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); - } - if (opcode[i]==0x21) { // LH + inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); + break; + case 0x21: // LH if(!c||memtarget) { if(!dummy) { - int x=0,a=tl; - if(!c) a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_movswl_indexed(x,a,tl); + int a = tl; + if (!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + if (offset_reg >= 0) + emit_ldrsh_dualindexed(offset_reg, a, tl); + else + emit_movswl_indexed(0, a, tl); } if(jaddr) - add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); + add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); } else - inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); - } - if (opcode[i]==0x23) { // LW + inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); + break; + case 0x23: // LW if(!c||memtarget) { if(!dummy) { - int a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_readword_indexed(0,a,tl); + int a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_load_word(a, tl, offset_reg); } if(jaddr) - add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); + add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); } else - inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); - } - if (opcode[i]==0x24) { // LBU + inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); + break; + case 0x24: // LBU if(!c||memtarget) { if(!dummy) { - int x=0,a=tl; - if(!c) a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; + int a = tl; + if (!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; - emit_movzbl_indexed(x,a,tl); + if (offset_reg >= 0) + emit_ldrb_dualindexed(offset_reg, a, tl); + else + emit_movzbl_indexed(0, a, tl); } if(jaddr) - add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); + add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); } else - inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); - } - if (opcode[i]==0x25) { // LHU + inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); + break; + case 0x25: // LHU if(!c||memtarget) { if(!dummy) { - int x=0,a=tl; - if(!c) a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_movzwl_indexed(x,a,tl); + int a = tl; + if(!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + if (offset_reg >= 0) + emit_ldrh_dualindexed(offset_reg, a, tl); + else + emit_movzwl_indexed(0, a, tl); } if(jaddr) - add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); + add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); } else - inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); - } - if (opcode[i]==0x27) { // LWU - assert(0); - } - if (opcode[i]==0x37) { // LD + inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); + break; + case 0x27: // LWU + case 0x37: // LD + default: assert(0); } } - if (fastio_reg_override == HOST_TEMPREG) + if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) host_tempreg_release(); } #ifndef loadlr_assemble -static void loadlr_assemble(int i, const struct regstat *i_regs) +static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_) { int s,tl,temp,temp2,addr; int offset; void *jaddr=0; int memtarget=0,c=0; - int fastio_reg_override=-1; + int offset_reg = -1; + int fastio_reg_override = -1; u_int reglist=get_host_reglist(i_regs->regmap); - tl=get_reg(i_regs->regmap,rt1[i]); - s=get_reg(i_regs->regmap,rs1[i]); - temp=get_reg(i_regs->regmap,-1); + tl=get_reg(i_regs->regmap,dops[i].rt1); + s=get_reg(i_regs->regmap,dops[i].rs1); + temp=get_reg_temp(i_regs->regmap); temp2=get_reg(i_regs->regmap,FTEMP); addr=get_reg(i_regs->regmap,AGEN1+(i&1)); assert(addr<0); @@ -2872,43 +3009,44 @@ static void loadlr_assemble(int i, const struct regstat *i_regs) } if(!c) { emit_shlimm(addr,3,temp); - if (opcode[i]==0x22||opcode[i]==0x26) { + if (dops[i].opcode==0x22||dops[i].opcode==0x26) { emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR }else{ emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR } - jaddr=emit_fastpath_cmp_jump(i,temp2,&fastio_reg_override); + jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2, + &offset_reg, &fastio_reg_override); } else { - if(ram_offset&&memtarget) { - host_tempreg_acquire(); - emit_addimm(temp2,ram_offset,HOST_TEMPREG); - fastio_reg_override=HOST_TEMPREG; + if (ram_offset && memtarget) { + offset_reg = get_ro_reg(i_regs, 0); } - if (opcode[i]==0x22||opcode[i]==0x26) { + if (dops[i].opcode==0x22||dops[i].opcode==0x26) { emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR }else{ emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR } } - if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR + if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR if(!c||memtarget) { - int a=temp2; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_readword_indexed(0,a,temp2); - if(fastio_reg_override==HOST_TEMPREG) host_tempreg_release(); - if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj[i],reglist); + int a = temp2; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_load_word(a, temp2, offset_reg); + if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) + host_tempreg_release(); + if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist); } else - inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist); - if(rt1[i]) { + inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist); + if(dops[i].rt1) { assert(tl>=0); emit_andimm(temp,24,temp); - if (opcode[i]==0x22) // LWL + if (dops[i].opcode==0x22) // LWL emit_xorimm(temp,24,temp); host_tempreg_acquire(); emit_movimm(-1,HOST_TEMPREG); - if (opcode[i]==0x26) { + if (dops[i].opcode==0x26) { emit_shr(temp2,temp,temp2); emit_bic_lsr(tl,HOST_TEMPREG,temp,tl); }else{ @@ -2918,29 +3056,30 @@ static void loadlr_assemble(int i, const struct regstat *i_regs) host_tempreg_release(); emit_or(temp2,tl,tl); } - //emit_storereg(rt1[i],tl); // DEBUG + //emit_storereg(dops[i].rt1,tl); // DEBUG } - if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR + if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR assert(0); } } #endif -void store_assemble(int i, const struct regstat *i_regs) +static void store_assemble(int i, const struct regstat *i_regs, int ccadj_) { int s,tl; int addr,temp; int offset; void *jaddr=0; - enum stub_type type; + enum stub_type type=0; int memtarget=0,c=0; int agr=AGEN1+(i&1); - int fastio_reg_override=-1; + int offset_reg = -1; + int fastio_reg_override = -1; u_int reglist=get_host_reglist(i_regs->regmap); - tl=get_reg(i_regs->regmap,rs2[i]); - s=get_reg(i_regs->regmap,rs1[i]); + tl=get_reg(i_regs->regmap,dops[i].rs2); + s=get_reg(i_regs->regmap,dops[i].rs1); temp=get_reg(i_regs->regmap,agr); - if(temp<0) temp=get_reg(i_regs->regmap,-1); + if(temp<0) temp=get_reg_temp(i_regs->regmap); offset=imm[i]; if(s>=0) { c=(i_regs->wasconst>>s)&1; @@ -2953,54 +3092,57 @@ void store_assemble(int i, const struct regstat *i_regs) if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<=0) a=fastio_reg_override; - emit_writebyte_indexed(tl,x,a); - } - type=STOREB_STUB; - } - if (opcode[i]==0x29) { // SH + int a = temp; + if (!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_store_byte(a, tl, offset_reg); + } + type = STOREB_STUB; + break; + case 0x29: // SH if(!c||memtarget) { - int x=0,a=temp; - if(!c) a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_writehword_indexed(tl,x,a); - } - type=STOREH_STUB; - } - if (opcode[i]==0x2B) { // SW + int a = temp; + if (!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_store_hword(a, 0, tl, offset_reg, 1); + } + type = STOREH_STUB; + break; + case 0x2B: // SW if(!c||memtarget) { - int a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_writeword_indexed(tl,0,a); - } - type=STOREW_STUB; - } - if (opcode[i]==0x3F) { // SD + int a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_store_word(a, 0, tl, offset_reg, 1); + } + type = STOREW_STUB; + break; + case 0x3F: // SD + default: assert(0); - type=STORED_STUB; } - if(fastio_reg_override==HOST_TEMPREG) + if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) host_tempreg_release(); if(jaddr) { // PCSX store handlers don't check invcode again reglist|=1<waswritten&(1<waswritten&(1<regmap,rs2[i],ccadj[i],reglist); + inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist); } // basic current block modification detection.. // not looking back as that should be in mips cache already @@ -3041,27 +3183,28 @@ void store_assemble(int i, const struct regstat *i_regs) emit_movimm(start+i*4+4,0); emit_writeword(0,&pcaddr); emit_addimm(HOST_CCREG,2,HOST_CCREG); - emit_far_call(get_addr_ht); + emit_far_call(ndrc_get_addr_ht); emit_jmpreg(0); } } } -static void storelr_assemble(int i, const struct regstat *i_regs) +static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_) { int s,tl; int temp; int offset; void *jaddr=0; - void *case1, *case2, *case3; + void *case1, *case23, *case3; void *done0, *done1, *done2; int memtarget=0,c=0; int agr=AGEN1+(i&1); + int offset_reg = -1; u_int reglist=get_host_reglist(i_regs->regmap); - tl=get_reg(i_regs->regmap,rs2[i]); - s=get_reg(i_regs->regmap,rs1[i]); + tl=get_reg(i_regs->regmap,dops[i].rs2); + s=get_reg(i_regs->regmap,dops[i].rs1); temp=get_reg(i_regs->regmap,agr); - if(temp<0) temp=get_reg(i_regs->regmap,-1); + if(temp<0) temp=get_reg_temp(i_regs->regmap); offset=imm[i]; if(s>=0) { c=(i_regs->isconst>>s)&1; @@ -3079,91 +3222,90 @@ static void storelr_assemble(int i, const struct regstat *i_regs) } else { - if(!memtarget||!rs1[i]) { + if(!memtarget||!dops[i].rs1) { jaddr=out; emit_jmp(0); } } - if(ram_offset) - emit_addimm_no_flags(ram_offset,temp); + if (ram_offset) + offset_reg = get_ro_reg(i_regs, 0); - if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR + if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR assert(0); } - emit_xorimm(temp,3,temp); emit_testimm(temp,2); - case2=out; + case23=out; emit_jne(0); emit_testimm(temp,1); case1=out; emit_jne(0); // 0 - if (opcode[i]==0x2A) { // SWL - emit_writeword_indexed(tl,0,temp); + if (dops[i].opcode == 0x2A) { // SWL + // Write msb into least significant byte + if (dops[i].rs2) emit_rorimm(tl, 24, tl); + do_store_byte(temp, tl, offset_reg); + if (dops[i].rs2) emit_rorimm(tl, 8, tl); } - else if (opcode[i]==0x2E) { // SWR - emit_writebyte_indexed(tl,3,temp); + else if (dops[i].opcode == 0x2E) { // SWR + // Write entire word + do_store_word(temp, 0, tl, offset_reg, 1); } - else - assert(0); - done0=out; + done0 = out; emit_jmp(0); // 1 set_jump_target(case1, out); - if (opcode[i]==0x2A) { // SWL - // Write 3 msb into three least significant bytes - if(rs2[i]) emit_rorimm(tl,8,tl); - emit_writehword_indexed(tl,-1,temp); - if(rs2[i]) emit_rorimm(tl,16,tl); - emit_writebyte_indexed(tl,1,temp); - if(rs2[i]) emit_rorimm(tl,8,tl); + if (dops[i].opcode == 0x2A) { // SWL + // Write two msb into two least significant bytes + if (dops[i].rs2) emit_rorimm(tl, 16, tl); + do_store_hword(temp, -1, tl, offset_reg, 0); + if (dops[i].rs2) emit_rorimm(tl, 16, tl); } - else if (opcode[i]==0x2E) { // SWR - // Write two lsb into two most significant bytes - emit_writehword_indexed(tl,1,temp); + else if (dops[i].opcode == 0x2E) { // SWR + // Write 3 lsb into three most significant bytes + do_store_byte(temp, tl, offset_reg); + if (dops[i].rs2) emit_rorimm(tl, 8, tl); + do_store_hword(temp, 1, tl, offset_reg, 0); + if (dops[i].rs2) emit_rorimm(tl, 24, tl); } done1=out; emit_jmp(0); - // 2 - set_jump_target(case2, out); + // 2,3 + set_jump_target(case23, out); emit_testimm(temp,1); - case3=out; + case3 = out; emit_jne(0); - if (opcode[i]==0x2A) { // SWL - // Write two msb into two least significant bytes - if(rs2[i]) emit_rorimm(tl,16,tl); - emit_writehword_indexed(tl,-2,temp); - if(rs2[i]) emit_rorimm(tl,16,tl); + // 2 + if (dops[i].opcode==0x2A) { // SWL + // Write 3 msb into three least significant bytes + if (dops[i].rs2) emit_rorimm(tl, 8, tl); + do_store_hword(temp, -2, tl, offset_reg, 1); + if (dops[i].rs2) emit_rorimm(tl, 16, tl); + do_store_byte(temp, tl, offset_reg); + if (dops[i].rs2) emit_rorimm(tl, 8, tl); } - else if (opcode[i]==0x2E) { // SWR - // Write 3 lsb into three most significant bytes - emit_writebyte_indexed(tl,-1,temp); - if(rs2[i]) emit_rorimm(tl,8,tl); - emit_writehword_indexed(tl,0,temp); - if(rs2[i]) emit_rorimm(tl,24,tl); + else if (dops[i].opcode == 0x2E) { // SWR + // Write two lsb into two most significant bytes + do_store_hword(temp, 0, tl, offset_reg, 1); } - done2=out; + done2 = out; emit_jmp(0); // 3 set_jump_target(case3, out); - if (opcode[i]==0x2A) { // SWL - // Write msb into least significant byte - if(rs2[i]) emit_rorimm(tl,24,tl); - emit_writebyte_indexed(tl,-3,temp); - if(rs2[i]) emit_rorimm(tl,8,tl); + if (dops[i].opcode == 0x2A) { // SWL + do_store_word(temp, -3, tl, offset_reg, 0); } - else if (opcode[i]==0x2E) { // SWR - // Write entire word - emit_writeword_indexed(tl,-3,temp); + else if (dops[i].opcode == 0x2E) { // SWR + do_store_byte(temp, tl, offset_reg); } set_jump_target(done0, out); set_jump_target(done1, out); set_jump_target(done2, out); + if (offset_reg == HOST_TEMPREG) + host_tempreg_release(); if(!c||!memtarget) - add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj[i],reglist); - if(!(i_regs->waswritten&(1<waswritten&(1<regmap,INVCP); assert(ir>=0); @@ -3171,7 +3313,7 @@ static void storelr_assemble(int i, const struct regstat *i_regs) #else emit_cmpmem_indexedsr12_imm(invalid_code,temp,1); #endif - #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) + #ifdef INVALIDATE_USE_COND_CALL emit_callne(invalidate_addr_reg[temp]); #else void *jaddr2 = out; @@ -3181,28 +3323,28 @@ static void storelr_assemble(int i, const struct regstat *i_regs) } } -static void cop0_assemble(int i,struct regstat *i_regs) +static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_) { - if(opcode2[i]==0) // MFC0 + if(dops[i].opcode2==0) // MFC0 { - signed char t=get_reg(i_regs->regmap,rt1[i]); + signed char t=get_reg(i_regs->regmap,dops[i].rt1); u_int copr=(source[i]>>11)&0x1f; //assert(t>=0); // Why does this happen? OOT is weird - if(t>=0&&rt1[i]!=0) { + if(t>=0&&dops[i].rt1!=0) { emit_readword(®_cop0[copr],t); } } - else if(opcode2[i]==4) // MTC0 + else if(dops[i].opcode2==4) // MTC0 { - signed char s=get_reg(i_regs->regmap,rs1[i]); + signed char s=get_reg(i_regs->regmap,dops[i].rs1); char copr=(source[i]>>11)&0x1f; assert(s>=0); - wb_register(rs1[i],i_regs->regmap,i_regs->dirty); + wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty); if(copr==9||copr==11||copr==12||copr==13) { emit_readword(&last_count,HOST_TEMPREG); emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG); - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); + emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG); emit_writeword(HOST_CCREG,&Count); } // What a mess. The status register (12) can enable interrupts, @@ -3217,10 +3359,10 @@ static void cop0_assemble(int i,struct regstat *i_regs) emit_writeword(HOST_CCREG,&last_count); emit_movimm(0,HOST_CCREG); emit_storereg(CCREG,HOST_CCREG); - emit_loadreg(rs1[i],1); + emit_loadreg(dops[i].rs1,1); emit_movimm(copr,0); emit_far_call(pcsx_mtc0_ds); - emit_loadreg(rs1[i],s); + emit_loadreg(dops[i].rs1,s); return; } emit_movimm(start+i*4+4,HOST_TEMPREG); @@ -3229,7 +3371,7 @@ static void cop0_assemble(int i,struct regstat *i_regs) emit_writeword(HOST_TEMPREG,&pending_exception); } if(s==HOST_CCREG) - emit_loadreg(rs1[i],1); + emit_loadreg(dops[i].rs1,1); else if(s!=1) emit_mov(s,1); emit_movimm(copr,0); @@ -3237,7 +3379,7 @@ static void cop0_assemble(int i,struct regstat *i_regs) if(copr==9||copr==11||copr==12||copr==13) { emit_readword(&Count,HOST_CCREG); emit_readword(&next_interupt,HOST_TEMPREG); - emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG); + emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG); emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG); emit_writeword(HOST_TEMPREG,&last_count); emit_storereg(CCREG,HOST_CCREG); @@ -3250,15 +3392,15 @@ static void cop0_assemble(int i,struct regstat *i_regs) emit_jeq(0); emit_readword(&pcaddr, 0); emit_addimm(HOST_CCREG,2,HOST_CCREG); - emit_far_call(get_addr_ht); + emit_far_call(ndrc_get_addr_ht); emit_jmpreg(0); set_jump_target(jaddr, out); } - emit_loadreg(rs1[i],s); + emit_loadreg(dops[i].rs1,s); } else { - assert(opcode2[i]==0x10); + assert(dops[i].opcode2==0x10); //if((source[i]&0x3f)==0x10) // RFE { emit_readword(&Status,0); @@ -3270,7 +3412,7 @@ static void cop0_assemble(int i,struct regstat *i_regs) } } -static void cop1_unusable(int i,struct regstat *i_regs) +static void cop1_unusable(int i, const struct regstat *i_regs) { // XXX: should just just do the exception instead //if(!cop1_usable) @@ -3281,12 +3423,12 @@ static void cop1_unusable(int i,struct regstat *i_regs) } } -static void cop1_assemble(int i,struct regstat *i_regs) +static void cop1_assemble(int i, const struct regstat *i_regs) { cop1_unusable(i, i_regs); } -static void c1ls_assemble(int i,struct regstat *i_regs) +static void c1ls_assemble(int i, const struct regstat *i_regs) { cop1_unusable(i, i_regs); } @@ -3309,21 +3451,21 @@ static void do_cop1stub(int n) wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty); if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); emit_movimm(start+(i-ds)*4,EAX); // Get PC - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle... + emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle... emit_far_jump(ds?fp_exception_ds:fp_exception); } static int cop2_is_stalling_op(int i, int *cycles) { - if (opcode[i] == 0x3a) { // SWC2 + if (dops[i].opcode == 0x3a) { // SWC2 *cycles = 0; return 1; } - if (itype[i] == COP2 && (opcode2[i] == 0 || opcode2[i] == 2)) { // MFC2/CFC2 + if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2 *cycles = 0; return 1; } - if (itype[i] == C2OP) { + if (dops[i].itype == C2OP) { *cycles = gte_cycletab[source[i] & 0x3f]; return 1; } @@ -3345,7 +3487,7 @@ static void emit_log_gte_stall(int i, int stall, u_int reglist) emit_movimm(stall, 0); else emit_mov(HOST_TEMPREG, 0); - emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]), 1); + emit_addimm(HOST_CCREG, ccadj[i], 1); emit_far_call(log_gte_stall); restore_regs(reglist); } @@ -3363,15 +3505,17 @@ static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u //printf("no cc %08x\n", start + i*4); return; } - if (!bt[i]) { + if (!dops[i].bt) { for (j = i - 1; j >= 0; j--) { - //if (is_ds[j]) break; - if (cop2_is_stalling_op(j, &other_gte_op_cycles) || bt[j]) + //if (dops[j].is_ds) break; + if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt) + break; + if (j > 0 && ccadj[j - 1] > ccadj[j]) break; } j = max(j, 0); } - cycles_passed = CLOCK_ADJUST(ccadj[i] - ccadj[j]); + cycles_passed = ccadj[i] - ccadj[j]; if (other_gte_op_cycles >= 0) stall = other_gte_op_cycles - cycles_passed; else if (cycles_passed >= 44) @@ -3382,13 +3526,13 @@ static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u #if 0 // too slow save_regs(reglist); emit_movimm(gte_cycletab[op], 0); - emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]), 1); + emit_addimm(HOST_CCREG, ccadj[i], 1); emit_far_call(call_gteStall); restore_regs(reglist); #else host_tempreg_acquire(); emit_readword(&psxRegs.gteBusyCycle, rtmp); - emit_addimm(rtmp, -CLOCK_ADJUST(ccadj[i]), rtmp); + emit_addimm(rtmp, -ccadj[i], rtmp); emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG); emit_cmpimm(HOST_TEMPREG, 44); emit_cmovb_reg(rtmp, HOST_CCREG); @@ -3408,7 +3552,7 @@ static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u for (j = i + 1; j < slen; j++) { if (cop2_is_stalling_op(j, &other_gte_op_cycles)) break; - if (is_jump(j)) { + if (dops[j].is_jump) { // check ds if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles)) j++; @@ -3418,7 +3562,7 @@ static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u if (other_gte_op_cycles >= 0) // will handle stall when assembling that op return; - cycles_passed = CLOCK_ADJUST(ccadj[min(j, slen -1)] - ccadj[i]); + cycles_passed = ccadj[min(j, slen -1)] - ccadj[i]; if (cycles_passed >= 44) return; assem_debug("; save gteBusyCycle\n"); @@ -3426,11 +3570,11 @@ static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u #if 0 emit_readword(&last_count, HOST_TEMPREG); emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG); - emit_addimm(HOST_TEMPREG, CLOCK_ADJUST(ccadj[i]), HOST_TEMPREG); + emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG); emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG); emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle); #else - emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]) + gte_cycletab[op], HOST_TEMPREG); + emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG); emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle); #endif host_tempreg_release(); @@ -3438,21 +3582,21 @@ static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u static int is_mflohi(int i) { - return (itype[i] == MOV && (rs1[i] == HIREG || rs1[i] == LOREG)); + return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG)); } static int check_multdiv(int i, int *cycles) { - if (itype[i] != MULTDIV) + if (dops[i].itype != MULTDIV) return 0; - if (opcode2[i] == 0x18 || opcode2[i] == 0x19) // MULT(U) + if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U) *cycles = 11; // approx from 7 11 14 else *cycles = 37; return 1; } -static void multdiv_prepare_stall(int i, const struct regstat *i_regs) +static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_) { int j, found = 0, c = 0; if (HACK_ENABLED(NDHACK_NO_STALLS)) @@ -3462,11 +3606,11 @@ static void multdiv_prepare_stall(int i, const struct regstat *i_regs) return; } for (j = i + 1; j < slen; j++) { - if (bt[j]) + if (dops[j].bt) break; if ((found = is_mflohi(j))) break; - if (is_jump(j)) { + if (dops[j].is_jump) { // check ds if (j + 1 < slen && (found = is_mflohi(j + 1))) j++; @@ -3480,7 +3624,7 @@ static void multdiv_prepare_stall(int i, const struct regstat *i_regs) assert(c > 0); assem_debug("; muldiv prepare stall %d\n", c); host_tempreg_acquire(); - emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]) + c, HOST_TEMPREG); + emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG); emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle); host_tempreg_release(); } @@ -3489,7 +3633,7 @@ static void multdiv_do_stall(int i, const struct regstat *i_regs) { int j, known_cycles = 0; u_int reglist = get_host_reglist(i_regs->regmap); - int rtmp = get_reg(i_regs->regmap, -1); + int rtmp = get_reg_temp(i_regs->regmap); if (rtmp < 0) rtmp = reglist_find_free(reglist); if (HACK_ENABLED(NDHACK_NO_STALLS)) @@ -3499,19 +3643,21 @@ static void multdiv_do_stall(int i, const struct regstat *i_regs) //printf("no cc/rtmp %08x\n", start + i*4); return; } - if (!bt[i]) { + if (!dops[i].bt) { for (j = i - 1; j >= 0; j--) { - if (is_ds[j]) break; - if (check_multdiv(j, &known_cycles) || bt[j]) + if (dops[j].is_ds) break; + if (check_multdiv(j, &known_cycles)) break; if (is_mflohi(j)) // already handled by this op return; + if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j])) + break; } j = max(j, 0); } if (known_cycles > 0) { - known_cycles -= CLOCK_ADJUST(ccadj[i] - ccadj[j]); + known_cycles -= ccadj[i] - ccadj[j]; assem_debug("; muldiv stall resolved %d\n", known_cycles); if (known_cycles > 0) emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG); @@ -3520,7 +3666,7 @@ static void multdiv_do_stall(int i, const struct regstat *i_regs) assem_debug("; muldiv stall unresolved\n"); host_tempreg_acquire(); emit_readword(&psxRegs.muldivBusyCycle, rtmp); - emit_addimm(rtmp, -CLOCK_ADJUST(ccadj[i]), rtmp); + emit_addimm(rtmp, -ccadj[i], rtmp); emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG); emit_cmpimm(HOST_TEMPREG, 37); emit_cmovb_reg(rtmp, HOST_CCREG); @@ -3611,7 +3757,7 @@ static void cop2_put_dreg(u_int copr,signed char sl,signed char temp) } } -static void c2ls_assemble(int i, const struct regstat *i_regs) +static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_) { int s,tl; int ar; @@ -3620,22 +3766,23 @@ static void c2ls_assemble(int i, const struct regstat *i_regs) void *jaddr2=NULL; enum stub_type type; int agr=AGEN1+(i&1); - int fastio_reg_override=-1; + int offset_reg = -1; + int fastio_reg_override = -1; u_int reglist=get_host_reglist(i_regs->regmap); u_int copr=(source[i]>>16)&0x1f; - s=get_reg(i_regs->regmap,rs1[i]); + s=get_reg(i_regs->regmap,dops[i].rs1); tl=get_reg(i_regs->regmap,FTEMP); offset=imm[i]; - assert(rs1[i]>0); + assert(dops[i].rs1>0); assert(tl>=0); if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<regmap,agr); - if(ar<0) ar=get_reg(i_regs->regmap,-1); + if(ar<0) ar=get_reg_temp(i_regs->regmap); reglist|=1<=0) a=fastio_reg_override; - emit_readword_indexed(0,a,tl); + jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar, + &offset_reg, &fastio_reg_override); + } + else if (ram_offset && memtarget) { + offset_reg = get_ro_reg(i_regs, 0); + } + switch (dops[i].opcode) { + case 0x32: { // LWC2 + int a = ar; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_load_word(a, tl, offset_reg); + break; } - if (opcode[i]==0x3a) { // SWC2 + case 0x3a: { // SWC2 #ifdef DESTRUCTIVE_SHIFT if(!offset&&!c&&s>=0) emit_mov(s,ar); #endif - int a=ar; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_writeword_indexed(tl,0,a); + int a = ar; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_store_word(a, 0, tl, offset_reg, 1); + break; + } + default: + assert(0); } } - if(fastio_reg_override==HOST_TEMPREG) + if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) host_tempreg_release(); if(jaddr2) - add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj[i],reglist); - if(opcode[i]==0x3a) // SWC2 - if(!(i_regs->waswritten&(1<waswritten&(1<regmap,INVCP); assert(ir>=0); @@ -3694,7 +3848,7 @@ static void c2ls_assemble(int i, const struct regstat *i_regs) #else emit_cmpmem_indexedsr12_imm(invalid_code,ar,1); #endif - #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) + #ifdef INVALIDATE_USE_COND_CALL emit_callne(invalidate_addr_reg[ar]); #else void *jaddr3 = out; @@ -3702,7 +3856,7 @@ static void c2ls_assemble(int i, const struct regstat *i_regs) add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<>11) & 0x1f; - signed char temp = get_reg(i_regs->regmap, -1); + signed char temp = get_reg_temp(i_regs->regmap); if (!HACK_ENABLED(NDHACK_NO_STALLS)) { u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1); - if (opcode2[i] == 0 || opcode2[i] == 2) { // MFC2/CFC2 - signed char tl = get_reg(i_regs->regmap, rt1[i]); + if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2 + signed char tl = get_reg(i_regs->regmap, dops[i].rt1); reglist = reglist_exclude(reglist, tl, -1); } cop2_do_stall_check(0, i, i_regs, reglist); } - if (opcode2[i]==0) { // MFC2 - signed char tl=get_reg(i_regs->regmap,rt1[i]); - if(tl>=0&&rt1[i]!=0) + if (dops[i].opcode2==0) { // MFC2 + signed char tl=get_reg(i_regs->regmap,dops[i].rt1); + if(tl>=0&&dops[i].rt1!=0) cop2_get_dreg(copr,tl,temp); } - else if (opcode2[i]==4) { // MTC2 - signed char sl=get_reg(i_regs->regmap,rs1[i]); + else if (dops[i].opcode2==4) { // MTC2 + signed char sl=get_reg(i_regs->regmap,dops[i].rs1); cop2_put_dreg(copr,sl,temp); } - else if (opcode2[i]==2) // CFC2 + else if (dops[i].opcode2==2) // CFC2 { - signed char tl=get_reg(i_regs->regmap,rt1[i]); - if(tl>=0&&rt1[i]!=0) + signed char tl=get_reg(i_regs->regmap,dops[i].rt1); + if(tl>=0&&dops[i].rt1!=0) emit_readword(®_cop2c[copr],tl); } - else if (opcode2[i]==6) // CTC2 + else if (dops[i].opcode2==6) // CTC2 { - signed char sl=get_reg(i_regs->regmap,rs1[i]); + signed char sl=get_reg(i_regs->regmap,dops[i].rs1); switch(copr) { case 4: case 12: @@ -3775,75 +3929,26 @@ static void do_unalignedwritestub(int n) signed char *i_regmap=i_regs->regmap; int temp2=get_reg(i_regmap,FTEMP); int rt; - rt=get_reg(i_regmap,rs2[i]); + rt=get_reg(i_regmap,dops[i].rs2); assert(rt>=0); assert(addr>=0); - assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented + assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented reglist|=(1<regmap,rt1[i]); + tl=get_reg(i_regs->regmap,dops[i].rt1); //assert(tl>=0); if(tl>=0) { - sl=get_reg(i_regs->regmap,rs1[i]); + sl=get_reg(i_regs->regmap,dops[i].rs1); if(sl>=0) emit_mov(sl,tl); - else emit_loadreg(rs1[i],tl); + else emit_loadreg(dops[i].rs1,tl); } } - if (rs1[i] == HIREG || rs1[i] == LOREG) // MFHI/MFLO + if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO multdiv_do_stall(i, i_regs); } // call interpreter, exception handler, things that change pc/regs/cycles ... -static void call_c_cpu_handler(int i, const struct regstat *i_regs, u_int pc, void *func) +static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func) { signed char ccreg=get_reg(i_regs->regmap,CCREG); assert(ccreg==HOST_CCREG); @@ -3883,33 +3988,39 @@ static void call_c_cpu_handler(int i, const struct regstat *i_regs, u_int pc, vo emit_movimm(pc,3); // Get PC emit_readword(&last_count,2); emit_writeword(3,&psxRegs.pc); - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX + emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG); emit_add(2,HOST_CCREG,2); emit_writeword(2,&psxRegs.cycle); emit_far_call(func); emit_far_jump(jump_to_new_pc); } -static void syscall_assemble(int i,struct regstat *i_regs) +static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_) { - emit_movimm(0x20,0); // cause code - emit_movimm(0,1); // not in delay slot - call_c_cpu_handler(i,i_regs,start+i*4,psxException); + // 'break' tends to be littered around to catch things like + // division by 0 and is almost never executed, so don't emit much code here + void *func = (dops[i].opcode2 == 0x0C) + ? (is_delayslot ? jump_syscall_ds : jump_syscall) + : (is_delayslot ? jump_break_ds : jump_break); + assert(get_reg(i_regs->regmap, CCREG) == HOST_CCREG); + emit_movimm(start + i*4, 2); // pc + emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG); + emit_far_jump(func); } -static void hlecall_assemble(int i,struct regstat *i_regs) +static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_) { void *hlefunc = psxNULL; uint32_t hleCode = source[i] & 0x03ffffff; if (hleCode < ARRAY_SIZE(psxHLEt)) hlefunc = psxHLEt[hleCode]; - call_c_cpu_handler(i,i_regs,start+i*4+4,hlefunc); + call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc); } -static void intcall_assemble(int i,struct regstat *i_regs) +static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_) { - call_c_cpu_handler(i,i_regs,start+i*4,execI); + call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI); } static void speculate_mov(int rs,int rt) @@ -3939,61 +4050,61 @@ static void speculate_register_values(int i) } smrv_strong=smrv_strong_next; smrv_weak=smrv_weak_next; - switch(itype[i]) { + switch(dops[i].itype) { case ALU: - if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]); - else if((smrv_strong>>rs2[i])&1) speculate_mov(rs2[i],rt1[i]); - else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]); - else if((smrv_weak>>rs2[i])&1) speculate_mov_weak(rs2[i],rt1[i]); + if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1); + else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1); + else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1); + else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1); else { - smrv_strong_next&=~(1<=0) { if(get_final_value(hr,i,&value)) - smrv[rt1[i]]=value; - else smrv[rt1[i]]=constmap[i][hr]; - smrv_strong_next|=1<>rs1[i])&1) speculate_mov(rs1[i],rt1[i]); - else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]); + if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1); + else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1); } break; case LOAD: - if(start<0x2000&&(rt1[i]==26||(smrv[rt1[i]]>>24)==0xa0)) { + if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) { // special case for BIOS - smrv[rt1[i]]=0xa0000000; - smrv_strong_next|=1<=0&&(pre[hr]&63)=0&&pre[hr]=0) { emit_mov(hr,nr); @@ -4103,26 +4276,18 @@ static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,u // Load the specified registers // This only loads the registers given as arguments because // we don't want to load things that will be overwritten -static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2) +static inline void load_reg(signed char entry[], signed char regmap[], int rs) { - int hr; - // Load 32-bit regs - for(hr=0;hr=0) { - if(entry[hr]!=regmap[hr]) { - if(regmap[hr]==rs1||regmap[hr]==rs2) - { - if(regmap[hr]==0) { - emit_zeroreg(hr); - } - else - { - emit_loadreg(regmap[hr],hr); - } - } - } - } - } + int hr = get_reg(regmap, rs); + if (hr >= 0 && entry[hr] != regmap[hr]) + emit_loadreg(regmap[hr], hr); +} + +static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2) +{ + load_reg(entry, regmap, rs1); + if (rs1 != rs2) + load_reg(entry, regmap, rs2); } // Load registers prior to the start of a loop @@ -4130,68 +4295,53 @@ static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2) static void loop_preload(signed char pre[],signed char entry[]) { int hr; - for(hr=0;hr=0) { - if(get_reg(pre,entry[hr])<0) { - assem_debug("loop preload:\n"); - //printf("loop preload: %d\n",hr); - if(entry[hr]==0) { - emit_zeroreg(hr); - } - else if(entry[hr]= 0 && pre[hr] != r && get_reg(pre, r) < 0) { + assem_debug("loop preload:\n"); + if (r < TEMPREG) + emit_loadreg(r, hr); } } } // Generate address for load/store instruction // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads -void address_generation(int i,struct regstat *i_regs,signed char entry[]) +static void address_generation(int i, const struct regstat *i_regs, signed char entry[]) { - if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) { + if (dops[i].is_load || dops[i].is_store) { int ra=-1; int agr=AGEN1+(i&1); - if(itype[i]==LOAD) { - ra=get_reg(i_regs->regmap,rt1[i]); - if(ra<0) ra=get_reg(i_regs->regmap,-1); + if(dops[i].itype==LOAD) { + ra=get_reg(i_regs->regmap,dops[i].rt1); + if(ra<0) ra=get_reg_temp(i_regs->regmap); assert(ra>=0); } - if(itype[i]==LOADLR) { + if(dops[i].itype==LOADLR) { ra=get_reg(i_regs->regmap,FTEMP); } - if(itype[i]==STORE||itype[i]==STORELR) { + if(dops[i].itype==STORE||dops[i].itype==STORELR) { ra=get_reg(i_regs->regmap,agr); - if(ra<0) ra=get_reg(i_regs->regmap,-1); + if(ra<0) ra=get_reg_temp(i_regs->regmap); } - if(itype[i]==C1LS||itype[i]==C2LS) { - if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2 + if(dops[i].itype==C2LS) { + if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2 ra=get_reg(i_regs->regmap,FTEMP); else { // SWC1/SDC1/SWC2/SDC2 ra=get_reg(i_regs->regmap,agr); - if(ra<0) ra=get_reg(i_regs->regmap,-1); + if(ra<0) ra=get_reg_temp(i_regs->regmap); } } - int rs=get_reg(i_regs->regmap,rs1[i]); + int rs=get_reg(i_regs->regmap,dops[i].rs1); if(ra>=0) { int offset=imm[i]; int c=(i_regs->wasconst>>rs)&1; - if(rs1[i]==0) { + if(dops[i].rs1==0) { // Using r0 as a base address if(!entry||entry[ra]!=agr) { - if (opcode[i]==0x22||opcode[i]==0x26) { + if (dops[i].opcode==0x22||dops[i].opcode==0x26) { emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR - }else if (opcode[i]==0x1a||opcode[i]==0x1b) { + }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) { emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR }else{ emit_movimm(offset,ra); @@ -4199,17 +4349,17 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[]) } // else did it in the previous cycle } else if(rs<0) { - if(!entry||entry[ra]!=rs1[i]) - emit_loadreg(rs1[i],ra); - //if(!entry||entry[ra]!=rs1[i]) + if(!entry||entry[ra]!=dops[i].rs1) + emit_loadreg(dops[i].rs1,ra); + //if(!entry||entry[ra]!=dops[i].rs1) // printf("poor load scheduling!\n"); } else if(c) { - if(rs1[i]!=rt1[i]||itype[i]!=LOAD) { + if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) { if(!entry||entry[ra]!=agr) { - if (opcode[i]==0x22||opcode[i]==0x26) { + if (dops[i].opcode==0x22||dops[i].opcode==0x26) { emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR - }else if (opcode[i]==0x1a||opcode[i]==0x1b) { + }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) { emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR }else{ emit_movimm(constmap[i][rs]+offset,ra); @@ -4218,7 +4368,7 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[]) } // else did it in the previous cycle } // else load_consts already did it } - if(offset&&!c&&rs1[i]) { + if(offset&&!c&&dops[i].rs1) { if(rs>=0) { emit_addimm(rs,offset,ra); }else{ @@ -4228,30 +4378,30 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[]) } } // Preload constants for next instruction - if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) { + if (dops[i+1].is_load || dops[i+1].is_store) { int agr,ra; // Actual address agr=AGEN1+((i+1)&1); ra=get_reg(i_regs->regmap,agr); if(ra>=0) { - int rs=get_reg(regs[i+1].regmap,rs1[i+1]); + int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1); int offset=imm[i+1]; int c=(regs[i+1].wasconst>>rs)&1; - if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) { - if (opcode[i+1]==0x22||opcode[i+1]==0x26) { + if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) { + if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) { emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR - }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) { + }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) { emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR }else{ emit_movimm(constmap[i+1][rs]+offset,ra); regs[i+1].loadedconst|=1<>hr)&1)) break; - if(bt[i+1]) break; + if(dops[i+1].bt) break; i++; } if(i>hr)&1)) + if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1)) { // Precompute load address *value=constmap[i][hr]+imm[i+2]; return 1; } } - if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg) + if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg) { // Precompute load address *value=constmap[i][hr]+imm[i+1]; @@ -4306,7 +4456,7 @@ static void load_consts(signed char pre[],signed char regmap[],int i) { int hr,hr2; // propagate loaded constant flags - if(i==0||bt[i]) + if(i==0||dops[i].bt) regs[i].loadedconst=0; else { for(hr=0;hr>2; @@ -4417,7 +4567,7 @@ void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr) } // Load all registers (except cycle count) -void load_all_regs(signed char i_regmap[]) +static void load_all_regs(const signed char i_regmap[]) { int hr; for(hr=0;hr0 && (i_regmap[hr]&63)0 && i_regmap[hr]0 && (i_regmap[hr]&63)0 && i_regmap[hr]0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP)) return 0; + //if(t>0&&(dops[t-1].is_jump) return 0; // Delay slots require additional processing, so do not match - if(is_ds[t]) return 0; + if(dops[t].is_ds) return 0; } else { @@ -4614,7 +4764,7 @@ static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr) } #ifdef DRC_DBG -static void drc_dbg_emit_do_cmp(int i) +static void drc_dbg_emit_do_cmp(int i, int ccadj_) { extern void do_insn_cmp(); //extern int cycle; @@ -4623,9 +4773,9 @@ static void drc_dbg_emit_do_cmp(int i) assem_debug("//do_insn_cmp %08x\n", start+i*4); save_regs(reglist); // write out changed consts to match the interpreter - if (i > 0 && !bt[i]) { + if (i > 0 && !dops[i].bt) { for (hr = 0; hr < HOST_REGS; hr++) { - int reg = regs[i-1].regmap[hr]; + int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr]; if (hr == EXCLUDE_REG || reg < 0) continue; if (!((regs[i-1].isconst >> hr) & 1)) @@ -4638,6 +4788,11 @@ static void drc_dbg_emit_do_cmp(int i) } emit_movimm(start+i*4,0); emit_writeword(0,&pcaddr); + int cc = get_reg(regs[i].regmap_entry, CCREG); + if (cc < 0) + emit_loadreg(CCREG, cc = 0); + emit_addimm(cc, ccadj_, 0); + emit_writeword(0, &psxRegs.cycle); emit_far_call(do_insn_cmp); //emit_readword(&cycle,0); //emit_addimm(0,2,0); @@ -4647,69 +4802,40 @@ static void drc_dbg_emit_do_cmp(int i) assem_debug("\\\\do_insn_cmp\n"); } #else -#define drc_dbg_emit_do_cmp(x) +#define drc_dbg_emit_do_cmp(x,y) #endif // Used when a branch jumps into the delay slot of another branch static void ds_assemble_entry(int i) { - int t=(ba[i]-start)>>2; + int t = (ba[i] - start) >> 2; + int ccadj_ = -CLOCK_ADJUST(1); if (!instr_addr[t]) instr_addr[t] = out; assem_debug("Assemble delay slot at %x\n",ba[i]); assem_debug("<->\n"); - drc_dbg_emit_do_cmp(t); + drc_dbg_emit_do_cmp(t, ccadj_); if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG) wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty); - load_regs(regs[t].regmap_entry,regs[t].regmap,rs1[t],rs2[t]); + load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2); address_generation(t,®s[t],regs[t].regmap_entry); - if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a) - load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP); + if (ram_offset && (dops[t].is_load || dops[t].is_store)) + load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG); + if (dops[t].is_store) + load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP); is_delayslot=0; - switch(itype[t]) { - case ALU: - alu_assemble(t,®s[t]);break; - case IMM16: - imm16_assemble(t,®s[t]);break; - case SHIFT: - shift_assemble(t,®s[t]);break; - case SHIFTIMM: - shiftimm_assemble(t,®s[t]);break; - case LOAD: - load_assemble(t,®s[t]);break; - case LOADLR: - loadlr_assemble(t,®s[t]);break; - case STORE: - store_assemble(t,®s[t]);break; - case STORELR: - storelr_assemble(t,®s[t]);break; - case COP0: - cop0_assemble(t,®s[t]);break; - case COP1: - cop1_assemble(t,®s[t]);break; - case C1LS: - c1ls_assemble(t,®s[t]);break; - case COP2: - cop2_assemble(t,®s[t]);break; - case C2LS: - c2ls_assemble(t,®s[t]);break; - case C2OP: - c2op_assemble(t,®s[t]);break; - case MULTDIV: - multdiv_assemble(t,®s[t]); - multdiv_prepare_stall(i,®s[t]); - break; - case MOV: - mov_assemble(t,®s[t]);break; + switch (dops[t].itype) { case SYSCALL: case HLECALL: case INTCALL: - case SPAN: case UJUMP: case RJUMP: case CJUMP: case SJUMP: SysPrintf("Jump in the delay slot. This is probably a bug.\n"); + break; + default: + assemble(t, ®s[t], ccadj_); } store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4); load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4); @@ -4722,16 +4848,6 @@ static void ds_assemble_entry(int i) emit_jmp(0); } -static void emit_extjump(void *addr, u_int target) -{ - emit_extjump2(addr, target, dyna_linker); -} - -static void emit_extjump_ds(void *addr, u_int target) -{ - emit_extjump2(addr, target, dyna_linker_ds); -} - // Load 2 immediates optimizing for small code size static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2) { @@ -4739,13 +4855,14 @@ static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2) emit_movimm_from(imm1,rt1,imm2,rt2); } -void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert) +static void do_cc(int i, const signed char i_regmap[], int *adj, + int addr, int taken, int invert) { - int count; + int count, count_plus2; void *jaddr; void *idle=NULL; int t=0; - if(itype[i]==RJUMP) + if(dops[i].itype==RJUMP) { *adj=0; } @@ -4753,14 +4870,15 @@ void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert) if(internal_branch(ba[i])) { t=(ba[i]-start)>>2; - if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle + if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle else *adj=ccadj[t]; } else { *adj=0; } - count=ccadj[i]; + count = ccadj[i]; + count_plus2 = count + CLOCK_ADJUST(2); if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) { // Idle loop if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG); @@ -4771,26 +4889,26 @@ void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert) emit_jmp(0); } else if(*adj==0||invert) { - int cycles=CLOCK_ADJUST(count+2); + int cycles = count_plus2; // faster loop HACK #if 0 if (t&&*adj) { int rel=t-i; if(-NO_CYCLE_PENALTY_THR=0); #ifdef DESTRUCTIVE_WRITEBACK - if(rs1[i]) { + if(dops[i].rs1) { if((branch_regs[i].dirty>>s1l)&&1) - emit_loadreg(rs1[i],s1l); + emit_loadreg(dops[i].rs1,s1l); } else { if((branch_regs[i].dirty>>s1l)&1) - emit_loadreg(rs2[i],s1l); + emit_loadreg(dops[i].rs2,s1l); } if(s2l>=0) if((branch_regs[i].dirty>>s2l)&1) - emit_loadreg(rs2[i],s2l); + emit_loadreg(dops[i].rs2,s2l); #endif int hr=0; int addr=-1,alt=-1,ntaddr=-1; while(hr=0) emit_cmp(s1l,s2l); @@ -4895,7 +5013,7 @@ static void do_ccstub(int n) emit_cmovne_reg(alt,addr); #endif } - if((opcode[i]&0x2f)==5) // BNE + if((dops[i].opcode&0x2f)==5) // BNE { #ifdef HAVE_CMOV_IMM if(s2l>=0) emit_cmp(s1l,s2l); @@ -4908,7 +5026,7 @@ static void do_ccstub(int n) emit_cmovne_reg(alt,addr); #endif } - if((opcode[i]&0x2f)==6) // BLEZ + if((dops[i].opcode&0x2f)==6) // BLEZ { //emit_movimm(ba[i],alt); //emit_movimm(start+i*4+8,addr); @@ -4916,7 +5034,7 @@ static void do_ccstub(int n) emit_cmpimm(s1l,1); emit_cmovl_reg(alt,addr); } - if((opcode[i]&0x2f)==7) // BGTZ + if((dops[i].opcode&0x2f)==7) // BGTZ { //emit_movimm(ba[i],addr); //emit_movimm(start+i*4+8,ntaddr); @@ -4924,7 +5042,7 @@ static void do_ccstub(int n) emit_cmpimm(s1l,1); emit_cmovl_reg(ntaddr,addr); } - if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ + if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ { //emit_movimm(ba[i],alt); //emit_movimm(start+i*4+8,addr); @@ -4932,7 +5050,7 @@ static void do_ccstub(int n) emit_test(s1l,s1l); emit_cmovs_reg(alt,addr); } - if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ + if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ { //emit_movimm(ba[i],addr); //emit_movimm(start+i*4+8,alt); @@ -4940,7 +5058,7 @@ static void do_ccstub(int n) emit_test(s1l,s1l); emit_cmovs_reg(alt,addr); } - if(opcode[i]==0x11 && opcode2[i]==0x08 ) { + if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) { if(source[i]&0x10000) // BC1T { //emit_movimm(ba[i],alt); @@ -4961,10 +5079,10 @@ static void do_ccstub(int n) emit_writeword(addr,&pcaddr); } else - if(itype[i]==RJUMP) + if(dops[i].itype==RJUMP) { - int r=get_reg(branch_regs[i].regmap,rs1[i]); - if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) { + int r=get_reg(branch_regs[i].regmap,dops[i].rs1); + if (ds_writes_rjump_rs(i)) { r=get_reg(branch_regs[i].regmap,RTEMP); } emit_writeword(r,&pcaddr); @@ -4973,17 +5091,17 @@ static void do_ccstub(int n) } // Update cycle count assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1); - if(stubs[n].a) emit_addimm(HOST_CCREG,CLOCK_ADJUST((signed int)stubs[n].a),HOST_CCREG); + if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG); emit_far_call(cc_interrupt); - if(stubs[n].a) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((signed int)stubs[n].a),HOST_CCREG); + if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG); if(stubs[n].d==TAKEN) { if(internal_branch(ba[i])) load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry); - else if(itype[i]==RJUMP) { + else if(dops[i].itype==RJUMP) { if(get_reg(branch_regs[i].regmap,RTEMP)>=0) emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP)); else - emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i])); + emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1)); } }else if(stubs[n].d==NOTTAKEN) { if(i=0) { #ifdef USE_MINI_HT - if(internal_branch(return_address)&&rt1[i+1]!=31) { + if(internal_branch(return_address)&&dops[i+1].rt1!=31) { int temp=-1; // note: must be ds-safe #ifdef HOST_TEMPREG temp=HOST_TEMPREG; @@ -5045,14 +5163,14 @@ static void ujump_assemble_write_ra(int i) } } -static void ujump_assemble(int i,struct regstat *i_regs) +static void ujump_assemble(int i, const struct regstat *i_regs) { int ra_done=0; if(i==(ba[i]-start)>>2) assem_debug("idle loop\n"); address_generation(i+1,i_regs,regs[i].regmap_entry); #ifdef REG_PREFETCH int temp=get_reg(branch_regs[i].regmap,PTEMP); - if(rt1[i]==31&&temp>=0) + if(dops[i].rt1==31&&temp>=0) { signed char *i_regmap=i_regs->regmap; int return_address=start+i*4+8; @@ -5060,32 +5178,32 @@ static void ujump_assemble(int i,struct regstat *i_regs) if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); } #endif - if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) { + if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) { ujump_assemble_write_ra(i); // writeback ra for DS ra_done=1; } ds_assemble(i+1,i_regs); uint64_t bc_unneeded=branch_regs[i].u; - bc_unneeded|=1|(1LL<=0) emit_prefetchreg(temp); + if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp); #endif do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); - if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal_branch(ba[i])) assem_debug("branch: internal\n"); else assem_debug("branch: external\n"); - if(internal_branch(ba[i])&&is_ds[(ba[i]-start)>>2]) { + if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) { ds_assemble_entry(i); } else { @@ -5097,9 +5215,9 @@ static void ujump_assemble(int i,struct regstat *i_regs) static void rjump_assemble_write_ra(int i) { int rt,return_address; - assert(rt1[i+1]!=rt1[i]); - assert(rt2[i+1]!=rt1[i]); - rt=get_reg(branch_regs[i].regmap,rt1[i]); + assert(dops[i+1].rt1!=dops[i].rt1); + assert(dops[i+1].rt2!=dops[i].rt1); + rt=get_reg(branch_regs[i].regmap,dops[i].rt1); assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); assert(rt>=0); return_address=start+i*4+8; @@ -5115,14 +5233,14 @@ static void rjump_assemble_write_ra(int i) #endif } -static void rjump_assemble(int i,struct regstat *i_regs) +static void rjump_assemble(int i, const struct regstat *i_regs) { int temp; int rs,cc; int ra_done=0; - rs=get_reg(branch_regs[i].regmap,rs1[i]); + rs=get_reg(branch_regs[i].regmap,dops[i].rs1); assert(rs>=0); - if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) { + if (ds_writes_rjump_rs(i)) { // Delay slot abuse, make a copy of the branch address register temp=get_reg(branch_regs[i].regmap,RTEMP); assert(temp>=0); @@ -5132,7 +5250,7 @@ static void rjump_assemble(int i,struct regstat *i_regs) } address_generation(i+1,i_regs,regs[i].regmap_entry); #ifdef REG_PREFETCH - if(rt1[i]==31) + if(dops[i].rt1==31) { if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) { signed char *i_regmap=i_regs->regmap; @@ -5142,22 +5260,22 @@ static void rjump_assemble(int i,struct regstat *i_regs) } #endif #ifdef USE_MINI_HT - if(rs1[i]==31) { + if(dops[i].rs1==31) { int rh=get_reg(regs[i].regmap,RHASH); if(rh>=0) do_preload_rhash(rh); } #endif - if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) { + if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) { rjump_assemble_write_ra(i); ra_done=1; } ds_assemble(i+1,i_regs); uint64_t bc_unneeded=branch_regs[i].u; - bc_unneeded|=1|(1LL<>rs)&1) { - if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) { - emit_loadreg(rs1[i],rs); + if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) { + emit_loadreg(dops[i].rs1,rs); } } #endif #ifdef REG_PREFETCH - if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp); + if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp); #endif #ifdef USE_MINI_HT - if(rs1[i]==31) { + if(dops[i].rs1==31) { do_miniht_load(ht,rh); } #endif //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN); //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen //assert(adj==0); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG); add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs); - if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10) + if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10) // special case for RFE emit_jmp(0); else emit_jns(0); //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1); #ifdef USE_MINI_HT - if(rs1[i]==31) { + if(dops[i].rs1==31) { do_miniht_jump(rs,rh,ht); } else @@ -5208,13 +5326,13 @@ static void rjump_assemble(int i,struct regstat *i_regs) do_jump_vaddr(rs); } #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK - if(rt1[i]!=31&&iregmap; + const signed char *i_regmap = i_regs->regmap; int cc; int match; match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); @@ -5232,45 +5350,45 @@ static void cjump_assemble(int i,struct regstat *i_regs) invert=1; // because of near cond. branches #endif - if(ooo[i]) { - s1l=get_reg(branch_regs[i].regmap,rs1[i]); - s2l=get_reg(branch_regs[i].regmap,rs2[i]); + if(dops[i].ooo) { + s1l=get_reg(branch_regs[i].regmap,dops[i].rs1); + s2l=get_reg(branch_regs[i].regmap,dops[i].rs2); } else { - s1l=get_reg(i_regmap,rs1[i]); - s2l=get_reg(i_regmap,rs2[i]); + s1l=get_reg(i_regmap,dops[i].rs1); + s2l=get_reg(i_regmap,dops[i].rs2); } - if(rs1[i]==0&&rs2[i]==0) + if(dops[i].rs1==0&&dops[i].rs2==0) { - if(opcode[i]&1) nop=1; + if(dops[i].opcode&1) nop=1; else unconditional=1; - //assert(opcode[i]!=5); - //assert(opcode[i]!=7); - //assert(opcode[i]!=0x15); - //assert(opcode[i]!=0x17); + //assert(dops[i].opcode!=5); + //assert(dops[i].opcode!=7); + //assert(dops[i].opcode!=0x15); + //assert(dops[i].opcode!=0x17); } - else if(rs1[i]==0) + else if(dops[i].rs1==0) { s1l=s2l; s2l=-1; } - else if(rs2[i]==0) + else if(dops[i].rs2==0) { s2l=-1; } - if(ooo[i]) { + if(dops[i].ooo) { // Out of order execution (delay slot first) //printf("OOOE\n"); address_generation(i+1,i_regs,regs[i].regmap_entry); ds_assemble(i+1,i_regs); int adj; uint64_t bc_unneeded=branch_regs[i].u; - bc_unneeded&=~((1LL<>2 || source[i+1]!=0) { - if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) assem_debug("branch: internal\n"); else assem_debug("branch: external\n"); - if(internal&&is_ds[(ba[i]-start)>>2]) { + if (internal && dops[(ba[i]-start)>>2].is_ds) { ds_assemble_entry(i); } else { @@ -5299,7 +5417,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) } } else if(nop) { - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); void *jaddr=out; emit_jns(0); add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); @@ -5307,11 +5425,11 @@ static void cjump_assemble(int i,struct regstat *i_regs) else { void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL; do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); - if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); assert(s1l>=0); - if(opcode[i]==4) // BEQ + if(dops[i].opcode==4) // BEQ { if(s2l>=0) emit_cmp(s1l,s2l); else emit_test(s1l,s1l); @@ -5323,7 +5441,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) emit_jeq(0); } } - if(opcode[i]==5) // BNE + if(dops[i].opcode==5) // BNE { if(s2l>=0) emit_cmp(s1l,s2l); else emit_test(s1l,s1l); @@ -5335,7 +5453,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) emit_jne(0); } } - if(opcode[i]==6) // BLEZ + if(dops[i].opcode==6) // BLEZ { emit_cmpimm(s1l,1); if(invert){ @@ -5346,7 +5464,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) emit_jl(0); } } - if(opcode[i]==7) // BGTZ + if(dops[i].opcode==7) // BGTZ { emit_cmpimm(s1l,1); if(invert){ @@ -5360,9 +5478,9 @@ static void cjump_assemble(int i,struct regstat *i_regs) if(invert) { if(taken) set_jump_target(taken, out); #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK - if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) { + if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) { if(adj) { - emit_addimm(cc,-CLOCK_ADJUST(adj),cc); + emit_addimm(cc,-adj,cc); add_to_linker(out,ba[i],internal); }else{ emit_addnop(13); @@ -5372,14 +5490,14 @@ static void cjump_assemble(int i,struct regstat *i_regs) }else #endif { - if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc); + if(adj) emit_addimm(cc,-adj,cc); store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) assem_debug("branch: internal\n"); else assem_debug("branch: external\n"); - if(internal&&is_ds[(ba[i]-start)>>2]) { + if (internal && dops[(ba[i] - start) >> 2].is_ds) { ds_assemble_entry(i); } else { @@ -5392,41 +5510,38 @@ static void cjump_assemble(int i,struct regstat *i_regs) if(nottaken1) set_jump_target(nottaken1, out); if(adj) { - if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc); + if(!invert) emit_addimm(cc,adj,cc); } } // (!unconditional) } // if(ooo) else { // In-order execution (branch first) - //if(likely[i]) printf("IOL\n"); - //else - //printf("IOE\n"); void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL; if(!unconditional&&!nop) { //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); assert(s1l>=0); - if((opcode[i]&0x2f)==4) // BEQ + if((dops[i].opcode&0x2f)==4) // BEQ { if(s2l>=0) emit_cmp(s1l,s2l); else emit_test(s1l,s1l); nottaken=out; emit_jne(DJT_2); } - if((opcode[i]&0x2f)==5) // BNE + if((dops[i].opcode&0x2f)==5) // BNE { if(s2l>=0) emit_cmp(s1l,s2l); else emit_test(s1l,s1l); nottaken=out; emit_jeq(DJT_2); } - if((opcode[i]&0x2f)==6) // BLEZ + if((dops[i].opcode&0x2f)==6) // BLEZ { emit_cmpimm(s1l,1); nottaken=out; emit_jge(DJT_2); } - if((opcode[i]&0x2f)==7) // BGTZ + if((dops[i].opcode&0x2f)==7) // BGTZ { emit_cmpimm(s1l,1); nottaken=out; @@ -5435,7 +5550,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) } // if(!unconditional) int adj; uint64_t ds_unneeded=branch_regs[i].u; - ds_unneeded&=~((1LL<>2]) { + if (internal && dops[(ba[i] - start) >> 2].is_ds) { ds_assemble_entry(i); } else { @@ -5475,18 +5592,19 @@ static void cjump_assemble(int i,struct regstat *i_regs) if(nottaken1) set_jump_target(nottaken1, out); set_jump_target(nottaken, out); assem_debug("2:\n"); - if(!likely[i]) { - wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); - load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i+1],rs2[i+1]); - address_generation(i+1,&branch_regs[i],0); - load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG); - ds_assemble(i+1,&branch_regs[i]); - } + wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); + // load regs + load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); + address_generation(i+1,&branch_regs[i],0); + if (ram_offset) + load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); + load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); + ds_assemble(i+1,&branch_regs[i]); cc=get_reg(branch_regs[i].regmap,CCREG); - if(cc==-1&&!likely[i]) { + if (cc == -1) { // Cycle count isn't in a register, temporarily load it then write it out emit_loadreg(CCREG,HOST_CCREG); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG); void *jaddr=out; emit_jns(0); add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); @@ -5495,22 +5613,22 @@ static void cjump_assemble(int i,struct regstat *i_regs) else{ cc=get_reg(i_regmap,CCREG); assert(cc==HOST_CCREG); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); void *jaddr=out; emit_jns(0); - add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0); + add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); } } } } -static void sjump_assemble(int i,struct regstat *i_regs) +static void sjump_assemble(int i, const struct regstat *i_regs) { - signed char *i_regmap=i_regs->regmap; + const signed char *i_regmap = i_regs->regmap; int cc; int match; match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); - assem_debug("smatch=%d\n",match); + assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo); int s1l; int unconditional=0,nevertaken=0; int invert=0; @@ -5524,39 +5642,39 @@ static void sjump_assemble(int i,struct regstat *i_regs) invert=1; // because of near cond. branches #endif - //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL) - //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL) + //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL) + //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL) - if(ooo[i]) { - s1l=get_reg(branch_regs[i].regmap,rs1[i]); + if(dops[i].ooo) { + s1l=get_reg(branch_regs[i].regmap,dops[i].rs1); } else { - s1l=get_reg(i_regmap,rs1[i]); + s1l=get_reg(i_regmap,dops[i].rs1); } - if(rs1[i]==0) + if(dops[i].rs1==0) { - if(opcode2[i]&1) unconditional=1; + if(dops[i].opcode2&1) unconditional=1; else nevertaken=1; // These are never taken (r0 is never less than zero) - //assert(opcode2[i]!=0); - //assert(opcode2[i]!=2); - //assert(opcode2[i]!=0x10); - //assert(opcode2[i]!=0x12); + //assert(dops[i].opcode2!=0); + //assert(dops[i].opcode2!=2); + //assert(dops[i].opcode2!=0x10); + //assert(dops[i].opcode2!=0x12); } - if(ooo[i]) { + if(dops[i].ooo) { // Out of order execution (delay slot first) //printf("OOOE\n"); address_generation(i+1,i_regs,regs[i].regmap_entry); ds_assemble(i+1,i_regs); int adj; uint64_t bc_unneeded=branch_regs[i].u; - bc_unneeded&=~((1LL<>2 || source[i+1]!=0) { - if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) assem_debug("branch: internal\n"); else assem_debug("branch: external\n"); - if(internal&&is_ds[(ba[i]-start)>>2]) { + if (internal && dops[(ba[i] - start) >> 2].is_ds) { ds_assemble_entry(i); } else { @@ -5597,7 +5715,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) } } else if(nevertaken) { - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); void *jaddr=out; emit_jns(0); add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); @@ -5605,10 +5723,10 @@ static void sjump_assemble(int i,struct regstat *i_regs) else { void *nottaken = NULL; do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); - if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); { assert(s1l>=0); - if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL + if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL { emit_test(s1l,s1l); if(invert){ @@ -5619,7 +5737,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) emit_js(0); } } - if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL + if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL { emit_test(s1l,s1l); if(invert){ @@ -5634,9 +5752,9 @@ static void sjump_assemble(int i,struct regstat *i_regs) if(invert) { #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK - if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) { + if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) { if(adj) { - emit_addimm(cc,-CLOCK_ADJUST(adj),cc); + emit_addimm(cc,-adj,cc); add_to_linker(out,ba[i],internal); }else{ emit_addnop(13); @@ -5646,14 +5764,14 @@ static void sjump_assemble(int i,struct regstat *i_regs) }else #endif { - if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc); + if(adj) emit_addimm(cc,-adj,cc); store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) assem_debug("branch: internal\n"); else assem_debug("branch: external\n"); - if(internal&&is_ds[(ba[i]-start)>>2]) { + if (internal && dops[(ba[i] - start) >> 2].is_ds) { ds_assemble_entry(i); } else { @@ -5665,7 +5783,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) } if(adj) { - if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc); + if(!invert) emit_addimm(cc,adj,cc); } } // (!unconditional) } // if(ooo) @@ -5674,7 +5792,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) // In-order execution (branch first) //printf("IOE\n"); void *nottaken = NULL; - if(rt1[i]==31) { + if(dops[i].rt1==31) { int rt,return_address; rt=get_reg(branch_regs[i].regmap,31); if(rt>=0) { @@ -5689,13 +5807,13 @@ static void sjump_assemble(int i,struct regstat *i_regs) if(!unconditional) { //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); assert(s1l>=0); - if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL + if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL { emit_test(s1l,s1l); nottaken=out; emit_jns(DJT_1); } - if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL + if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL { emit_test(s1l,s1l); nottaken=out; @@ -5704,15 +5822,17 @@ static void sjump_assemble(int i,struct regstat *i_regs) } // if(!unconditional) int adj; uint64_t ds_unneeded=branch_regs[i].u; - ds_unneeded&=~((1LL<>2]) { + if (internal && dops[(ba[i] - start) >> 2].is_ds) { ds_assemble_entry(i); } else { @@ -5742,18 +5862,18 @@ static void sjump_assemble(int i,struct regstat *i_regs) if(!unconditional) { set_jump_target(nottaken, out); assem_debug("1:\n"); - if(!likely[i]) { - wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); - load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i+1],rs2[i+1]); - address_generation(i+1,&branch_regs[i],0); - load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG); - ds_assemble(i+1,&branch_regs[i]); - } + wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); + load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); + address_generation(i+1,&branch_regs[i],0); + if (ram_offset) + load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); + load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); + ds_assemble(i+1,&branch_regs[i]); cc=get_reg(branch_regs[i].regmap,CCREG); - if(cc==-1&&!likely[i]) { + if (cc == -1) { // Cycle count isn't in a register, temporarily load it then write it out emit_loadreg(CCREG,HOST_CCREG); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG); void *jaddr=out; emit_jns(0); add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); @@ -5762,1028 +5882,127 @@ static void sjump_assemble(int i,struct regstat *i_regs) else{ cc=get_reg(i_regmap,CCREG); assert(cc==HOST_CCREG); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); void *jaddr=out; emit_jns(0); - add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0); + add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); } } } } -static void pagespan_assemble(int i,struct regstat *i_regs) +static void check_regmap(signed char *regmap) { - int s1l=get_reg(i_regs->regmap,rs1[i]); - int s2l=get_reg(i_regs->regmap,rs2[i]); - void *taken = NULL; - void *nottaken = NULL; - int unconditional=0; - if(rs1[i]==0) - { - s1l=s2l; - s2l=-1; - } - else if(rs2[i]==0) - { - s2l=-1; - } - int hr=0; - int addr=-1,alt=-1,ntaddr=-1; - if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;} - else { - while(hrregmap[hr]&63)!=rs1[i] && - (i_regs->regmap[hr]&63)!=rs2[i] ) - { - addr=hr++;break; - } - hr++; - } - } - while(hrregmap[hr]&63)!=rs1[i] && - (i_regs->regmap[hr]&63)!=rs2[i] ) - { - alt=hr++;break; - } - hr++; - } - if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register - { - while(hrregmap[hr]&63)!=rs1[i] && - (i_regs->regmap[hr]&63)!=rs2[i] ) - { - ntaddr=hr;break; - } - hr++; - } - } - assert(hrregmap,31); - emit_movimm(start+i*4+8,rt); - unconditional=1; - } - if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR - { - emit_mov(s1l,addr); - if(opcode2[i]==9) // JALR - { - int rt=get_reg(i_regs->regmap,rt1[i]); - emit_movimm(start+i*4+8,rt); - } - } - if((opcode[i]&0x3f)==4) // BEQ - { - if(rs1[i]==rs2[i]) - { - unconditional=1; - } - else - #ifdef HAVE_CMOV_IMM - if(1) { - if(s2l>=0) emit_cmp(s1l,s2l); - else emit_test(s1l,s1l); - emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr); - } - else - #endif - { - assert(s1l>=0); - emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); - if(s2l>=0) emit_cmp(s1l,s2l); - else emit_test(s1l,s1l); - emit_cmovne_reg(alt,addr); - } - } - if((opcode[i]&0x3f)==5) // BNE - { - #ifdef HAVE_CMOV_IMM - if(s2l>=0) emit_cmp(s1l,s2l); - else emit_test(s1l,s1l); - emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr); - #else - assert(s1l>=0); - emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt); - if(s2l>=0) emit_cmp(s1l,s2l); - else emit_test(s1l,s1l); - emit_cmovne_reg(alt,addr); - #endif - } - if((opcode[i]&0x3f)==0x14) // BEQL - { - if(s2l>=0) emit_cmp(s1l,s2l); - else emit_test(s1l,s1l); - if(nottaken) set_jump_target(nottaken, out); - nottaken=out; - emit_jne(0); - } - if((opcode[i]&0x3f)==0x15) // BNEL - { - if(s2l>=0) emit_cmp(s1l,s2l); - else emit_test(s1l,s1l); - nottaken=out; - emit_jeq(0); - if(taken) set_jump_target(taken, out); - } - if((opcode[i]&0x3f)==6) // BLEZ - { - emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); - emit_cmpimm(s1l,1); - emit_cmovl_reg(alt,addr); - } - if((opcode[i]&0x3f)==7) // BGTZ - { - emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr); - emit_cmpimm(s1l,1); - emit_cmovl_reg(ntaddr,addr); - } - if((opcode[i]&0x3f)==0x16) // BLEZL - { - assert((opcode[i]&0x3f)!=0x16); - } - if((opcode[i]&0x3f)==0x17) // BGTZL - { - assert((opcode[i]&0x3f)!=0x17); - } - assert(opcode[i]!=1); // BLTZ/BGEZ - - //FIXME: Check CSREG - if(opcode[i]==0x11 && opcode2[i]==0x08 ) { - if((source[i]&0x30000)==0) // BC1F - { - emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); - emit_testimm(s1l,0x800000); - emit_cmovne_reg(alt,addr); - } - if((source[i]&0x30000)==0x10000) // BC1T - { - emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); - emit_testimm(s1l,0x800000); - emit_cmovne_reg(alt,addr); - } - if((source[i]&0x30000)==0x20000) // BC1FL - { - emit_testimm(s1l,0x800000); - nottaken=out; - emit_jne(0); - } - if((source[i]&0x30000)==0x30000) // BC1TL - { - emit_testimm(s1l,0x800000); - nottaken=out; - emit_jeq(0); - } - } - - assert(i_regs->regmap[HOST_CCREG]==CCREG); - wb_dirtys(regs[i].regmap,regs[i].dirty); - if(likely[i]||unconditional) - { - emit_movimm(ba[i],HOST_BTREG); - } - else if(addr!=HOST_BTREG) - { - emit_mov(addr,HOST_BTREG); - } - void *branch_addr=out; - emit_jmp(0); - int target_addr=start+i*4+5; - void *stub=out; - void *compiled_target_addr=check_addr(target_addr); - emit_extjump_ds(branch_addr, target_addr); - if(compiled_target_addr) { - set_jump_target(branch_addr, compiled_target_addr); - add_jump_out(target_addr,stub); - } - else set_jump_target(branch_addr, stub); - if(likely[i]) { - // Not-taken path - set_jump_target(nottaken, out); - wb_dirtys(regs[i].regmap,regs[i].dirty); - void *branch_addr=out; - emit_jmp(0); - int target_addr=start+i*4+8; - void *stub=out; - void *compiled_target_addr=check_addr(target_addr); - emit_extjump_ds(branch_addr, target_addr); - if(compiled_target_addr) { - set_jump_target(branch_addr, compiled_target_addr); - add_jump_out(target_addr,stub); - } - else set_jump_target(branch_addr, stub); - } -} - -// Assemble the delay slot for the above -static void pagespan_ds() -{ - assem_debug("initial delay slot:\n"); - u_int vaddr=start+1; - u_int page=get_page(vaddr); - u_int vpage=get_vpage(vaddr); - ll_add(jump_dirty+vpage,vaddr,(void *)out); - do_dirty_stub_ds(slen*4); - ll_add(jump_in+page,vaddr,(void *)out); - assert(regs[0].regmap_entry[HOST_CCREG]==CCREG); - if(regs[0].regmap[HOST_CCREG]!=CCREG) - wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty); - if(regs[0].regmap[HOST_BTREG]!=BTREG) - emit_writeword(HOST_BTREG,&branch_target); - load_regs(regs[0].regmap_entry,regs[0].regmap,rs1[0],rs2[0]); - address_generation(0,®s[0],regs[0].regmap_entry); - if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a) - load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP); - is_delayslot=0; - switch(itype[0]) { - case ALU: - alu_assemble(0,®s[0]);break; - case IMM16: - imm16_assemble(0,®s[0]);break; - case SHIFT: - shift_assemble(0,®s[0]);break; - case SHIFTIMM: - shiftimm_assemble(0,®s[0]);break; - case LOAD: - load_assemble(0,®s[0]);break; - case LOADLR: - loadlr_assemble(0,®s[0]);break; - case STORE: - store_assemble(0,®s[0]);break; - case STORELR: - storelr_assemble(0,®s[0]);break; - case COP0: - cop0_assemble(0,®s[0]);break; - case COP1: - cop1_assemble(0,®s[0]);break; - case C1LS: - c1ls_assemble(0,®s[0]);break; - case COP2: - cop2_assemble(0,®s[0]);break; - case C2LS: - c2ls_assemble(0,®s[0]);break; - case C2OP: - c2op_assemble(0,®s[0]);break; - case MULTDIV: - multdiv_assemble(0,®s[0]); - multdiv_prepare_stall(0,®s[0]); - break; - case MOV: - mov_assemble(0,®s[0]);break; - case SYSCALL: - case HLECALL: - case INTCALL: - case SPAN: - case UJUMP: - case RJUMP: - case CJUMP: - case SJUMP: - SysPrintf("Jump in the delay slot. This is probably a bug.\n"); - } - int btaddr=get_reg(regs[0].regmap,BTREG); - if(btaddr<0) { - btaddr=get_reg(regs[0].regmap,-1); - emit_readword(&branch_target,btaddr); - } - assert(btaddr!=HOST_CCREG); - if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); -#ifdef HOST_IMM8 - host_tempreg_acquire(); - emit_movimm(start+4,HOST_TEMPREG); - emit_cmp(btaddr,HOST_TEMPREG); - host_tempreg_release(); -#else - emit_cmpimm(btaddr,start+4); -#endif - void *branch = out; - emit_jeq(0); - store_regs_bt(regs[0].regmap,regs[0].dirty,-1); - do_jump_vaddr(btaddr); - set_jump_target(branch, out); - store_regs_bt(regs[0].regmap,regs[0].dirty,start+4); - load_regs_bt(regs[0].regmap,regs[0].dirty,start+4); -} - -// Basic liveness analysis for MIPS registers -void unneeded_registers(int istart,int iend,int r) -{ - int i; - uint64_t u,gte_u,b,gte_b; - uint64_t temp_u,temp_gte_u=0; - uint64_t gte_u_unknown=0; - if (HACK_ENABLED(NDHACK_GTE_UNNEEDED)) - gte_u_unknown=~0ll; - if(iend==slen-1) { - u=1; - gte_u=gte_u_unknown; - }else{ - //u=unneeded_reg[iend+1]; - u=1; - gte_u=gte_unneeded[iend+1]; - } - - for (i=iend;i>=istart;i--) - { - //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r); - if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP) - { - // If subroutine call, flag return address as a possible branch target - if(rt1[i]==31 && i=(start+slen*4)) - { - // Branch out of this block, flush all regs - u=1; - gte_u=gte_u_unknown; - branch_unneeded_reg[i]=u; - // Merge in delay slot - u|=(1LL<>2]=1; - if(ba[i]<=start+i*4) { - // Backward branch - if(is_ujump(i)) - { - // Unconditional branch - temp_u=1; - temp_gte_u=0; - } else { - // Conditional branch (not taken case) - temp_u=unneeded_reg[i+2]; - temp_gte_u&=gte_unneeded[i+2]; - } - // Merge in delay slot - temp_u|=(1LL<>2,i-1,r+1); - }else{ - unneeded_reg[(ba[i]-start)>>2]=1; - gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown; - } - } /*else*/ if(1) { - if (is_ujump(i)) - { - // Unconditional branch - u=unneeded_reg[(ba[i]-start)>>2]; - gte_u=gte_unneeded[(ba[i]-start)>>2]; - branch_unneeded_reg[i]=u; - // Merge in delay slot - u|=(1LL<>2]; - gte_b=gte_unneeded[(ba[i]-start)>>2]; - branch_unneeded_reg[i]=b; - // Branch delay slot - b|=(1LL<>r)&1) { - if(r==HIREG) printf(" HI"); - else if(r==LOREG) printf(" LO"); - else printf(" r%d",r); - } - } - printf("\n"); - */ - } -} - -// Write back dirty registers as soon as we will no longer modify them, -// so that we don't end up with lots of writes at the branches. -void clean_registers(int istart,int iend,int wr) -{ - int i; - int r; - u_int will_dirty_i,will_dirty_next,temp_will_dirty; - u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty; - if(iend==slen-1) { - will_dirty_i=will_dirty_next=0; - wont_dirty_i=wont_dirty_next=0; - }else{ - will_dirty_i=will_dirty_next=will_dirty[iend+1]; - wont_dirty_i=wont_dirty_next=wont_dirty[iend+1]; - } - for (i=iend;i>=istart;i--) - { - if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP) - { - if(ba[i]=(start+slen*4)) - { - // Branch out of this block, flush all regs - if (is_ujump(i)) - { - // Unconditional branch - will_dirty_i=0; - wont_dirty_i=0; - // Merge in delay slot (will dirty) - for(r=0;r33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) temp_will_dirty&=~(1<33) temp_will_dirty&=~(1<33) temp_will_dirty&=~(1<33) temp_will_dirty&=~(1<0 && (regmap_pre[i][r]&63)<34) { - temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<>(regmap_pre[i][r]&63))&1)<>2,i-1,0); - }else{ - // Limit recursion. It can take an excessive amount - // of time if there are a lot of nested loops. - will_dirty[(ba[i]-start)>>2]=0; - wont_dirty[(ba[i]-start)>>2]=-1; - } - } - /*else*/ if(1) - { - if (is_ujump(i)) - { - // Unconditional branch - will_dirty_i=0; - wont_dirty_i=0; - //if(ba[i]>start+i*4) { // Disable recursion (for debugging) - for(r=0;r>2].regmap_entry[r]) { - will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<>2]&(1<=0) { - will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<>2]>>(branch_regs[i].regmap[r]&63))&1)<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<start+i*4) { // Disable recursion (for debugging) - for(r=0;r>2].regmap_entry[r]) { - will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<>2]&(1<=0) { - will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<>2]>>(target_reg&63))&1)<>2].regmap_entry[r]) { - will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<>2]&(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<istart) { - if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP) - { - // Don't store a register immediately after writing it, - // may prevent dual-issue. - if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<>r)&1) { - printf(" r%d",r); - } - } - printf("\n");*/ - - //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP)) { - regs[i].dirty|=will_dirty_i; - #ifndef DESTRUCTIVE_WRITEBACK - regs[i].dirty&=wont_dirty_i; - if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP) - { - if (i < iend-1 && !is_ujump(i)) { - for(r=0;r>r)&1));*/} - } - } - } - } - else - { - if(i>r)&1));*/} - } - } - } - } - #endif - //} - } - // Deal with changed mappings - temp_will_dirty=will_dirty_i; - temp_wont_dirty=wont_dirty_i; - for(r=0;r=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) { - // Register moved to a different register - will_dirty_i&=~(1<>nr)&1)<>nr)&1)<0 && (regmap_pre[i][r]&63)<34) { - will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<>(regmap_pre[i][r]&63))&1)<>r)&1));*/ - } - } - } - } +#ifndef NDEBUG + int i,j; + for (i = 0; i < HOST_REGS; i++) { + if (regmap[i] < 0) + continue; + for (j = i + 1; j < HOST_REGS; j++) + assert(regmap[i] != regmap[j]); } +#endif } #ifdef DISASM +#include +static char insn[MAXBLOCK][10]; + +#define set_mnemonic(i_, n_) \ + strcpy(insn[i_], n_) + +void print_regmap(const char *name, const signed char *regmap) +{ + char buf[5]; + int i, l; + fputs(name, stdout); + for (i = 0; i < HOST_REGS; i++) { + l = 0; + if (regmap[i] >= 0) + l = snprintf(buf, sizeof(buf), "$%d", regmap[i]); + for (; l < 3; l++) + buf[l] = ' '; + buf[l] = 0; + printf(" r%d=%s", i, buf); + } + fputs("\n", stdout); +} + /* disassembly */ void disassemble_inst(int i) { - if (bt[i]) printf("*"); else printf(" "); - switch(itype[i]) { + if (dops[i].bt) printf("*"); else printf(" "); + switch(dops[i].itype) { case UJUMP: printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break; case CJUMP: - printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break; + printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break; case SJUMP: - printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break; + printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break; case RJUMP: - if (opcode[i]==0x9&&rt1[i]!=31) - printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]); + if (dops[i].opcode==0x9&&dops[i].rt1!=31) + printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1); else - printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]); + printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1); break; - case SPAN: - printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break; case IMM16: - if(opcode[i]==0xf) //LUI - printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff); + if(dops[i].opcode==0xf) //LUI + printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff); else - printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]); + printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]); break; case LOAD: case LOADLR: - printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]); + printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]); break; case STORE: case STORELR: - printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]); + printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]); break; case ALU: case SHIFT: - printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]); + printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2); break; case MULTDIV: - printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]); + printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2); break; case SHIFTIMM: - printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]); + printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]); break; case MOV: - if((opcode2[i]&0x1d)==0x10) - printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]); - else if((opcode2[i]&0x1d)==0x11) - printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]); + if((dops[i].opcode2&0x1d)==0x10) + printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1); + else if((dops[i].opcode2&0x1d)==0x11) + printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1); else printf (" %x: %s\n",start+i*4,insn[i]); break; case COP0: - if(opcode2[i]==0) - printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0 - else if(opcode2[i]==4) - printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0 + if(dops[i].opcode2==0) + printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0 + else if(dops[i].opcode2==4) + printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0 else printf (" %x: %s\n",start+i*4,insn[i]); break; case COP1: - if(opcode2[i]<3) - printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1 - else if(opcode2[i]>3) - printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1 + if(dops[i].opcode2<3) + printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1 + else if(dops[i].opcode2>3) + printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1 else printf (" %x: %s\n",start+i*4,insn[i]); break; case COP2: - if(opcode2[i]<3) - printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2 - else if(opcode2[i]>3) - printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2 + if(dops[i].opcode2<3) + printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2 + else if(dops[i].opcode2>3) + printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2 else printf (" %x: %s\n",start+i*4,insn[i]); break; case C1LS: - printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]); + printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]); break; case C2LS: - printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]); + printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]); break; case INTCALL: printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]); @@ -6792,8 +6011,19 @@ void disassemble_inst(int i) //printf (" %s %8x\n",insn[i],source[i]); printf (" %x: %s\n",start+i*4,insn[i]); } + return; + printf("D: %"PRIu64" WD: %"PRIu64" U: %"PRIu64"\n", + regs[i].dirty, regs[i].wasdirty, unneeded_reg[i]); + print_regmap("pre: ", regmap_pre[i]); + print_regmap("entry: ", regs[i].regmap_entry); + print_regmap("map: ", regs[i].regmap); + if (dops[i].is_jump) { + print_regmap("bentry:", branch_regs[i].regmap_entry); + print_regmap("bmap: ", branch_regs[i].regmap); + } } #else +#define set_mnemonic(i_, n_) static void disassemble_inst(int i) {} #endif // DISASM @@ -6812,7 +6042,7 @@ static void new_dynarec_test(void) SysPrintf("linkage_arm* miscompilation/breakage detected.\n"); } - SysPrintf("testing if we can run recompiled code...\n"); + SysPrintf("testing if we can run recompiled code @%p...\n", out); ((volatile u_int *)out)[0]++; // make cache dirty for (i = 0; i < ARRAY_SIZE(ret); i++) { @@ -6842,18 +6072,21 @@ void new_dynarec_clear_full(void) memset(invalid_code,1,sizeof(invalid_code)); memset(hash_table,0xff,sizeof(hash_table)); memset(mini_ht,-1,sizeof(mini_ht)); - memset(restore_candidate,0,sizeof(restore_candidate)); memset(shadow,0,sizeof(shadow)); copy=shadow; - expirep=16384; // Expiry pointer, +2 blocks + expirep = EXPIRITY_OFFSET; pending_exception=0; literalcount=0; stop_after_jal=0; inv_code_start=inv_code_end=~0; - // TLB - for(n=0;n<4096;n++) ll_clear(jump_in+n); - for(n=0;n<4096;n++) ll_clear(jump_out+n); - for(n=0;n<4096;n++) ll_clear(jump_dirty+n); + hack_addr=0; + f1_hack=0; + for (n = 0; n < ARRAY_SIZE(blocks); n++) + blocks_clear(&blocks[n]); + for (n = 0; n < ARRAY_SIZE(jump_out); n++) + ll_clear(&jump_out[n]); + stat_clear(stat_blocks); + stat_clear(stat_links); cycle_multiplier_old = cycle_multiplier; new_dynarec_hacks_old = new_dynarec_hacks; @@ -6861,16 +6094,24 @@ void new_dynarec_clear_full(void) void new_dynarec_init(void) { - SysPrintf("Init new dynarec\n"); + SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc)); +#ifdef _3DS + check_rosalina(); +#endif #ifdef BASE_ADDR_DYNAMIC #ifdef VITA - sceBlock = sceKernelAllocMemBlockForVM("code", 1 << TARGET_SIZE_2); - if (sceBlock < 0) - SysPrintf("sceKernelAllocMemBlockForVM failed\n"); + sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc)); + if (sceBlock <= 0) + SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock); int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc); if (ret < 0) - SysPrintf("sceKernelGetMemBlockBase failed\n"); + SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret); + sceKernelOpenVMDomain(); + sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache); + #elif defined(_MSC_VER) + ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE, + PAGE_EXECUTE_READWRITE); #else uintptr_t desired_addr = 0; #ifdef __ELF__ @@ -6888,7 +6129,8 @@ void new_dynarec_init(void) #else #ifndef NO_WRITE_EXEC // not all systems allow execute in data segment by default - if (mprotect(ndrc, sizeof(ndrc->translation_cache) + sizeof(ndrc->tramp.ops), + // size must be 4K aligned for 3DS? + if (mprotect(ndrc, sizeof(*ndrc), PROT_READ | PROT_WRITE | PROT_EXEC) != 0) SysPrintf("mprotect() failed: %s\n", strerror(errno)); #endif @@ -6902,11 +6144,11 @@ void new_dynarec_init(void) #endif arch_init(); new_dynarec_test(); -#ifndef RAM_FIXED ram_offset=(uintptr_t)rdram-0x80000000; -#endif if (ram_offset!=0) SysPrintf("warning: RAM is not directly mapped, performance will suffer\n"); + SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n"); + SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out); } void new_dynarec_cleanup(void) @@ -6914,26 +6156,28 @@ void new_dynarec_cleanup(void) int n; #ifdef BASE_ADDR_DYNAMIC #ifdef VITA - sceKernelFreeMemBlock(sceBlock); - sceBlock = -1; + // sceBlock is managed by retroarch's bootstrap code + //sceKernelFreeMemBlock(sceBlock); + //sceBlock = -1; #else if (munmap(ndrc, sizeof(*ndrc)) < 0) SysPrintf("munmap() failed\n"); #endif #endif - for(n=0;n<4096;n++) ll_clear(jump_in+n); - for(n=0;n<4096;n++) ll_clear(jump_out+n); - for(n=0;n<4096;n++) ll_clear(jump_dirty+n); + for (n = 0; n < ARRAY_SIZE(blocks); n++) + blocks_clear(&blocks[n]); + for (n = 0; n < ARRAY_SIZE(jump_out); n++) + ll_clear(&jump_out[n]); + stat_clear(stat_blocks); + stat_clear(stat_links); #ifdef ROM_COPY if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");} #endif + new_dynarec_print_stats(); } static u_int *get_source_start(u_int addr, u_int *limit) { - if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M)) - cycle_multiplier_override = 0; - if (addr < 0x00200000 || (0xa0000000 <= addr && addr < 0xa0200000)) { @@ -6948,7 +6192,7 @@ static u_int *get_source_start(u_int addr, u_int *limit) // BIOS. The multiplier should be much higher as it's uncached 8bit mem, // but timings in PCSX are too tied to the interpreter's BIAS if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M)) - cycle_multiplier_override = 200; + cycle_multiplier_active = 200; *limit = (addr & 0xfff00000) | 0x80000; return (u_int *)((u_char *)psxR + (addr&0x7ffff)); @@ -6991,19 +6235,21 @@ static int addr_cmp(const void *p1_, const void *p2_) int new_dynarec_save_blocks(void *save, int size) { - struct savestate_block *blocks = save; - int maxcount = size / sizeof(blocks[0]); + struct savestate_block *sblocks = save; + int maxcount = size / sizeof(sblocks[0]); struct savestate_block tmp_blocks[1024]; - struct ll_entry *head; + struct block_info *block; int p, s, d, o, bcnt; u_int addr; o = 0; - for (p = 0; p < ARRAY_SIZE(jump_in); p++) { + for (p = 0; p < ARRAY_SIZE(blocks); p++) { bcnt = 0; - for (head = jump_in[p]; head != NULL; head = head->next) { - tmp_blocks[bcnt].addr = head->vaddr; - tmp_blocks[bcnt].regflags = head->reg_sv_flags; + for (block = blocks[p]; block != NULL; block = block->next) { + if (block->is_dirty) + continue; + tmp_blocks[bcnt].addr = block->start; + tmp_blocks[bcnt].regflags = block->reg_sv_flags; bcnt++; } if (bcnt < 1) @@ -7021,22 +6267,39 @@ int new_dynarec_save_blocks(void *save, int size) if (o + d > maxcount) d = maxcount - o; - memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0])); + memcpy(&sblocks[o], tmp_blocks, d * sizeof(sblocks[0])); o += d; } - return o * sizeof(blocks[0]); + return o * sizeof(sblocks[0]); } void new_dynarec_load_blocks(const void *save, int size) { - const struct savestate_block *blocks = save; - int count = size / sizeof(blocks[0]); + const struct savestate_block *sblocks = save; + int count = size / sizeof(sblocks[0]); + struct block_info *block; u_int regs_save[32]; + u_int page; uint32_t f; int i, b; - get_addr(psxRegs.pc); + // restore clean blocks, if any + for (page = 0, b = i = 0; page < ARRAY_SIZE(blocks); page++) { + for (block = blocks[page]; block != NULL; block = block->next, b++) { + if (!block->is_dirty) + continue; + assert(block->source && block->copy); + if (memcmp(block->source, block->copy, block->len)) + continue; + + // see try_restore_block + block->is_dirty = 0; + mark_invalid_code(block->start, block->len, 0); + i++; + } + } + inv_debug("load_blocks: %d/%d clean blocks\n", i, b); // change GPRs for speculation to at least partially work.. memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save)); @@ -7044,14 +6307,14 @@ void new_dynarec_load_blocks(const void *save, int size) psxRegs.GPR.r[i] = 0x80000000; for (b = 0; b < count; b++) { - for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) { + for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) { if (f & 1) psxRegs.GPR.r[i] = 0x1f800000; } - get_addr(blocks[b].addr); + ndrc_get_addr_ht(sblocks[b].addr); - for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) { + for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) { if (f & 1) psxRegs.GPR.r[i] = 0x80000000; } @@ -7060,414 +6323,400 @@ void new_dynarec_load_blocks(const void *save, int size) memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save)); } -int new_recompile_block(u_int addr) +void new_dynarec_print_stats(void) { - u_int pagelimit = 0; - u_int state_rflags = 0; - int i; - - assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out); - //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr); - //if(debug) - //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29); - - // this is just for speculation - for (i = 1; i < 32; i++) { - if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000) - state_rflags |= 1 << i; - } - - start = (u_int)addr&~3; - //assert(((u_int)addr&1)==0); // start-in-delay-slot flag - new_dynarec_did_compile=1; - if (Config.HLE && start == 0x80001000) // hlecall - { - // XXX: is this enough? Maybe check hleSoftCall? - void *beginning=start_block(); - u_int page=get_page(start); +#ifdef STAT_PRINT + printf("cc %3d,%3d,%3d lu%6d,%3d,%3d c%3d inv%3d,%3d tc_offs %zu b %u,%u\n", + stat_bc_pre, stat_bc_direct, stat_bc_restore, + stat_ht_lookups, stat_jump_in_lookups, stat_restore_tries, + stat_restore_compares, stat_inv_addr_calls, stat_inv_hits, + out - ndrc->translation_cache, stat_blocks, stat_links); + stat_bc_direct = stat_bc_pre = stat_bc_restore = + stat_ht_lookups = stat_jump_in_lookups = stat_restore_tries = + stat_restore_compares = stat_inv_addr_calls = stat_inv_hits = 0; +#endif +} - invalid_code[start>>12]=0; - emit_movimm(start,0); - emit_writeword(0,&pcaddr); - emit_far_jump(new_dyna_leave); - literal_pool(0); - end_block(beginning); - ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning); +static int apply_hacks(void) +{ + int i; + if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS)) return 0; + /* special hack(s) */ + for (i = 0; i < slen - 4; i++) + { + // lui a4, 0xf200; jal ; addu a0, 2; slti v0, 28224 + if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP + && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a + && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2) + { + SysPrintf("PE2 hack @%08x\n", start + (i+3)*4); + dops[i + 3].itype = NOP; + } } - - source = get_source_start(start, &pagelimit); - if (source == NULL) { - SysPrintf("Compile at bogus memory address: %08x\n", addr); - abort(); + i = slen; + if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008 + && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809 + && dops[i-7].itype == STORE) + { + i = i-8; + if (dops[i].itype == IMM16) + i--; + // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6 + if (dops[i].itype == STORELR && dops[i].rs1 == 6 + && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6) + { + SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr); + f1_hack = 1; + return 1; + } } + return 0; +} - /* Pass 1: disassemble */ - /* Pass 2: register dependencies, branch targets */ - /* Pass 3: register allocation */ - /* Pass 4: branch dependencies */ - /* Pass 5: pre-alloc */ - /* Pass 6: optimize clean/dirty state */ - /* Pass 7: flag 32-bit registers */ - /* Pass 8: assembly */ - /* Pass 9: linker */ - /* Pass 10: garbage collection / free memory */ - - int j; - int done=0; +static noinline void pass1_disassemble(u_int pagelimit) +{ + int i, j, done = 0, ni_count = 0; unsigned int type,op,op2; - //printf("addr = %x source = %x %x\n", addr,source,source[0]); - - /* Pass 1 disassembly */ - - for(i=0;!done;i++) { - bt[i]=0;likely[i]=0;ooo[i]=0;op2=0; + for (i = 0; !done; i++) + { + memset(&dops[i], 0, sizeof(dops[i])); + op2=0; minimum_free_regs[i]=0; - opcode[i]=op=source[i]>>26; + dops[i].opcode=op=source[i]>>26; switch(op) { - case 0x00: strcpy(insn[i],"special"); type=NI; + case 0x00: set_mnemonic(i, "special"); type=NI; op2=source[i]&0x3f; switch(op2) { - case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break; - case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break; - case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break; - case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break; - case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break; - case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break; - case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break; - case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break; - case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break; - case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break; - case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break; - case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break; - case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break; - case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break; - case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break; - case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break; - case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break; - case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break; - case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break; - case 0x20: strcpy(insn[i],"ADD"); type=ALU; break; - case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break; - case 0x22: strcpy(insn[i],"SUB"); type=ALU; break; - case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break; - case 0x24: strcpy(insn[i],"AND"); type=ALU; break; - case 0x25: strcpy(insn[i],"OR"); type=ALU; break; - case 0x26: strcpy(insn[i],"XOR"); type=ALU; break; - case 0x27: strcpy(insn[i],"NOR"); type=ALU; break; - case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break; - case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break; - case 0x30: strcpy(insn[i],"TGE"); type=NI; break; - case 0x31: strcpy(insn[i],"TGEU"); type=NI; break; - case 0x32: strcpy(insn[i],"TLT"); type=NI; break; - case 0x33: strcpy(insn[i],"TLTU"); type=NI; break; - case 0x34: strcpy(insn[i],"TEQ"); type=NI; break; - case 0x36: strcpy(insn[i],"TNE"); type=NI; break; + case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break; + case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break; + case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break; + case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break; + case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break; + case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break; + case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break; + case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break; + case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break; + case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break; + case 0x0F: set_mnemonic(i, "SYNC"); type=OTHER; break; + case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break; + case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break; + case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break; + case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break; + case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break; + case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break; + case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break; + case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break; + case 0x20: set_mnemonic(i, "ADD"); type=ALU; break; + case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break; + case 0x22: set_mnemonic(i, "SUB"); type=ALU; break; + case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break; + case 0x24: set_mnemonic(i, "AND"); type=ALU; break; + case 0x25: set_mnemonic(i, "OR"); type=ALU; break; + case 0x26: set_mnemonic(i, "XOR"); type=ALU; break; + case 0x27: set_mnemonic(i, "NOR"); type=ALU; break; + case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break; + case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break; + case 0x30: set_mnemonic(i, "TGE"); type=NI; break; + case 0x31: set_mnemonic(i, "TGEU"); type=NI; break; + case 0x32: set_mnemonic(i, "TLT"); type=NI; break; + case 0x33: set_mnemonic(i, "TLTU"); type=NI; break; + case 0x34: set_mnemonic(i, "TEQ"); type=NI; break; + case 0x36: set_mnemonic(i, "TNE"); type=NI; break; #if 0 - case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break; - case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break; - case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break; - case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break; - case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break; - case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break; - case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break; - case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break; - case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break; - case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break; - case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break; - case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break; - case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break; - case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break; - case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break; - case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break; - case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break; + case 0x14: set_mnemonic(i, "DSLLV"); type=SHIFT; break; + case 0x16: set_mnemonic(i, "DSRLV"); type=SHIFT; break; + case 0x17: set_mnemonic(i, "DSRAV"); type=SHIFT; break; + case 0x1C: set_mnemonic(i, "DMULT"); type=MULTDIV; break; + case 0x1D: set_mnemonic(i, "DMULTU"); type=MULTDIV; break; + case 0x1E: set_mnemonic(i, "DDIV"); type=MULTDIV; break; + case 0x1F: set_mnemonic(i, "DDIVU"); type=MULTDIV; break; + case 0x2C: set_mnemonic(i, "DADD"); type=ALU; break; + case 0x2D: set_mnemonic(i, "DADDU"); type=ALU; break; + case 0x2E: set_mnemonic(i, "DSUB"); type=ALU; break; + case 0x2F: set_mnemonic(i, "DSUBU"); type=ALU; break; + case 0x38: set_mnemonic(i, "DSLL"); type=SHIFTIMM; break; + case 0x3A: set_mnemonic(i, "DSRL"); type=SHIFTIMM; break; + case 0x3B: set_mnemonic(i, "DSRA"); type=SHIFTIMM; break; + case 0x3C: set_mnemonic(i, "DSLL32"); type=SHIFTIMM; break; + case 0x3E: set_mnemonic(i, "DSRL32"); type=SHIFTIMM; break; + case 0x3F: set_mnemonic(i, "DSRA32"); type=SHIFTIMM; break; #endif } break; - case 0x01: strcpy(insn[i],"regimm"); type=NI; + case 0x01: set_mnemonic(i, "regimm"); type=NI; op2=(source[i]>>16)&0x1f; switch(op2) { - case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break; - case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break; - case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break; - case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break; - case 0x08: strcpy(insn[i],"TGEI"); type=NI; break; - case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break; - case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break; - case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break; - case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break; - case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break; - case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break; - case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break; - case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break; - case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break; + case 0x00: set_mnemonic(i, "BLTZ"); type=SJUMP; break; + case 0x01: set_mnemonic(i, "BGEZ"); type=SJUMP; break; + //case 0x02: set_mnemonic(i, "BLTZL"); type=SJUMP; break; + //case 0x03: set_mnemonic(i, "BGEZL"); type=SJUMP; break; + //case 0x08: set_mnemonic(i, "TGEI"); type=NI; break; + //case 0x09: set_mnemonic(i, "TGEIU"); type=NI; break; + //case 0x0A: set_mnemonic(i, "TLTI"); type=NI; break; + //case 0x0B: set_mnemonic(i, "TLTIU"); type=NI; break; + //case 0x0C: set_mnemonic(i, "TEQI"); type=NI; break; + //case 0x0E: set_mnemonic(i, "TNEI"); type=NI; break; + case 0x10: set_mnemonic(i, "BLTZAL"); type=SJUMP; break; + case 0x11: set_mnemonic(i, "BGEZAL"); type=SJUMP; break; + //case 0x12: set_mnemonic(i, "BLTZALL"); type=SJUMP; break; + //case 0x13: set_mnemonic(i, "BGEZALL"); type=SJUMP; break; } break; - case 0x02: strcpy(insn[i],"J"); type=UJUMP; break; - case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break; - case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break; - case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break; - case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break; - case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break; - case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break; - case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break; - case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break; - case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break; - case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break; - case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break; - case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break; - case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break; - case 0x10: strcpy(insn[i],"cop0"); type=NI; + case 0x02: set_mnemonic(i, "J"); type=UJUMP; break; + case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break; + case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break; + case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break; + case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break; + case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break; + case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break; + case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break; + case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break; + case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break; + case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break; + case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break; + case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break; + case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break; + case 0x10: set_mnemonic(i, "cop0"); type=NI; op2=(source[i]>>21)&0x1f; switch(op2) { - case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break; - case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break; - case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break; - case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break; - case 0x10: strcpy(insn[i],"RFE"); type=COP0; break; + case 0x00: set_mnemonic(i, "MFC0"); type=COP0; break; + case 0x02: set_mnemonic(i, "CFC0"); type=COP0; break; + case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break; + case 0x06: set_mnemonic(i, "CTC0"); type=COP0; break; + case 0x10: set_mnemonic(i, "RFE"); type=COP0; break; } break; - case 0x11: strcpy(insn[i],"cop1"); type=COP1; + case 0x11: set_mnemonic(i, "cop1"); type=COP1; op2=(source[i]>>21)&0x1f; break; #if 0 - case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break; - case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break; - case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break; - case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break; - case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break; - case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break; - case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break; - case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break; + case 0x14: set_mnemonic(i, "BEQL"); type=CJUMP; break; + case 0x15: set_mnemonic(i, "BNEL"); type=CJUMP; break; + case 0x16: set_mnemonic(i, "BLEZL"); type=CJUMP; break; + case 0x17: set_mnemonic(i, "BGTZL"); type=CJUMP; break; + case 0x18: set_mnemonic(i, "DADDI"); type=IMM16; break; + case 0x19: set_mnemonic(i, "DADDIU"); type=IMM16; break; + case 0x1A: set_mnemonic(i, "LDL"); type=LOADLR; break; + case 0x1B: set_mnemonic(i, "LDR"); type=LOADLR; break; #endif - case 0x20: strcpy(insn[i],"LB"); type=LOAD; break; - case 0x21: strcpy(insn[i],"LH"); type=LOAD; break; - case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break; - case 0x23: strcpy(insn[i],"LW"); type=LOAD; break; - case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break; - case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break; - case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break; + case 0x20: set_mnemonic(i, "LB"); type=LOAD; break; + case 0x21: set_mnemonic(i, "LH"); type=LOAD; break; + case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; break; + case 0x23: set_mnemonic(i, "LW"); type=LOAD; break; + case 0x24: set_mnemonic(i, "LBU"); type=LOAD; break; + case 0x25: set_mnemonic(i, "LHU"); type=LOAD; break; + case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; break; #if 0 - case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break; + case 0x27: set_mnemonic(i, "LWU"); type=LOAD; break; #endif - case 0x28: strcpy(insn[i],"SB"); type=STORE; break; - case 0x29: strcpy(insn[i],"SH"); type=STORE; break; - case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break; - case 0x2B: strcpy(insn[i],"SW"); type=STORE; break; + case 0x28: set_mnemonic(i, "SB"); type=STORE; break; + case 0x29: set_mnemonic(i, "SH"); type=STORE; break; + case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; break; + case 0x2B: set_mnemonic(i, "SW"); type=STORE; break; #if 0 - case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break; - case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break; + case 0x2C: set_mnemonic(i, "SDL"); type=STORELR; break; + case 0x2D: set_mnemonic(i, "SDR"); type=STORELR; break; #endif - case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break; - case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break; - case 0x30: strcpy(insn[i],"LL"); type=NI; break; - case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break; + case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; break; + case 0x2F: set_mnemonic(i, "CACHE"); type=NOP; break; + case 0x30: set_mnemonic(i, "LL"); type=NI; break; + case 0x31: set_mnemonic(i, "LWC1"); type=C1LS; break; #if 0 - case 0x34: strcpy(insn[i],"LLD"); type=NI; break; - case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break; - case 0x37: strcpy(insn[i],"LD"); type=LOAD; break; + case 0x34: set_mnemonic(i, "LLD"); type=NI; break; + case 0x35: set_mnemonic(i, "LDC1"); type=C1LS; break; + case 0x37: set_mnemonic(i, "LD"); type=LOAD; break; #endif - case 0x38: strcpy(insn[i],"SC"); type=NI; break; - case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break; + case 0x38: set_mnemonic(i, "SC"); type=NI; break; + case 0x39: set_mnemonic(i, "SWC1"); type=C1LS; break; #if 0 - case 0x3C: strcpy(insn[i],"SCD"); type=NI; break; - case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break; - case 0x3F: strcpy(insn[i],"SD"); type=STORE; break; + case 0x3C: set_mnemonic(i, "SCD"); type=NI; break; + case 0x3D: set_mnemonic(i, "SDC1"); type=C1LS; break; + case 0x3F: set_mnemonic(i, "SD"); type=STORE; break; #endif - case 0x12: strcpy(insn[i],"COP2"); type=NI; + case 0x12: set_mnemonic(i, "COP2"); type=NI; op2=(source[i]>>21)&0x1f; //if (op2 & 0x10) if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns if (gte_handlers[source[i]&0x3f]!=NULL) { +#ifdef DISASM if (gte_regnames[source[i]&0x3f]!=NULL) strcpy(insn[i],gte_regnames[source[i]&0x3f]); else snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f); +#endif type=C2OP; } } else switch(op2) { - case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break; - case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break; - case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break; - case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break; + case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break; + case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break; + case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break; + case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break; } break; - case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break; - case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break; - case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break; - default: strcpy(insn[i],"???"); type=NI; - SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr); + case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; break; + case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; break; + case 0x3B: set_mnemonic(i, "HLECALL"); type=HLECALL; break; + default: set_mnemonic(i, "???"); type=NI; + SysPrintf("NI %08x @%08x (%08x)\n", source[i], start + i*4, start); break; } - itype[i]=type; - opcode2[i]=op2; + dops[i].itype=type; + dops[i].opcode2=op2; /* Get registers/immediates */ - lt1[i]=0; - dep1[i]=0; - dep2[i]=0; + dops[i].use_lt1=0; gte_rs[i]=gte_rt[i]=0; switch(type) { case LOAD: - rs1[i]=(source[i]>>21)&0x1f; - rs2[i]=0; - rt1[i]=(source[i]>>16)&0x1f; - rt2[i]=0; + dops[i].rs1=(source[i]>>21)&0x1f; + dops[i].rs2=0; + dops[i].rt1=(source[i]>>16)&0x1f; + dops[i].rt2=0; imm[i]=(short)source[i]; break; case STORE: case STORELR: - rs1[i]=(source[i]>>21)&0x1f; - rs2[i]=(source[i]>>16)&0x1f; - rt1[i]=0; - rt2[i]=0; + dops[i].rs1=(source[i]>>21)&0x1f; + dops[i].rs2=(source[i]>>16)&0x1f; + dops[i].rt1=0; + dops[i].rt2=0; imm[i]=(short)source[i]; break; case LOADLR: // LWL/LWR only load part of the register, // therefore the target register must be treated as a source too - rs1[i]=(source[i]>>21)&0x1f; - rs2[i]=(source[i]>>16)&0x1f; - rt1[i]=(source[i]>>16)&0x1f; - rt2[i]=0; + dops[i].rs1=(source[i]>>21)&0x1f; + dops[i].rs2=(source[i]>>16)&0x1f; + dops[i].rt1=(source[i]>>16)&0x1f; + dops[i].rt2=0; imm[i]=(short)source[i]; - if(op==0x26) dep1[i]=rt1[i]; // LWR break; case IMM16: - if (op==0x0f) rs1[i]=0; // LUI instruction has no source register - else rs1[i]=(source[i]>>21)&0x1f; - rs2[i]=0; - rt1[i]=(source[i]>>16)&0x1f; - rt2[i]=0; + if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register + else dops[i].rs1=(source[i]>>21)&0x1f; + dops[i].rs2=0; + dops[i].rt1=(source[i]>>16)&0x1f; + dops[i].rt2=0; if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI imm[i]=(unsigned short)source[i]; }else{ imm[i]=(short)source[i]; } - if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI break; case UJUMP: - rs1[i]=0; - rs2[i]=0; - rt1[i]=0; - rt2[i]=0; + dops[i].rs1=0; + dops[i].rs2=0; + dops[i].rt1=0; + dops[i].rt2=0; // The JAL instruction writes to r31. if (op&1) { - rt1[i]=31; + dops[i].rt1=31; } - rs2[i]=CCREG; + dops[i].rs2=CCREG; break; case RJUMP: - rs1[i]=(source[i]>>21)&0x1f; - rs2[i]=0; - rt1[i]=0; - rt2[i]=0; + dops[i].rs1=(source[i]>>21)&0x1f; + dops[i].rs2=0; + dops[i].rt1=0; + dops[i].rt2=0; // The JALR instruction writes to rd. if (op2&1) { - rt1[i]=(source[i]>>11)&0x1f; + dops[i].rt1=(source[i]>>11)&0x1f; } - rs2[i]=CCREG; + dops[i].rs2=CCREG; break; case CJUMP: - rs1[i]=(source[i]>>21)&0x1f; - rs2[i]=(source[i]>>16)&0x1f; - rt1[i]=0; - rt2[i]=0; + dops[i].rs1=(source[i]>>21)&0x1f; + dops[i].rs2=(source[i]>>16)&0x1f; + dops[i].rt1=0; + dops[i].rt2=0; if(op&2) { // BGTZ/BLEZ - rs2[i]=0; + dops[i].rs2=0; } - likely[i]=op>>4; break; case SJUMP: - rs1[i]=(source[i]>>21)&0x1f; - rs2[i]=CCREG; - rt1[i]=0; - rt2[i]=0; + dops[i].rs1=(source[i]>>21)&0x1f; + dops[i].rs2=CCREG; + dops[i].rt1=0; + dops[i].rt2=0; if(op2&0x10) { // BxxAL - rt1[i]=31; + dops[i].rt1=31; // NOTE: If the branch is not taken, r31 is still overwritten } - likely[i]=(op2&2)>>1; break; case ALU: - rs1[i]=(source[i]>>21)&0x1f; // source - rs2[i]=(source[i]>>16)&0x1f; // subtract amount - rt1[i]=(source[i]>>11)&0x1f; // destination - rt2[i]=0; - if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR - dep1[i]=rs1[i];dep2[i]=rs2[i]; - } - else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB - dep1[i]=rs1[i];dep2[i]=rs2[i]; - } + dops[i].rs1=(source[i]>>21)&0x1f; // source + dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount + dops[i].rt1=(source[i]>>11)&0x1f; // destination + dops[i].rt2=0; break; case MULTDIV: - rs1[i]=(source[i]>>21)&0x1f; // source - rs2[i]=(source[i]>>16)&0x1f; // divisor - rt1[i]=HIREG; - rt2[i]=LOREG; + dops[i].rs1=(source[i]>>21)&0x1f; // source + dops[i].rs2=(source[i]>>16)&0x1f; // divisor + dops[i].rt1=HIREG; + dops[i].rt2=LOREG; break; case MOV: - rs1[i]=0; - rs2[i]=0; - rt1[i]=0; - rt2[i]=0; - if(op2==0x10) rs1[i]=HIREG; // MFHI - if(op2==0x11) rt1[i]=HIREG; // MTHI - if(op2==0x12) rs1[i]=LOREG; // MFLO - if(op2==0x13) rt1[i]=LOREG; // MTLO - if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx - if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx - dep1[i]=rs1[i]; + dops[i].rs1=0; + dops[i].rs2=0; + dops[i].rt1=0; + dops[i].rt2=0; + if(op2==0x10) dops[i].rs1=HIREG; // MFHI + if(op2==0x11) dops[i].rt1=HIREG; // MTHI + if(op2==0x12) dops[i].rs1=LOREG; // MFLO + if(op2==0x13) dops[i].rt1=LOREG; // MTLO + if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx + if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx break; case SHIFT: - rs1[i]=(source[i]>>16)&0x1f; // target of shift - rs2[i]=(source[i]>>21)&0x1f; // shift amount - rt1[i]=(source[i]>>11)&0x1f; // destination - rt2[i]=0; + dops[i].rs1=(source[i]>>16)&0x1f; // target of shift + dops[i].rs2=(source[i]>>21)&0x1f; // shift amount + dops[i].rt1=(source[i]>>11)&0x1f; // destination + dops[i].rt2=0; break; case SHIFTIMM: - rs1[i]=(source[i]>>16)&0x1f; - rs2[i]=0; - rt1[i]=(source[i]>>11)&0x1f; - rt2[i]=0; + dops[i].rs1=(source[i]>>16)&0x1f; + dops[i].rs2=0; + dops[i].rt1=(source[i]>>11)&0x1f; + dops[i].rt2=0; imm[i]=(source[i]>>6)&0x1f; // DSxx32 instructions if(op2>=0x3c) imm[i]|=0x20; break; case COP0: - rs1[i]=0; - rs2[i]=0; - rt1[i]=0; - rt2[i]=0; - if(op2==0||op2==2) rt1[i]=(source[i]>>16)&0x1F; // MFC0/CFC0 - if(op2==4||op2==6) rs1[i]=(source[i]>>16)&0x1F; // MTC0/CTC0 - if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status - if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET + dops[i].rs1=0; + dops[i].rs2=0; + dops[i].rt1=0; + dops[i].rt2=0; + if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0 + if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0 + if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status + if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET break; case COP1: - rs1[i]=0; - rs2[i]=0; - rt1[i]=0; - rt2[i]=0; - if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1 - if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1 - rs2[i]=CSREG; + dops[i].rs1=0; + dops[i].rs2=0; + dops[i].rt1=0; + dops[i].rt2=0; + if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1 + if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1 + dops[i].rs2=CSREG; break; case COP2: - rs1[i]=0; - rs2[i]=0; - rt1[i]=0; - rt2[i]=0; - if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2 - if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2 - rs2[i]=CSREG; + dops[i].rs1=0; + dops[i].rs2=0; + dops[i].rt1=0; + dops[i].rt2=0; + if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2 + if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2 + dops[i].rs2=CSREG; int gr=(source[i]>>11)&0x1F; switch(op2) { @@ -7478,26 +6727,26 @@ int new_recompile_block(u_int addr) } break; case C1LS: - rs1[i]=(source[i]>>21)&0x1F; - rs2[i]=CSREG; - rt1[i]=0; - rt2[i]=0; + dops[i].rs1=(source[i]>>21)&0x1F; + dops[i].rs2=CSREG; + dops[i].rt1=0; + dops[i].rt2=0; imm[i]=(short)source[i]; break; case C2LS: - rs1[i]=(source[i]>>21)&0x1F; - rs2[i]=0; - rt1[i]=0; - rt2[i]=0; + dops[i].rs1=(source[i]>>21)&0x1F; + dops[i].rs2=0; + dops[i].rt1=0; + dops[i].rt2=0; imm[i]=(short)source[i]; if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2 break; case C2OP: - rs1[i]=0; - rs2[i]=0; - rt1[i]=0; - rt2[i]=0; + dops[i].rs1=0; + dops[i].rs2=0; + dops[i].rt1=0; + dops[i].rt2=0; gte_rs[i]=gte_reg_reads[source[i]&0x3f]; gte_rt[i]=gte_reg_writes[source[i]&0x3f]; gte_rt[i]|=1ll<<63; // every op changes flags @@ -7511,127 +6760,314 @@ int new_recompile_block(u_int addr) case SYSCALL: case HLECALL: case INTCALL: - rs1[i]=CCREG; - rs2[i]=0; - rt1[i]=0; - rt2[i]=0; + dops[i].rs1=CCREG; + dops[i].rs2=0; + dops[i].rt1=0; + dops[i].rt2=0; break; default: - rs1[i]=0; - rs2[i]=0; - rt1[i]=0; - rt2[i]=0; + dops[i].rs1=0; + dops[i].rs2=0; + dops[i].rt1=0; + dops[i].rt2=0; } /* Calculate branch target addresses */ if(type==UJUMP) ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4); - else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1)) + else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1)) ba[i]=start+i*4+8; // Ignore never taken branch - else if(type==SJUMP&&rs1[i]==0&&!(op2&1)) + else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1)) ba[i]=start+i*4+8; // Ignore never taken branch else if(type==CJUMP||type==SJUMP) ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14); else ba[i]=-1; - if (i > 0 && is_jump(i-1)) { + + /* simplify always (not)taken branches */ + if (type == CJUMP && dops[i].rs1 == dops[i].rs2) { + dops[i].rs1 = dops[i].rs2 = 0; + if (!(op & 1)) { + dops[i].itype = type = UJUMP; + dops[i].rs2 = CCREG; + } + } + else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1)) + dops[i].itype = type = UJUMP; + + dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP); + dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0 + dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2 + dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2 + + /* messy cases to just pass over to the interpreter */ + if (i > 0 && dops[i-1].is_jump) { int do_in_intrp=0; // branch in delay slot? - if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP) { + if (dops[i].is_jump) { // don't handle first branch and call interpreter if it's hit - SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr); + SysPrintf("branch in delay slot @%08x (%08x)\n", start + i*4, start); do_in_intrp=1; } // basic load delay detection - else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) { + else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) { int t=(ba[i-1]-start)/4; - if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) { + if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) { // jump target wants DS result - potential load delay effect - SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr); + SysPrintf("load delay @%08x (%08x)\n", start + i*4, start); do_in_intrp=1; - bt[t+1]=1; // expected return from interpreter + dops[t+1].bt=1; // expected return from interpreter } - else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&& - !(i>=3&&is_jump(i-3))) { + else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&& + !(i>=3&&dops[i-3].is_jump)) { // v0 overwrite like this is a sign of trouble, bail out - SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr); + SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start); do_in_intrp=1; } } - if(do_in_intrp) { - rs1[i-1]=CCREG; - rs2[i-1]=rt1[i-1]=rt2[i-1]=0; - ba[i-1]=-1; - itype[i-1]=INTCALL; - done=2; + if (do_in_intrp) { + memset(&dops[i-1], 0, sizeof(dops[i-1])); + dops[i-1].itype = INTCALL; + dops[i-1].rs1 = CCREG; + ba[i-1] = -1; + done = 2; i--; // don't compile the DS } } + /* Is this the end of the block? */ - if (i > 0 && is_ujump(i-1)) { - if(rt1[i-1]==0) { // Continue past subroutine call (JAL) - done=2; + if (i > 0 && dops[i-1].is_ujump) { + if (dops[i-1].rt1 == 0) { // not jal + int found_bbranch = 0, t = (ba[i-1] - start) / 4; + if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) { + // scan for a branch back to i+1 + for (j = t; j < t + 64; j++) { + int tmpop = source[j] >> 26; + if (tmpop == 1 || ((tmpop & ~3) == 4)) { + int t2 = j + 1 + (int)(signed short)source[j]; + if (t2 == i + 1) { + //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4); + found_bbranch = 1; + break; + } + } + } + } + if (!found_bbranch) + done = 2; } else { if(stop_after_jal) done=1; // Stop on BREAK if((source[i+1]&0xfc00003f)==0x0d) done=1; } - // Don't recompile stuff that's already compiled - if(check_addr(start+i*4+4)) done=1; - // Don't get too close to the limit - if(i>MAXBLOCK/2) done=1; + // Don't recompile stuff that's already compiled + if(check_addr(start+i*4+4)) done=1; + // Don't get too close to the limit + if(i>MAXBLOCK/2) done=1; + } + if (dops[i].itype == SYSCALL || dops[i].itype == HLECALL || dops[i].itype == INTCALL) + done = stop_after_jal ? 1 : 2; + if (done == 2) { + // Does the block continue due to a branch? + for(j=i-1;j>=0;j--) + { + if(ba[j]==start+i*4) done=j=0; // Branch into delay slot + if(ba[j]==start+i*4+4) done=j=0; + if(ba[j]==start+i*4+8) done=j=0; + } + } + //assert(i 8 || dops[i].opcode == 0x11)) { + done=stop_after_jal=1; + SysPrintf("Disabled speculative precompilation\n"); + } + } + while (i > 0 && dops[i-1].is_jump) + i--; + assert(i > 0); + assert(!dops[i-1].is_jump); + slen = i; +} + +// Basic liveness analysis for MIPS registers +static noinline void pass2_unneeded_regs(int istart,int iend,int r) +{ + int i; + uint64_t u,gte_u,b,gte_b; + uint64_t temp_u,temp_gte_u=0; + uint64_t gte_u_unknown=0; + if (HACK_ENABLED(NDHACK_GTE_UNNEEDED)) + gte_u_unknown=~0ll; + if(iend==slen-1) { + u=1; + gte_u=gte_u_unknown; + }else{ + //u=unneeded_reg[iend+1]; + u=1; + gte_u=gte_unneeded[iend+1]; + } + + for (i=iend;i>=istart;i--) + { + //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r); + if(dops[i].is_jump) + { + // If subroutine call, flag return address as a possible branch target + if(dops[i].rt1==31 && i=(start+slen*4)) + { + // Branch out of this block, flush all regs + u=1; + gte_u=gte_u_unknown; + branch_unneeded_reg[i]=u; + // Merge in delay slot + u|=(1LL<>2].bt=1; + if(ba[i]<=start+i*4) { + // Backward branch + if(dops[i].is_ujump) + { + // Unconditional branch + temp_u=1; + temp_gte_u=0; + } else { + // Conditional branch (not taken case) + temp_u=unneeded_reg[i+2]; + temp_gte_u&=gte_unneeded[i+2]; + } + // Merge in delay slot + temp_u|=(1LL<>2,i-1,r+1); + }else{ + unneeded_reg[(ba[i]-start)>>2]=1; + gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown; + } + } /*else*/ if(1) { + if (dops[i].is_ujump) + { + // Unconditional branch + u=unneeded_reg[(ba[i]-start)>>2]; + gte_u=gte_unneeded[(ba[i]-start)>>2]; + branch_unneeded_reg[i]=u; + // Merge in delay slot + u|=(1LL<>2]; + gte_b=gte_unneeded[(ba[i]-start)>>2]; + branch_unneeded_reg[i]=b; + // Branch delay slot + b|=(1LL<=0;j--) - { - if(ba[j]==start+i*4) done=j=0; // Branch into delay slot - if(ba[j]==start+i*4+4) done=j=0; - if(ba[j]==start+i*4+8) done=j=0; - } + else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL) + { + // SYSCALL instruction (software interrupt) + u=1; } - //assert(i>r)&1) { + if(r==HIREG) printf(" HI"); + else if(r==LOREG) printf(" LO"); + else printf(" r%d",r); + } } + printf("\n"); + */ } - assert(slen>0); - - /* Pass 2 - Register dependencies and branch targets */ - - unneeded_registers(0,slen-1,0); - - /* Pass 3 - Register allocation */ +} +static noinline void pass3_register_alloc(u_int addr) +{ struct regstat current; // Current register allocations/status - current.dirty=0; - current.u=unneeded_reg[0]; + clear_all_regs(current.regmap_entry); clear_all_regs(current.regmap); - alloc_reg(¤t,0,CCREG); - dirty_reg(¤t,CCREG); - current.isconst=0; - current.wasconst=0; - current.waswritten=0; + current.wasdirty = current.dirty = 0; + current.u = unneeded_reg[0]; + alloc_reg(¤t, 0, CCREG); + dirty_reg(¤t, CCREG); + current.wasconst = 0; + current.isconst = 0; + current.loadedconst = 0; + current.waswritten = 0; int ds=0; int cc=0; - int hr=-1; + int hr; + int i, j; - if((u_int)addr&1) { + if (addr & 1) { // First instruction is delay slot cc=-1; - bt[1]=1; + dops[1].bt=1; ds=1; unneeded_reg[0]=1; current.regmap[HOST_BTREG]=BTREG; @@ -7639,9 +7075,8 @@ int new_recompile_block(u_int addr) for(i=0;i=TEMPREG){ + if(or<0||r>=TEMPREG){ regs[i].regmap_entry[hr]=-1; } else @@ -7973,7 +7411,7 @@ int new_recompile_block(u_int addr) // Just move it to a different register regs[i].regmap_entry[hr]=r; // If it was dirty before, it's still dirty - if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63); + if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r); } } else @@ -8004,26 +7442,26 @@ int new_recompile_block(u_int addr) memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap)); } - if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800) - current.waswritten|=1<=0x800) - current.waswritten&=~(1<0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800) + current.waswritten|=1<=0x800) + current.waswritten&=~(1<0) { current.wasdirty=current.dirty; - switch(itype[i-1]) { + switch(dops[i-1].itype) { case UJUMP: memcpy(&branch_regs[i-1],¤t,sizeof(current)); branch_regs[i-1].isconst=0; branch_regs[i-1].wasconst=0; - branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i]==SYSCALL||itype[i]==HLECALL)) + ccadj[i] = CLOCK_ADJUST(cc); + if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL)) { cc=0; } #if !defined(DRC_DBG) - else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2) + else if(dops[i].itype==C2OP&>e_cycletab[source[i]&0x3f]>2) { // this should really be removed since the real stalls have been implemented, // but doing so causes sizeable perf regression against the older version u_int gtec = gte_cycletab[source[i] & 0x3f]; cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2; } - else if(i>1&&itype[i]==STORE&&itype[i-1]==STORE&&itype[i-2]==STORE&&!bt[i]) + else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt) { cc+=4; } - else if(itype[i]==C2LS) + else if(dops[i].itype==C2LS) { // same as with C2OP cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2; @@ -8248,7 +7686,7 @@ int new_recompile_block(u_int addr) cc++; } - if(!is_ds[i]) { + if(!dops[i].is_ds) { regs[i].dirty=current.dirty; regs[i].isconst=current.isconst; memcpy(constmap[i],current_constmap,sizeof(constmap[i])); @@ -8263,15 +7701,19 @@ int new_recompile_block(u_int addr) if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1; regs[i].waswritten=current.waswritten; } +} - /* Pass 4 - Cull unused host registers */ - - uint64_t nr=0; +static noinline void pass4_cull_unused_regs(void) +{ + u_int last_needed_regs[4] = {0,0,0,0}; + u_int nr=0; + int i; for (i=slen-1;i>=0;i--) { int hr; - if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP) + __builtin_prefetch(regs[i-2].regmap); + if(dops[i].is_jump) { if(ba[i]=(start+slen*4)) { @@ -8292,10 +7734,10 @@ int new_recompile_block(u_int addr) } } // Conditional branch may need registers for following instructions - if (!is_ujump(i)) + if (!dops[i].is_ujump) { if(i=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1< 0 && !dops[i].bt && regs[i].wasdirty) for(hr=0;hr0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) { + if((regs[i].wasdirty>>hr)&1) { if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) { - if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) { - if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<>hr)&1)) { if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1; - if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] && - (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] && - (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG) - { - if (!is_ujump(i)) - { - if(likely[i]) { - regs[i].regmap[hr]=-1; - regs[i].isconst&=~(1<0) { - int map=-1,temp=-1; - if(itype[i]==STORE || itype[i]==STORELR || - (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2 - map=INVCP; - } - if(itype[i]==LOADLR || itype[i]==STORELR || - itype[i]==C1LS || itype[i]==C2LS) - temp=FTEMP; - if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] && - regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] && - (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map && - (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG)) + int map1 = -1, map2 = -1, temp=-1; + if (dops[i].is_load || dops[i].is_store) + map1 = ROREG; + if (dops[i].is_store) + map2 = INVCP; + if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS) + temp = FTEMP; + if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 && + regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 && + regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 && + //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG) + regs[i].regmap[hr] != CCREG) { - if(i0) if(regmap_pre[i+1][hr]!=regs[i].regmap[hr]) @@ -8479,35 +7909,38 @@ int new_recompile_block(u_int addr) } regs[i].regmap[hr]=-1; regs[i].isconst&=~(1<=start && ba[i]<(start+i*4)) - if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU - ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD - ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS - ||itype[i+1]==SHIFT||itype[i+1]==COP1 - ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP) + if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU + ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD + ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS + ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1 + ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP) { int t=(ba[i]-start)>>2; - if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP)) // loop_preload can't handle jumps into delay slots - if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated + if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots + if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated for(hr=0;hr=0) { @@ -8534,7 +7967,7 @@ int new_recompile_block(u_int addr) f_regmap[hr]=branch_regs[i].regmap[hr]; } } - if(ooo[i]) { + if(dops[i].ooo) { if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) f_regmap[hr]=branch_regs[i].regmap[hr]; }else{ @@ -8560,15 +7993,12 @@ int new_recompile_block(u_int addr) //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r); if(r<34&&((unneeded_reg[j]>>r)&1)) break; assert(r < 64); - if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63) %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r); int k; if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) { + if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break; if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break; - if(r>63) { - if(get_reg(regs[i].regmap,r&63)<0) break; - if(get_reg(branch_regs[i].regmap,r&63)<0) break; - } k=i; while(k>1&®s[k-1].regmap[hr]==-1) { if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) { @@ -8579,15 +8009,14 @@ int new_recompile_block(u_int addr) //printf("no-match due to different register\n"); break; } - if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP) { + if (dops[k-2].is_jump) { //printf("no-match due to branch\n"); break; } // call/ret fast path assumes no registers allocated - if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) { + if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) { break; } - assert(r < 64); k--; } if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) { @@ -8628,7 +8057,7 @@ int new_recompile_block(u_int addr) branch_regs[i].dirty|=(1<=0) + if(dops[i+1].rs1) { + if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0) { if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) { @@ -8810,8 +8243,8 @@ int new_recompile_block(u_int addr) } } } - if(rs2[i+1]) { - if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0) + if(dops[i+1].rs2) { + if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0) { if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) { @@ -8827,14 +8260,14 @@ int new_recompile_block(u_int addr) } } // Preload target address for load instruction (non-constant) - if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) { - if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0) + if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { + if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0) { if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) { - regs[i].regmap[hr]=rs1[i+1]; - regmap_pre[i+1][hr]=rs1[i+1]; - regs[i+1].regmap_entry[hr]=rs1[i+1]; + regs[i].regmap[hr]=dops[i+1].rs1; + regmap_pre[i+1][hr]=dops[i+1].rs1; + regs[i+1].regmap_entry[hr]=dops[i+1].rs1; regs[i].isconst&=~(1<=0) + if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { + if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0) { if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) { - regs[i].regmap[hr]=rs1[i+1]; - regmap_pre[i+1][hr]=rs1[i+1]; - regs[i+1].regmap_entry[hr]=rs1[i+1]; + regs[i].regmap[hr]=dops[i+1].rs1; + regmap_pre[i+1][hr]=dops[i+1].rs1; + regs[i+1].regmap_entry[hr]=dops[i+1].rs1; regs[i].isconst&=~(1<=0); if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) { - regs[i].regmap[hr]=rs1[i+1]; - regmap_pre[i+1][hr]=rs1[i+1]; - regs[i+1].regmap_entry[hr]=rs1[i+1]; + regs[i].regmap[hr]=dops[i+1].rs1; + regmap_pre[i+1][hr]=dops[i+1].rs1; + regs[i+1].regmap_entry[hr]=dops[i+1].rs1; regs[i].isconst&=~(1<=0); if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) { - regs[i].regmap[hr]=rs1[i+1]; - regmap_pre[i+1][hr]=rs1[i+1]; - regs[i+1].regmap_entry[hr]=rs1[i+1]; + regs[i].regmap[hr]=dops[i+1].rs1; + regmap_pre[i+1][hr]=dops[i+1].rs1; + regs[i+1].regmap_entry[hr]=dops[i+1].rs1; regs[i].isconst&=~(1<=0&®s[i].regmap[hr]<0) { - int rs=get_reg(regs[i+1].regmap,rs1[i+1]); - if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) { - regs[i].regmap[hr]=AGEN1+((i+1)&1); - regmap_pre[i+1][hr]=AGEN1+((i+1)&1); - regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1); - regs[i].isconst&=~(1<=0&®s[i].regmap[hr]<0) { + int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1); + if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) { + regs[i].regmap[hr]=AGEN1+((i+1)&1); + regmap_pre[i+1][hr]=AGEN1+((i+1)&1); + regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1); + regs[i].isconst&=~(1<=istart;i--) + { + signed char rregmap_i[RRMAP_SIZE]; + u_int hr_candirty = 0; + assert(HOST_REGS < 32); + make_rregs(regs[i].regmap, rregmap_i, &hr_candirty); + __builtin_prefetch(regs[i-1].regmap); + if(dops[i].is_jump) + { + signed char branch_rregmap_i[RRMAP_SIZE]; + u_int branch_hr_candirty = 0; + make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty); + if(ba[i]=(start+slen*4)) + { + // Branch out of this block, flush all regs + will_dirty_i = 0; + will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); + will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); + will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); + will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); + will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); + will_dirty_i &= branch_hr_candirty; + if (dops[i].is_ujump) + { + // Unconditional branch + wont_dirty_i = 0; + // Merge in delay slot (will dirty) + will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); + will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); + will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); + will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); + will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); + will_dirty_i &= hr_candirty; + } + else + { + // Conditional branch + wont_dirty_i = wont_dirty_next; + // Merge in delay slot (will dirty) + // (the original code had no explanation why these 2 are commented out) + //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); + //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); + will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); + will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); + will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); + will_dirty_i &= hr_candirty; + } + // Merge in delay slot (wont dirty) + wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); + wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); + wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); + wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); + wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); + wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); + wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); + wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); + wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); + wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); + wont_dirty_i &= ~(1u << 31); + if(wr) { + #ifndef DESTRUCTIVE_WRITEBACK + branch_regs[i].dirty&=wont_dirty_i; + #endif + branch_regs[i].dirty|=will_dirty_i; + } + } + else + { + // Internal branch + if(ba[i]<=start+i*4) { + // Backward branch + if (dops[i].is_ujump) + { + // Unconditional branch + temp_will_dirty=0; + temp_wont_dirty=0; + // Merge in delay slot (will dirty) + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); + temp_will_dirty &= branch_hr_candirty; + temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); + temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); + temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); + temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); + temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31); + temp_will_dirty &= hr_candirty; + } else { + // Conditional branch (not taken case) + temp_will_dirty=will_dirty_next; + temp_wont_dirty=wont_dirty_next; + // Merge in delay slot (will dirty) + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); + temp_will_dirty &= branch_hr_candirty; + //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); + //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); + temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); + temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); + temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31); + temp_will_dirty &= hr_candirty; + } + // Merge in delay slot (wont dirty) + temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); + temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); + temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); + temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); + temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31); + temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); + temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); + temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); + temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); + temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); + temp_wont_dirty &= ~(1u << 31); + // Deal with changed mappings + if(i0 && regmap_pre[i][r]<34) { + temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<>regmap_pre[i][r])&1)<>2,i-1,0); + }else{ + // Limit recursion. It can take an excessive amount + // of time if there are a lot of nested loops. + will_dirty[(ba[i]-start)>>2]=0; + wont_dirty[(ba[i]-start)>>2]=-1; + } + } + /*else*/ if(1) + { + if (dops[i].is_ujump) + { + // Unconditional branch + will_dirty_i=0; + wont_dirty_i=0; + //if(ba[i]>start+i*4) { // Disable recursion (for debugging) + for(r=0;r>2].regmap_entry[r]) { + will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<>2]&(1<=0) { + will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<>2]>>branch_regs[i].regmap[r])&1)<start+i*4) // Disable recursion (for debugging) + for(r=0;r>2].regmap_entry[r]) { + will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<>2]&(1<=0) { + will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<>2]>>target_reg)&1)< istart && !dops[i].is_jump) { + // Don't store a register immediately after writing it, + // may prevent dual-issue. + wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31); + wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31); + } + // Save it + will_dirty[i]=will_dirty_i; + wont_dirty[i]=wont_dirty_i; + // Mark registers that won't be dirtied as not dirty + if(wr) { + regs[i].dirty|=will_dirty_i; + #ifndef DESTRUCTIVE_WRITEBACK + regs[i].dirty&=wont_dirty_i; + if(dops[i].is_jump) + { + if (i < iend-1 && !dops[i].is_ujump) { + for(r=0;r>r)&1));*/} + } + } + } + } + else + { + if(i>r)&1));*/} } } } } + #endif + } + // Deal with changed mappings + temp_will_dirty=will_dirty_i; + temp_wont_dirty=wont_dirty_i; + for(r=0;r=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) { + // Register moved to a different register + will_dirty_i&=~(1<>nr)&1)<>nr)&1)<0 && regmap_pre[i][r]<34) { + will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<>regmap_pre[i][r])&1)<>r)&1));*/ + } + } + } + } + } +} + +static noinline void pass10_expire_blocks(void) +{ + u_int step = MAX_OUTPUT_BLOCK_SIZE / PAGE_COUNT / 2; + // not sizeof(ndrc->translation_cache) due to vita hack + u_int step_mask = ((1u << TARGET_SIZE_2) - 1u) & ~(step - 1u); + u_int end = (out - ndrc->translation_cache + EXPIRITY_OFFSET) & step_mask; + u_int base_shift = __builtin_ctz(MAX_OUTPUT_BLOCK_SIZE); + int hit; + + for (; expirep != end; expirep = ((expirep + step) & step_mask)) + { + u_int base_offs = expirep & ~(MAX_OUTPUT_BLOCK_SIZE - 1); + u_int block_i = expirep / step & (PAGE_COUNT - 1); + u_int phase = (expirep >> (base_shift - 1)) & 1u; + if (!(expirep & (MAX_OUTPUT_BLOCK_SIZE / 2 - 1))) { + inv_debug("EXP: base_offs %x/%x phase %u\n", base_offs, + out - ndrc->translation_cache phase); + } + + if (!phase) { + hit = blocks_remove_matching_addrs(&blocks[block_i], base_offs, base_shift); + if (hit) { + do_clear_cache(); + #ifdef USE_MINI_HT + memset(mini_ht, -1, sizeof(mini_ht)); + #endif } } + else + ll_remove_matching_addrs(&jump_out[block_i], base_offs, base_shift); + } +} + +static struct block_info *new_block_info(u_int start, u_int len, + const void *source, const void *copy, u_char *beginning, u_short jump_in_count) +{ + struct block_info **b_pptr; + struct block_info *block; + u_int page = get_page(start); + + block = malloc(sizeof(*block) + jump_in_count * sizeof(block->jump_in[0])); + assert(block); + assert(jump_in_count > 0); + block->source = source; + block->copy = copy; + block->start = start; + block->len = len; + block->reg_sv_flags = 0; + block->tc_offs = beginning - ndrc->translation_cache; + //block->tc_len = out - beginning; + block->is_dirty = 0; + block->jump_in_cnt = jump_in_count; + + // insert sorted by start mirror-unmasked vaddr + for (b_pptr = &blocks[page]; ; b_pptr = &((*b_pptr)->next)) { + if (*b_pptr == NULL || (*b_pptr)->start >= start) { + block->next = *b_pptr; + *b_pptr = block; + break; + } + } + stat_inc(stat_blocks); + return block; +} + +static int new_recompile_block(u_int addr) +{ + u_int pagelimit = 0; + u_int state_rflags = 0; + int i; + + assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out); + + // this is just for speculation + for (i = 1; i < 32; i++) { + if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000) + state_rflags |= 1 << i; + } + + assert(!(addr & 3)); + start = addr & ~3; + new_dynarec_did_compile=1; + if (Config.HLE && start == 0x80001000) // hlecall + { + // XXX: is this enough? Maybe check hleSoftCall? + void *beginning = start_block(); + + emit_movimm(start,0); + emit_writeword(0,&pcaddr); + emit_far_jump(new_dyna_leave); + literal_pool(0); + end_block(beginning); + struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1); + block->jump_in[0].vaddr = start; + block->jump_in[0].addr = beginning; + return 0; + } + else if (f1_hack && hack_addr == 0) { + void *beginning = start_block(); + emit_movimm(start, 0); + emit_writeword(0, &hack_addr); + emit_readword(&psxRegs.GPR.n.sp, 0); + emit_readptr(&mem_rtab, 1); + emit_shrimm(0, 12, 2); + emit_readptr_dualindexedx_ptrlen(1, 2, 1); + emit_addimm(0, 0x18, 0); + emit_adds_ptr(1, 1, 1); + emit_ldr_dualindexed(1, 0, 0); + emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp) + emit_far_call(ndrc_get_addr_ht); + emit_jmpreg(0); // jr k0 + literal_pool(0); + end_block(beginning); + + struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1); + block->jump_in[0].vaddr = start; + block->jump_in[0].addr = beginning; + SysPrintf("F1 hack to %08x\n", start); + return 0; + } + + cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT + ? cycle_multiplier_override : cycle_multiplier; + + source = get_source_start(start, &pagelimit); + if (source == NULL) { + if (addr != hack_addr) { + SysPrintf("Compile at bogus memory address: %08x\n", addr); + hack_addr = addr; + } + //abort(); + return -1; } + /* Pass 1: disassemble */ + /* Pass 2: register dependencies, branch targets */ + /* Pass 3: register allocation */ + /* Pass 4: branch dependencies */ + /* Pass 5: pre-alloc */ + /* Pass 6: optimize clean/dirty state */ + /* Pass 7: flag 32-bit registers */ + /* Pass 8: assembly */ + /* Pass 9: linker */ + /* Pass 10: garbage collection / free memory */ + + /* Pass 1 disassembly */ + + pass1_disassemble(pagelimit); + + int clear_hack_addr = apply_hacks(); + + /* Pass 2 - Register dependencies and branch targets */ + + pass2_unneeded_regs(0,slen-1,0); + + /* Pass 3 - Register allocation */ + + pass3_register_alloc(addr); + + /* Pass 4 - Cull unused host registers */ + + pass4_cull_unused_regs(); + + /* Pass 5 - Pre-allocate registers */ + + pass5a_preallocate1(); + pass5b_preallocate2(); + /* Pass 6 - Optimize clean/dirty state */ - clean_registers(0,slen-1,1); + pass6_clean_registers(0, slen-1, 1); /* Pass 7 - Identify 32-bit registers */ for (i=slen-1;i>=0;i--) { - if(itype[i]==CJUMP||itype[i]==SJUMP) + if(dops[i].itype==CJUMP||dops[i].itype==SJUMP) { // Conditional branch if((source[i]>>16)!=0x1000&&i>r)&1) { - if(r==HIREG) printf(" HI"); - else if(r==LOREG) printf(" LO"); - else printf(" r%d",r); + dops[i+2].bt=1; } } - printf("\n"); - #if defined(__i386__) || defined(__x86_64__) - printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]); - #endif - #ifdef __arm__ - printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]); - #endif - #if defined(__i386__) || defined(__x86_64__) - printf("needs: "); - if(needed_reg[i]&1) printf("eax "); - if((needed_reg[i]>>1)&1) printf("ecx "); - if((needed_reg[i]>>2)&1) printf("edx "); - if((needed_reg[i]>>3)&1) printf("ebx "); - if((needed_reg[i]>>5)&1) printf("ebp "); - if((needed_reg[i]>>6)&1) printf("esi "); - if((needed_reg[i]>>7)&1) printf("edi "); - printf("\n"); - printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]); - printf("dirty: "); - if(regs[i].wasdirty&1) printf("eax "); - if((regs[i].wasdirty>>1)&1) printf("ecx "); - if((regs[i].wasdirty>>2)&1) printf("edx "); - if((regs[i].wasdirty>>3)&1) printf("ebx "); - if((regs[i].wasdirty>>5)&1) printf("ebp "); - if((regs[i].wasdirty>>6)&1) printf("esi "); - if((regs[i].wasdirty>>7)&1) printf("edi "); - #endif - #ifdef __arm__ - printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]); - printf("dirty: "); - if(regs[i].wasdirty&1) printf("r0 "); - if((regs[i].wasdirty>>1)&1) printf("r1 "); - if((regs[i].wasdirty>>2)&1) printf("r2 "); - if((regs[i].wasdirty>>3)&1) printf("r3 "); - if((regs[i].wasdirty>>4)&1) printf("r4 "); - if((regs[i].wasdirty>>5)&1) printf("r5 "); - if((regs[i].wasdirty>>6)&1) printf("r6 "); - if((regs[i].wasdirty>>7)&1) printf("r7 "); - if((regs[i].wasdirty>>8)&1) printf("r8 "); - if((regs[i].wasdirty>>9)&1) printf("r9 "); - if((regs[i].wasdirty>>10)&1) printf("r10 "); - if((regs[i].wasdirty>>12)&1) printf("r12 "); - #endif - printf("\n"); - disassemble_inst(i); - //printf ("ccadj[%d] = %d\n",i,ccadj[i]); - #if defined(__i386__) || defined(__x86_64__) - printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]); - if(regs[i].dirty&1) printf("eax "); - if((regs[i].dirty>>1)&1) printf("ecx "); - if((regs[i].dirty>>2)&1) printf("edx "); - if((regs[i].dirty>>3)&1) printf("ebx "); - if((regs[i].dirty>>5)&1) printf("ebp "); - if((regs[i].dirty>>6)&1) printf("esi "); - if((regs[i].dirty>>7)&1) printf("edi "); - #endif - #ifdef __arm__ - printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]); - if(regs[i].dirty&1) printf("r0 "); - if((regs[i].dirty>>1)&1) printf("r1 "); - if((regs[i].dirty>>2)&1) printf("r2 "); - if((regs[i].dirty>>3)&1) printf("r3 "); - if((regs[i].dirty>>4)&1) printf("r4 "); - if((regs[i].dirty>>5)&1) printf("r5 "); - if((regs[i].dirty>>6)&1) printf("r6 "); - if((regs[i].dirty>>7)&1) printf("r7 "); - if((regs[i].dirty>>8)&1) printf("r8 "); - if((regs[i].dirty>>9)&1) printf("r9 "); - if((regs[i].dirty>>10)&1) printf("r10 "); - if((regs[i].dirty>>12)&1) printf("r12 "); - #endif - printf("\n"); - if(regs[i].isconst) { - printf("constants: "); - #if defined(__i386__) || defined(__x86_64__) - if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]); - if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]); - if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]); - if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]); - if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]); - if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]); - if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]); - #endif - #if defined(__arm__) || defined(__aarch64__) - int r; - for (r = 0; r < ARRAY_SIZE(constmap[i]); r++) - if ((regs[i].isconst >> r) & 1) - printf(" r%d=%x", r, (u_int)constmap[i][r]); - #endif - printf("\n"); - } - if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP) { - #if defined(__i386__) || defined(__x86_64__) - printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); - if(branch_regs[i].dirty&1) printf("eax "); - if((branch_regs[i].dirty>>1)&1) printf("ecx "); - if((branch_regs[i].dirty>>2)&1) printf("edx "); - if((branch_regs[i].dirty>>3)&1) printf("ebx "); - if((branch_regs[i].dirty>>5)&1) printf("ebp "); - if((branch_regs[i].dirty>>6)&1) printf("esi "); - if((branch_regs[i].dirty>>7)&1) printf("edi "); - #endif - #ifdef __arm__ - printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]); - if(branch_regs[i].dirty&1) printf("r0 "); - if((branch_regs[i].dirty>>1)&1) printf("r1 "); - if((branch_regs[i].dirty>>2)&1) printf("r2 "); - if((branch_regs[i].dirty>>3)&1) printf("r3 "); - if((branch_regs[i].dirty>>4)&1) printf("r4 "); - if((branch_regs[i].dirty>>5)&1) printf("r5 "); - if((branch_regs[i].dirty>>6)&1) printf("r6 "); - if((branch_regs[i].dirty>>7)&1) printf("r7 "); - if((branch_regs[i].dirty>>8)&1) printf("r8 "); - if((branch_regs[i].dirty>>9)&1) printf("r9 "); - if((branch_regs[i].dirty>>10)&1) printf("r10 "); - if((branch_regs[i].dirty>>12)&1) printf("r12 "); - #endif - } } -#endif // DISASM /* Pass 8 - Assembly */ linkcount=0;stubcount=0; - ds=0;is_delayslot=0; + is_delayslot=0; u_int dirty_pre=0; void *beginning=start_block(); - if((u_int)addr&1) { - ds=1; - pagespan_ds(); - } void *instr_addr0_override = NULL; + int ds = 0; if (start == 0x80030000) { // nasty hack for the fastbios thing @@ -9128,27 +8950,31 @@ int new_recompile_block(u_int addr) } for(i=0;i\n"); - drc_dbg_emit_do_cmp(i); + drc_dbg_emit_do_cmp(i, ccadj[i]); + if (clear_hack_addr) { + emit_movimm(0, 0); + emit_writeword(0, &hack_addr); + clear_hack_addr = 0; + } // load regs if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG) wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty); - load_regs(regs[i].regmap_entry,regs[i].regmap,rs1[i],rs2[i]); + load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2); address_generation(i,®s[i],regs[i].regmap_entry); load_consts(regmap_pre[i],regs[i].regmap,i); - if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP) + if(dops[i].is_jump) { // Load the delay slot registers if necessary - if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0)) - load_regs(regs[i].regmap_entry,regs[i].regmap,rs1[i+1],rs1[i+1]); - if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0)) - load_regs(regs[i].regmap_entry,regs[i].regmap,rs2[i+1],rs2[i+1]); - if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) - load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP); + if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0)) + load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1); + if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0)) + load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2); + if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) + load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG); + if (dops[i+1].is_store) + load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP); } else if(i+1 0); - if (itype[slen-1] == INTCALL) { + if (slen > 0 && dops[slen-1].itype == INTCALL) { // no ending needed for this block since INTCALL never returns } // If the block did not end with an unconditional branch, // add a jump to the next instruction. else if (i > 1) { - if(!is_ujump(i-2)&&itype[i-1]!=SPAN) { - assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP); + if (!dops[i-2].is_ujump) { + assert(!dops[i-1].is_jump); assert(i==slen); - if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP) { + if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) { store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4); if(regs[i-1].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG); + emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG); } - else if(!likely[i-2]) + else { store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4); assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG); } - else - { - store_regs_bt(regs[i-2].regmap,regs[i-2].dirty,start+i*4); - assert(regs[i-2].regmap[HOST_CCREG]==CCREG); - } add_to_linker(out,start+i*4,0); emit_jmp(0); } @@ -9282,11 +9062,11 @@ int new_recompile_block(u_int addr) else { assert(i>0); - assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP); + assert(!dops[i-1].is_jump); store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4); if(regs[i-1].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG); + emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG); add_to_linker(out,start+i*4,0); emit_jmp(0); } @@ -9323,19 +9103,30 @@ int new_recompile_block(u_int addr) if (instr_addr0_override) instr_addr[0] = instr_addr0_override; +#if 0 + /* check for improper expiration */ + for (i = 0; i < ARRAY_SIZE(jumps); i++) { + int j; + if (!jumps[i]) + continue; + for (j = 0; j < jumps[i]->count; j++) + assert(jumps[i]->e[j].stub < beginning || (u_char *)jumps[i]->e[j].stub > out); + } +#endif + /* Pass 9 - Linker */ for(i=0;i %8x\n",link_addr[i].addr,link_addr[i].target); literal_pool(64); - if (!link_addr[i].ext) + if (!link_addr[i].internal) { void *stub = out; void *addr = check_addr(link_addr[i].target); emit_extjump(link_addr[i].addr, link_addr[i].target); if (addr) { set_jump_target(link_addr[i].addr, addr); - add_jump_out(link_addr[i].target,stub); + ndrc_add_jump_out(link_addr[i].target,stub); } else set_jump_target(link_addr[i].addr, stub); @@ -9355,7 +9146,7 @@ int new_recompile_block(u_int addr) } u_int source_len = slen*4; - if (itype[slen-1] == INTCALL && source_len > 4) + if (dops[slen-1].itype == INTCALL && source_len > 4) // no need to treat the last instruction as compiled // as interpreter fully handles it source_len -= 4; @@ -9364,35 +9155,41 @@ int new_recompile_block(u_int addr) copy = shadow; // External Branch Targets (jump_in) - for(i=0;ireg_sv_flags = state_rflags; + + int jump_in_i = 0; + for (i = 0; i < slen; i++) { - if(bt[i]||i==0) + if ((i == 0 || dops[i].bt) && instr_addr[i]) { - if(instr_addr[i]) // TODO - delay slots (=null) - { - u_int vaddr=start+i*4; - u_int page=get_page(vaddr); - u_int vpage=get_vpage(vaddr); - literal_pool(256); - { - assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4); - assem_debug("jump_in: %x\n",start+i*4); - ll_add(jump_dirty+vpage,vaddr,out); - void *entry_point = do_dirty_stub(i, source_len); - ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point); - // If there was an existing entry in the hash table, - // replace it with the new address. - // Don't add new entries. We'll insert the - // ones that actually get used in check_addr(). - struct ht_entry *ht_bin = hash_table_get(vaddr); - if (ht_bin->vaddr[0] == vaddr) - ht_bin->tcaddr[0] = entry_point; - if (ht_bin->vaddr[1] == vaddr) - ht_bin->tcaddr[1] = entry_point; - } - } + assem_debug("%p (%d) <- %8x\n", instr_addr[i], i, start + i*4); + u_int vaddr = start + i*4; + + literal_pool(256); + void *entry = out; + load_regs_entry(i); + if (entry == out) + entry = instr_addr[i]; + else + emit_jmp(instr_addr[i]); + + block->jump_in[jump_in_i].vaddr = vaddr; + block->jump_in[jump_in_i].addr = entry; + jump_in_i++; } } + assert(jump_in_i == jump_in_count); + hash_table_add(block->jump_in[0].vaddr, block->jump_in[0].addr); // Write out the literal pool if necessary literal_pool(0); #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK @@ -9412,73 +9209,16 @@ int new_recompile_block(u_int addr) out = ndrc->translation_cache; // Trap writes to any of the pages we compiled - for(i=start>>12;i<=(start+slen*4)>>12;i++) { - invalid_code[i]=0; - } - inv_code_start=inv_code_end=~0; - - // for PCSX we need to mark all mirrors too - if(get_page(start)<(RAM_SIZE>>12)) - for(i=start>>12;i<=(start+slen*4)>>12;i++) - invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]= - invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]= - invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0; + mark_invalid_code(start, slen*4, 0); /* Pass 10 - Free memory by expiring oldest blocks */ - int end=(((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535; - while(expirep!=end) - { - int shift=TARGET_SIZE_2-3; // Divide into 8 blocks - uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block - uintptr_t base_offs_s = base_offs >> shift; - inv_debug("EXP: Phase %d\n",expirep); - switch((expirep>>11)&3) - { - case 0: - // Clear jump_in and jump_dirty - ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift); - ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift); - ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift); - ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift); - break; - case 1: - // Clear pointers - ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift); - ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift); - break; - case 2: - // Clear hash table - for(i=0;i<32;i++) { - struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i]; - uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache; - uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE; - if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) { - inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]); - ht_bin->vaddr[1] = -1; - ht_bin->tcaddr[1] = NULL; - } - o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache; - o2 = o1 - MAX_OUTPUT_BLOCK_SIZE; - if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) { - inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]); - ht_bin->vaddr[0] = ht_bin->vaddr[1]; - ht_bin->tcaddr[0] = ht_bin->tcaddr[1]; - ht_bin->vaddr[1] = -1; - ht_bin->tcaddr[1] = NULL; - } - } - break; - case 3: - // Clear jump_out - if((expirep&2047)==0) - do_clear_cache(); - ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift); - ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift); - break; - } - expirep=(expirep+1)&65535; - } + pass10_expire_blocks(); + +#ifdef ASSEM_PRINT + fflush(stdout); +#endif + stat_inc(stat_bc_direct); return 0; }