X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fnew_dynarec.c;h=88c059aba139ab895a85e40508861db83802818e;hp=e4e6a9afb4030d0fe3df3e6618826d00649a60a8;hb=1fd1aceb4382827b39bda6fe6915e38a294534e6;hpb=f76eeef94001323d5019a134c54847ece2493ae9

diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c
index e4e6a9af..88c059ab 100644
--- a/libpcsxcore/new_dynarec/new_dynarec.c
+++ b/libpcsxcore/new_dynarec/new_dynarec.c
@@ -680,8 +680,8 @@ void lsn(u_char hsn[], int i, int *preferred_reg)
   if(itype[i]==LOADLR) {
     hsn[FTEMP]=0;
   }
-  // Also 64-bit SDL/SDR
-  if(opcode[i]==0x2c||opcode[i]==0x2d) {
+  // Also SWL/SWR/SDL/SDR
+  if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
     hsn[FTEMP]=0;
   }
   // Don't remove the TLB registers either
@@ -1153,7 +1153,7 @@ void invalidate_block(u_int block)
     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
       get_bounds((int)head->addr,&start,&end);
       //printf("start: %x end: %x\n",start,end);
-      if(page<2048&&start>=0x80000000&&end<0x80800000) {
+      if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
@@ -1266,7 +1266,7 @@ void clean_blocks(u_int page)
           u_int i;
           u_int inv=0;
           get_bounds((int)head->addr,&start,&end);
-          if(start-(u_int)rdram<0x800000) {
+          if(start-(u_int)rdram<RAM_SIZE) {
             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
               inv|=invalid_code[i];
             }
@@ -1276,7 +1276,7 @@ void clean_blocks(u_int page)
             //printf("addr=%x start=%x end=%x\n",addr,start,end);
             if(addr<start||addr>=end) inv=1;
           }
-          else if((signed int)head->vaddr>=(signed int)0x80800000) {
+          else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
             inv=1;
           }
           if(!inv) {
@@ -1638,7 +1638,7 @@ void store_alloc(struct regstat *current,int i)
   // On CPUs without 32-bit immediates we need a pointer to invalid_code
   else alloc_reg(current,i,INVCP);
   #endif
-  if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR
+  if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
     alloc_reg(current,i,FTEMP);
   }
   // We need a temporary register for address generation
@@ -2746,7 +2746,7 @@ void load_assemble(int i,struct regstat *i_regs)
   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
   if(s>=0) {
     c=(i_regs->wasconst>>s)&1;
-    memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
+    memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
   }
   //printf("load_assemble: c=%d\n",c);
@@ -2774,10 +2774,10 @@ void load_assemble(int i,struct regstat *i_regs)
 //#define R29_HACK 1
         #ifdef R29_HACK
         // Strmnnrmn's speed hack
-        if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
+        if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
         #endif
         {
-          emit_cmpimm(addr,0x800000);
+          emit_cmpimm(addr,RAM_SIZE);
           jaddr=(int)out;
           #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
           // Hint to branch predictor that the branch is unlikely to be taken
@@ -3020,7 +3020,7 @@ void store_assemble(int i,struct regstat *i_regs)
   offset=imm[i];
   if(s>=0) {
     c=(i_regs->wasconst>>s)&1;
-    memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
+    memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
   }
   assert(tl>=0);
@@ -3036,14 +3036,14 @@ void store_assemble(int i,struct regstat *i_regs)
       #ifdef R29_HACK
       // Strmnnrmn's speed hack
       memtarget=1;
-      if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
+      if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
       #endif
-      emit_cmpimm(addr,0x800000);
+      emit_cmpimm(addr,RAM_SIZE);
       #ifdef DESTRUCTIVE_SHIFT
       if(s==addr) emit_mov(s,temp);
       #endif
       #ifdef R29_HACK
-      if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
+      if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
       #endif
       {
         jaddr=(int)out;
@@ -3193,15 +3193,17 @@ void storelr_assemble(int i,struct regstat *i_regs)
   int case1,case2,case3;
   int done0,done1,done2;
   int memtarget,c=0;
+  int agr=AGEN1+(i&1);
   u_int hr,reglist=0;
   th=get_reg(i_regs->regmap,rs2[i]|64);
   tl=get_reg(i_regs->regmap,rs2[i]);
   s=get_reg(i_regs->regmap,rs1[i]);
-  temp=get_reg(i_regs->regmap,-1);
+  temp=get_reg(i_regs->regmap,agr);
+  if(temp<0) temp=get_reg(i_regs->regmap,-1);
   offset=imm[i];
   if(s>=0) {
     c=(i_regs->isconst>>s)&1;
-    memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
+    memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
   }
   assert(tl>=0);
@@ -3212,7 +3214,7 @@ void storelr_assemble(int i,struct regstat *i_regs)
     assert(temp>=0);
     if(!using_tlb) {
       if(!c) {
-        emit_cmpimm(s<0||offset?temp:s,0x800000);
+        emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
         if(!offset&&s!=temp) emit_mov(s,temp);
         jaddr=(int)out;
         emit_jno(0);
@@ -3379,7 +3381,7 @@ void storelr_assemble(int i,struct regstat *i_regs)
       set_jump_target(done0,(int)out);
     }
     if(!c||!memtarget)
-      add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist);
+      add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
   }
   if(!using_tlb) {
     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
@@ -3464,7 +3466,7 @@ void c1ls_assemble(int i,struct regstat *i_regs)
   // Generate address + offset
   if(!using_tlb) {
     if(!c)
-      emit_cmpimm(offset||c||s<0?ar:s,0x800000);
+      emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
   }
   else
   {
@@ -3495,7 +3497,7 @@ void c1ls_assemble(int i,struct regstat *i_regs)
       jaddr2=(int)out;
       emit_jno(0);
     }
-    else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
+    else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
       jaddr2=(int)out;
       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
     }
@@ -3596,7 +3598,7 @@ void c2ls_assemble(int i,struct regstat *i_regs)
   int s,tl;
   int ar;
   int offset;
-  int c=0;
+  int memtarget=0,c=0;
   int jaddr,jaddr2=0,jaddr3,type;
   int agr=AGEN1+(i&1);
   u_int hr,reglist=0;
@@ -3622,36 +3624,41 @@ void c2ls_assemble(int i,struct regstat *i_regs)
   } else { // LWC2
     ar=tl;
   }
+  if(s>=0) c=(i_regs->wasconst>>s)&1;
+  memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
   if (!offset&&!c&&s>=0) ar=s;
   assert(ar>=0);
 
   if (opcode[i]==0x3a) { // SWC2
     cop2_get_dreg(copr,tl,HOST_TEMPREG);
+    type=STOREW_STUB;
   }
-  if(s>=0) c=(i_regs->wasconst>>s)&1;
-  if(!c) {
-    emit_cmpimm(offset||c||s<0?ar:s,0x800000);
-    jaddr2=(int)out;
-    emit_jno(0);
-  }
-  else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
-    jaddr2=(int)out;
-    emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
-  }
-  if (opcode[i]==0x32) { // LWC2
-    #ifdef HOST_IMM_ADDR32
-    if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
-    else
-    #endif
-    emit_readword_indexed(0,ar,tl);
+  else
     type=LOADW_STUB;
+
+  if(c&&!memtarget) {
+    jaddr2=(int)out;
+    emit_jmp(0); // inline_readstub/inline_writestub?
   }
-  if (opcode[i]==0x3a) { // SWC2
-#ifdef DESTRUCTIVE_SHIFT
-    if(!offset&&!c&&s>=0) emit_mov(s,ar);
-#endif
-    emit_writeword_indexed(tl,0,ar);
-    type=STOREW_STUB;
+  else {
+    if(!c) {
+      emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
+      jaddr2=(int)out;
+      emit_jno(0);
+    }
+    if (opcode[i]==0x32) { // LWC2
+      #ifdef HOST_IMM_ADDR32
+      if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
+      else
+      #endif
+      emit_readword_indexed(0,ar,tl);
+    }
+    if (opcode[i]==0x3a) { // SWC2
+      #ifdef DESTRUCTIVE_SHIFT
+      if(!offset&&!c&&s>=0) emit_mov(s,ar);
+      #endif
+      emit_writeword_indexed(tl,0,ar);
+    }
   }
   if(jaddr2)
     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
@@ -3962,7 +3969,7 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
     if(itype[i]==C1LS||itype[i]==C2LS) {
       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
         ra=get_reg(i_regs->regmap,FTEMP);
-      else { // SWC1/SDC1
+      else { // SWC1/SDC1/SWC2/SDC2
         ra=get_reg(i_regs->regmap,agr);
         if(ra<0) ra=get_reg(i_regs->regmap,-1);
       }
@@ -4002,7 +4009,7 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
               // Stores to memory go thru the mapper to detect self-modifying
               // code, loads don't.
               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
-                 (unsigned int)(constmap[i][rs]+offset)<0x80800000 )
+                 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
                 generate_map_const(constmap[i][rs]+offset,rm);
             }else{
               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
@@ -4052,7 +4059,7 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
           // Stores to memory go thru the mapper to detect self-modifying
           // code, loads don't.
           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
-             (unsigned int)(constmap[i+1][rs]+offset)<0x80800000 )
+             (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
             generate_map_const(constmap[i+1][rs]+offset,ra);
         }else{
           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
@@ -5619,7 +5626,7 @@ void sjump_assemble(int i,struct regstat *i_regs)
   #endif
 
   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
-  assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
+  //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
 
   if(ooo)
     if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))
@@ -5628,8 +5635,7 @@ void sjump_assemble(int i,struct regstat *i_regs)
     // First test branch condition, then execute delay slot, then branch
     ooo=0;
   }
-  // TODO: Conditional branches w/link must execute in-order so that
-  // condition test and write to r31 occur before cycle count test
+  assert(opcode2[i]<0x10||ooo); // FIXME (BxxZALL)
 
   if(ooo) {
     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
@@ -5724,7 +5730,7 @@ void sjump_assemble(int i,struct regstat *i_regs)
       if(!only32)
       {
         assert(s1h>=0);
-        if(opcode2[i]==0) // BLTZ
+        if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
         {
           emit_test(s1h,s1h);
           if(invert){
@@ -5735,7 +5741,7 @@ void sjump_assemble(int i,struct regstat *i_regs)
             emit_js(0);
           }
         }
-        if(opcode2[i]==1) // BGEZ
+        if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
         {
           emit_test(s1h,s1h);
           if(invert){
@@ -5750,7 +5756,7 @@ void sjump_assemble(int i,struct regstat *i_regs)
       else
       {
         assert(s1l>=0);
-        if(opcode2[i]==0) // BLTZ
+        if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
         {
           emit_test(s1l,s1l);
           if(invert){
@@ -5761,7 +5767,7 @@ void sjump_assemble(int i,struct regstat *i_regs)
             emit_js(0);
           }
         }
-        if(opcode2[i]==1) // BGEZ
+        if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
         {
           emit_test(s1l,s1l);
           if(invert){
@@ -6535,7 +6541,7 @@ void unneeded_registers(int istart,int iend,int r)
         {
           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
         }
-        if(start>0x80000400&&start<0x80800000) {
+        if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
           if(itype[i]==UJUMP&&rt1[i]==31)
           {
             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
@@ -7764,9 +7770,9 @@ int new_recompile_block(int addr)
   }
   else
 #endif
-  if ((int)addr >= 0x80000000 && (int)addr < 0x80800000) {
+  if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
     source = (u_int *)((u_int)rdram+start-0x80000000);
-    pagelimit = 0x80800000;
+    pagelimit = 0x80000000+RAM_SIZE;
   }
 #ifndef DISABLE_TLB
   else if ((signed int)addr >= (signed int)0xC0000000) {
@@ -8050,10 +8056,12 @@ int new_recompile_block(int addr)
       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
+#ifndef FORCE32
       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
+#endif
       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
@@ -8066,20 +8074,26 @@ int new_recompile_block(int addr)
       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
+#ifndef FORCE32
       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
+#endif
       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
+#ifndef FORCE32
       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
+#endif
       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
+#ifndef FORCE32
       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
+#endif
 #ifdef PCSX
       case 0x12: strcpy(insn[i],"COP2"); type=NI;
         op2=(source[i]>>21)&0x1f;
@@ -8102,7 +8116,7 @@ int new_recompile_block(int addr)
       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
 #endif
       default: strcpy(insn[i],"???"); type=NI;
-        printf("NI %08x @%08x\n", source[i], addr + i*4);
+        printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
         break;
     }
     itype[i]=type;
@@ -8357,9 +8371,9 @@ int new_recompile_block(int addr)
       // Don't get too close to the limit
       if(i>MAXBLOCK/2) done=1;
     }
-    if(i>0&&itype[i-1]==SYSCALL&&stop_after_jal) done=1;
-    if(itype[i-1]==HLECALL) done=1;
-    assert(i<MAXBLOCK-1);
+    if(itype[i]==SYSCALL&&stop_after_jal) done=1;
+    if(itype[i]==HLECALL) done=1;
+    //assert(i<MAXBLOCK-1);
     if(start+i*4==pagelimit-4) done=1;
     assert(start+i*4<pagelimit);
     if (i==MAXBLOCK-1) done=1;