X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fnew_dynarec.c;h=8fe3f93df121db933faf2e81ca04f0fb8fbf4d3f;hp=72f18bff13dc018a283f694046cc93587b50054c;hb=7ebfcedf465063e7692daac83081a556abeb41c1;hpb=cf95b4f0e912b19298e38ae60dd66a9f4a773e9b diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index 72f18bff..8fe3f93d 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -116,13 +116,13 @@ enum stub_type { struct regstat { - signed char regmap_entry[HOST_REGS]; + signed char regmap_entry[HOST_REGS]; // pre-insn + loop preloaded regs? signed char regmap[HOST_REGS]; uint64_t wasdirty; uint64_t dirty; uint64_t u; - u_int wasconst; - u_int isconst; + u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true + u_int isconst; // ... but isconst is false when r2 is known u_int loadedconst; // host regs that have constants loaded u_int waswritten; // MIPS regs that were used as store base before }; @@ -172,9 +172,12 @@ static struct decoded_insn u_char rt2; u_char lt1; u_char bt:1; - u_char likely:1; u_char ooo:1; u_char is_ds:1; + u_char is_jump:1; + u_char is_ujump:1; + u_char is_load:1; + u_char is_store:1; } dops[MAXBLOCK]; // used by asm: @@ -199,7 +202,8 @@ static struct decoded_insn static u_int ba[MAXBLOCK]; static uint64_t unneeded_reg[MAXBLOCK]; static uint64_t branch_unneeded_reg[MAXBLOCK]; - static signed char regmap_pre[MAXBLOCK][HOST_REGS]; // pre-instruction i? + // pre-instruction [i], excluding loop-preload regs? + static signed char regmap_pre[MAXBLOCK][HOST_REGS]; // contains 'real' consts at [i] insn, but may differ from what's actually // loaded in host reg as 'final' value is always loaded, see get_final_value() static uint32_t current_constmap[HOST_REGS]; @@ -224,11 +228,7 @@ static struct decoded_insn static void *copy; static int expirep; static u_int stop_after_jal; -#ifndef RAM_FIXED - static uintptr_t ram_offset; -#else - static const uintptr_t ram_offset=0; -#endif + static u_int f1_hack; // 0 - off, ~0 - capture address, else addr int new_dynarec_hacks; int new_dynarec_hacks_pergame; @@ -242,6 +242,7 @@ static struct decoded_insn extern int pcaddr; extern int pending_exception; extern int branch_target; + extern uintptr_t ram_offset; extern uintptr_t mini_ht[32][2]; extern u_char restore_candidate[512]; @@ -254,7 +255,7 @@ static struct decoded_insn #define CCREG 36 // Cycle count #define INVCP 37 // Pointer to invalid_code //#define MMREG 38 // Pointer to memory_map -//#define ROREG 39 // ram offset (if rdram!=0x80000000) +#define ROREG 39 // ram offset (if rdram!=0x80000000) #define TEMPREG 40 #define FTEMP 40 // FPU temporary register #define PTEMP 41 // Prefetch temporary register @@ -328,13 +329,13 @@ void call_gteStall(); void new_dyna_leave(); // Needed by assembler -static void wb_register(signed char r,signed char regmap[],uint64_t dirty); -static void wb_dirtys(signed char i_regmap[],uint64_t i_dirty); -static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr); -static void load_all_regs(signed char i_regmap[]); -static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]); +static void wb_register(signed char r, const signed char regmap[], uint64_t dirty); +static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty); +static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr); +static void load_all_regs(const signed char i_regmap[]); +static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]); static void load_regs_entry(int t); -static void load_all_consts(signed char regmap[],u_int dirty,int i); +static void load_all_consts(const signed char regmap[], u_int dirty, int i); static u_int get_host_reglist(const signed char *regmap); static int verify_dirty(const u_int *ptr); @@ -344,7 +345,8 @@ static void add_stub(enum stub_type type, void *addr, void *retaddr, static void add_stub_r(enum stub_type type, void *addr, void *retaddr, int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist); static void add_to_linker(void *addr, u_int target, int ext); -static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override); +static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs, + int addr, int *offset_reg, int *addr_reg_override); static void *get_direct_memhandler(void *table, u_int addr, enum stub_type type, uintptr_t *addr_host); static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist); @@ -463,30 +465,18 @@ static void do_clear_cache(void) #define NO_CYCLE_PENALTY_THR 12 -int cycle_multiplier; // 100 for 1.0 +int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0 int cycle_multiplier_override; int cycle_multiplier_old; +static int cycle_multiplier_active; static int CLOCK_ADJUST(int x) { - int m = cycle_multiplier_override - ? cycle_multiplier_override : cycle_multiplier; - int s=(x>>31)|1; + int m = cycle_multiplier_active; + int s = (x >> 31) | 1; return (x * m + s * 50) / 100; } -// is the op an unconditional jump? -static int is_ujump(int i) -{ - return dops[i].itype == UJUMP || dops[i].itype == RJUMP - || (source[i] >> 16) == 0x1000; // beq r0, r0, offset // b offset -} - -static int is_jump(int i) -{ - return dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP; -} - static int ds_writes_rjump_rs(int i) { return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2); @@ -699,7 +689,7 @@ void lsn(u_char hsn[], int i, int *preferred_reg) j=slen-i-1; break; } - if (is_ujump(i+j)) + if (dops[i+j].is_ujump) { // Don't go past an unconditonal jump j++; @@ -717,11 +707,12 @@ void lsn(u_char hsn[], int i, int *preferred_reg) hsn[dops[i+j].rs1]=j; hsn[dops[i+j].rs2]=j; } + if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store)) + hsn[ROREG] = j; // On some architectures stores need invc_ptr #if defined(HOST_IMM8) - if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR || (dops[i+j].opcode&0x3b)==0x39 || (dops[i+j].opcode&0x3b)==0x3a) { - hsn[INVCP]=j; - } + if (dops[i+j].is_store) + hsn[INVCP] = j; #endif if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP)) { @@ -747,7 +738,7 @@ void lsn(u_char hsn[], int i, int *preferred_reg) // TODO: preferred register based on backward branch } // Delay slot should preferably not overwrite branch conditions or cycle count - if (i > 0 && is_jump(i-1)) { + if (i > 0 && dops[i-1].is_jump) { if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1; if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1; hsn[CCREG]=1; @@ -756,7 +747,7 @@ void lsn(u_char hsn[], int i, int *preferred_reg) hsn[RHTBL]=1; } // Coprocessor load/store needs FTEMP, even if not declared - if(dops[i].itype==C1LS||dops[i].itype==C2LS) { + if(dops[i].itype==C2LS) { hsn[FTEMP]=0; } // Load L/R also uses FTEMP as a temporary register @@ -782,7 +773,7 @@ int needed_again(int r, int i) int b=-1; int rn=10; - if (i > 0 && is_ujump(i-1)) + if (i > 0 && dops[i-1].is_ujump) { if(ba[i-1]start+slen*4-4) return 0; // Don't need any registers if exiting the block @@ -793,7 +784,7 @@ int needed_again(int r, int i) j=slen-i-1; break; } - if (is_ujump(i+j)) + if (dops[i+j].is_ujump) { // Don't go past an unconditonal jump j++; @@ -830,7 +821,7 @@ int loop_reg(int i, int r, int hr) j=slen-i-1; break; } - if (is_ujump(i+j)) + if (dops[i+j].is_ujump) { // Don't go past an unconditonal jump j++; @@ -1374,9 +1365,11 @@ void clean_blocks(u_int page) static void alloc_reg(struct regstat *cur,int i,signed char reg) { int r,hr; - int preferred_reg = (reg&7); - if(reg==CCREG) preferred_reg=HOST_CCREG; - if(reg==PTEMP||reg==FTEMP) preferred_reg=12; + int preferred_reg = PREFERRED_REG_FIRST + + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1); + if (reg == CCREG) preferred_reg = HOST_CCREG; + if (reg == PTEMP || reg == FTEMP) preferred_reg = 12; + assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS); // Don't allocate unused registers if((cur->u>>reg)&1) return; @@ -1420,28 +1413,47 @@ static void alloc_reg(struct regstat *cur,int i,signed char reg) if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;} } } + // Try to allocate any available register, but prefer // registers that have not been used recently. - if(i>0) { - for(hr=0;hrregmap[hr]==-1) { - if(regs[i-1].regmap[hr]!=dops[i-1].rs1&®s[i-1].regmap[hr]!=dops[i-1].rs2&®s[i-1].regmap[hr]!=dops[i-1].rt1&®s[i-1].regmap[hr]!=dops[i-1].rt2) { + if (i > 0) { + for (hr = PREFERRED_REG_FIRST; ; ) { + if (cur->regmap[hr] < 0) { + int oldreg = regs[i-1].regmap[hr]; + if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2 + && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2)) + { cur->regmap[hr]=reg; cur->dirty&=~(1<isconst&=~(1<regmap[hr]==-1) { + for (hr = PREFERRED_REG_FIRST; ; ) { + if (cur->regmap[hr] < 0) { cur->regmap[hr]=reg; cur->dirty&=~(1<isconst&=~(1<2) hsn[CCREG]=2; - if(i>1&&hsn[CCREG]>2&&(dops[i-2].itype==RJUMP||dops[i-2].itype==UJUMP||dops[i-2].itype==CJUMP||dops[i-2].itype==SJUMP)) hsn[CCREG]=2; + if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2; for(j=10;j>=3;j--) { // Alloc preferred register if available @@ -1562,7 +1574,7 @@ static void alloc_reg_temp(struct regstat *cur,int i,signed char reg) // Don't evict the cycle count at entry points, otherwise the entry // stub will have to write it. if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2; - if(i>1&&hsn[CCREG]>2&&(dops[i-2].itype==RJUMP||dops[i-2].itype==UJUMP||dops[i-2].itype==CJUMP||dops[i-2].itype==SJUMP)) hsn[CCREG]=2; + if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2; for(j=10;j>=3;j--) { for(r=1;r<=MAXREG;r++) @@ -1604,9 +1616,8 @@ static void alloc_reg_temp(struct regstat *cur,int i,signed char reg) static void mov_alloc(struct regstat *current,int i) { if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) { - // logically this is needed but just won't work, no idea why - //alloc_cc(current,i); // for stalls - //dirty_reg(current,CCREG); + alloc_cc(current,i); // for stalls + dirty_reg(current,CCREG); } // Note: Don't need to actually alloc the source registers @@ -1766,7 +1777,10 @@ static void load_alloc(struct regstat *current,int i) clear_const(current,dops[i].rt1); //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt? if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register - if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); + if (needed_again(dops[i].rs1, i)) + alloc_reg(current, i, dops[i].rs1); + if (ram_offset) + alloc_reg(current, i, ROREG); if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) { alloc_reg(current,i,dops[i].rt1); assert(get_reg(current->regmap,dops[i].rt1)>=0); @@ -1813,9 +1827,11 @@ void store_alloc(struct regstat *current,int i) if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD assert(0); } + if (ram_offset) + alloc_reg(current, i, ROREG); #if defined(HOST_IMM8) // On CPUs without 32-bit immediates we need a pointer to invalid_code - else alloc_reg(current,i,INVCP); + alloc_reg(current, i, INVCP); #endif if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR alloc_reg(current,i,FTEMP); @@ -1827,21 +1843,8 @@ void store_alloc(struct regstat *current,int i) void c1ls_alloc(struct regstat *current,int i) { - //clear_const(current,dops[i].rs1); // FIXME clear_const(current,dops[i].rt1); - if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); alloc_reg(current,i,CSREG); // Status - alloc_reg(current,i,FTEMP); - if(dops[i].opcode==0x35||dops[i].opcode==0x3d) { // 64-bit LDC1/SDC1 - assert(0); - } - #if defined(HOST_IMM8) - // On CPUs without 32-bit immediates we need a pointer to invalid_code - else if((dops[i].opcode&0x3b)==0x39) // SWC1/SDC1 - alloc_reg(current,i,INVCP); - #endif - // We need a temporary register for address generation - alloc_reg_temp(current,i,-1); } void c2ls_alloc(struct regstat *current,int i) @@ -1849,9 +1852,11 @@ void c2ls_alloc(struct regstat *current,int i) clear_const(current,dops[i].rt1); if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); alloc_reg(current,i,FTEMP); + if (ram_offset) + alloc_reg(current, i, ROREG); #if defined(HOST_IMM8) // On CPUs without 32-bit immediates we need a pointer to invalid_code - if((dops[i].opcode&0x3b)==0x3a) // SWC2/SDC2 + if (dops[i].opcode == 0x3a) // SWC2 alloc_reg(current,i,INVCP); #endif // We need a temporary register for address generation @@ -2098,7 +2103,7 @@ static void add_stub_r(enum stub_type type, void *addr, void *retaddr, } // Write out a single register -static void wb_register(signed char r,signed char regmap[],uint64_t dirty) +static void wb_register(signed char r, const signed char regmap[], uint64_t dirty) { int hr; for(hr=0;hr=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU if(dops[i].rt1) { @@ -2293,7 +2298,7 @@ static void alu_assemble(int i,struct regstat *i_regs) } } -void imm16_assemble(int i,struct regstat *i_regs) +static void imm16_assemble(int i, const struct regstat *i_regs) { if (dops[i].opcode==0x0f) { // LUI if(dops[i].rt1) { @@ -2448,7 +2453,7 @@ void imm16_assemble(int i,struct regstat *i_regs) } } -void shiftimm_assemble(int i,struct regstat *i_regs) +static void shiftimm_assemble(int i, const struct regstat *i_regs) { if(dops[i].opcode2<=0x3) // SLL/SRL/SRA { @@ -2506,7 +2511,7 @@ void shiftimm_assemble(int i,struct regstat *i_regs) } #ifndef shift_assemble -static void shift_assemble(int i,struct regstat *i_regs) +static void shift_assemble(int i, const struct regstat *i_regs) { signed char s,t,shift; if (dops[i].rt1 == 0) @@ -2572,11 +2577,25 @@ static int get_ptr_mem_type(u_int a) return MTYPE_8000; } -static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override) +static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free) +{ + int r = get_reg(i_regs->regmap, ROREG); + if (r < 0 && host_tempreg_free) { + host_tempreg_acquire(); + emit_loadreg(ROREG, r = HOST_TEMPREG); + } + if (r < 0) + abort(); + return r; +} + +static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs, + int addr, int *offset_reg, int *addr_reg_override) { void *jaddr = NULL; - int type=0; - int mr=dops[i].rs1; + int type = 0; + int mr = dops[i].rs1; + *offset_reg = -1; if(((smrv_strong|smrv_weak)>>mr)&1) { type=get_ptr_mem_type(smrv[mr]); //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type); @@ -2620,22 +2639,19 @@ static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override) } } - if(type==0) + if (type == 0) // need ram check { emit_cmpimm(addr,RAM_SIZE); - jaddr=out; + jaddr = out; #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK // Hint to branch predictor that the branch is unlikely to be taken - if(dops[i].rs1>=28) + if (dops[i].rs1 >= 28) emit_jno_unlikely(0); else #endif emit_jno(0); - if(ram_offset!=0) { - host_tempreg_acquire(); - emit_addimm(addr,ram_offset,HOST_TEMPREG); - addr=*addr_reg_override=HOST_TEMPREG; - } + if (ram_offset != 0) + *offset_reg = get_ro_reg(i_regs, 0); } return jaddr; @@ -2645,9 +2661,10 @@ static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override) static void *get_direct_memhandler(void *table, u_int addr, enum stub_type type, uintptr_t *addr_host) { + uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1); uintptr_t l1, l2 = 0; l1 = ((uintptr_t *)table)[addr>>12]; - if ((l1 & (1ul << (sizeof(l1)*8-1))) == 0) { + if (!(l1 & msb)) { uintptr_t v = l1 << 1; *addr_host = v + addr; return NULL; @@ -2657,10 +2674,10 @@ static void *get_direct_memhandler(void *table, u_int addr, if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB) l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)]; else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB) - l2=((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2]; + l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2]; else - l2=((uintptr_t *)l1)[(addr&0xfff)/4]; - if ((l2 & (1<<31)) == 0) { + l2 = ((uintptr_t *)l1)[(addr&0xfff)/4]; + if (!(l2 & msb)) { uintptr_t v = l2 << 1; *addr_host = v + (addr&0xfff); return NULL; @@ -2697,13 +2714,56 @@ static int reglist_find_free(u_int reglist) return __builtin_ctz(free_regs); } -static void load_assemble(int i, const struct regstat *i_regs) +static void do_load_word(int a, int rt, int offset_reg) +{ + if (offset_reg >= 0) + emit_ldr_dualindexed(offset_reg, a, rt); + else + emit_readword_indexed(0, a, rt); +} + +static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a) +{ + if (offset_reg < 0) { + emit_writeword_indexed(rt, ofs, a); + return; + } + if (ofs != 0) + emit_addimm(a, ofs, a); + emit_str_dualindexed(offset_reg, a, rt); + if (ofs != 0 && preseve_a) + emit_addimm(a, -ofs, a); +} + +static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a) +{ + if (offset_reg < 0) { + emit_writehword_indexed(rt, ofs, a); + return; + } + if (ofs != 0) + emit_addimm(a, ofs, a); + emit_strh_dualindexed(offset_reg, a, rt); + if (ofs != 0 && preseve_a) + emit_addimm(a, -ofs, a); +} + +static void do_store_byte(int a, int rt, int offset_reg) +{ + if (offset_reg >= 0) + emit_strb_dualindexed(offset_reg, a, rt); + else + emit_writebyte_indexed(rt, 0, a); +} + +static void load_assemble(int i, const struct regstat *i_regs, int ccadj_) { int s,tl,addr; int offset; void *jaddr=0; int memtarget=0,c=0; - int fastio_reg_override=-1; + int offset_reg = -1; + int fastio_reg_override = -1; u_int reglist=get_host_reglist(i_regs->regmap); tl=get_reg(i_regs->regmap,dops[i].rt1); s=get_reg(i_regs->regmap,dops[i].rs1); @@ -2740,107 +2800,122 @@ static void load_assemble(int i, const struct regstat *i_regs) if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE) #endif { - jaddr=emit_fastpath_cmp_jump(i,addr,&fastio_reg_override); + jaddr = emit_fastpath_cmp_jump(i, i_regs, addr, + &offset_reg, &fastio_reg_override); } } - else if(ram_offset&&memtarget) { - host_tempreg_acquire(); - emit_addimm(addr,ram_offset,HOST_TEMPREG); - fastio_reg_override=HOST_TEMPREG; + else if (ram_offset && memtarget) { + offset_reg = get_ro_reg(i_regs, 0); } int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg - if (dops[i].opcode==0x20) { // LB + switch (dops[i].opcode) { + case 0x20: // LB if(!c||memtarget) { if(!dummy) { - { - int x=0,a=tl; - if(!c) a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; + int a = tl; + if (!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; - emit_movsbl_indexed(x,a,tl); - } + if (offset_reg >= 0) + emit_ldrsb_dualindexed(offset_reg, a, tl); + else + emit_movsbl_indexed(0, a, tl); } if(jaddr) - add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); + add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); } else - inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist); - } - if (dops[i].opcode==0x21) { // LH + inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); + break; + case 0x21: // LH if(!c||memtarget) { if(!dummy) { - int x=0,a=tl; - if(!c) a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_movswl_indexed(x,a,tl); + int a = tl; + if (!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + if (offset_reg >= 0) + emit_ldrsh_dualindexed(offset_reg, a, tl); + else + emit_movswl_indexed(0, a, tl); } if(jaddr) - add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); + add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); } else - inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist); - } - if (dops[i].opcode==0x23) { // LW + inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); + break; + case 0x23: // LW if(!c||memtarget) { if(!dummy) { - int a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_readword_indexed(0,a,tl); + int a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_load_word(a, tl, offset_reg); } if(jaddr) - add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); + add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); } else - inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist); - } - if (dops[i].opcode==0x24) { // LBU + inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); + break; + case 0x24: // LBU if(!c||memtarget) { if(!dummy) { - int x=0,a=tl; - if(!c) a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; + int a = tl; + if (!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; - emit_movzbl_indexed(x,a,tl); + if (offset_reg >= 0) + emit_ldrb_dualindexed(offset_reg, a, tl); + else + emit_movzbl_indexed(0, a, tl); } if(jaddr) - add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); + add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); } else - inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist); - } - if (dops[i].opcode==0x25) { // LHU + inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); + break; + case 0x25: // LHU if(!c||memtarget) { if(!dummy) { - int x=0,a=tl; - if(!c) a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_movzwl_indexed(x,a,tl); + int a = tl; + if(!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + if (offset_reg >= 0) + emit_ldrh_dualindexed(offset_reg, a, tl); + else + emit_movzwl_indexed(0, a, tl); } if(jaddr) - add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); + add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); } else - inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist); - } - if (dops[i].opcode==0x27) { // LWU - assert(0); - } - if (dops[i].opcode==0x37) { // LD + inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); + break; + case 0x27: // LWU + case 0x37: // LD + default: assert(0); } } - if (fastio_reg_override == HOST_TEMPREG) + if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) host_tempreg_release(); } #ifndef loadlr_assemble -static void loadlr_assemble(int i, const struct regstat *i_regs) +static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_) { int s,tl,temp,temp2,addr; int offset; void *jaddr=0; int memtarget=0,c=0; - int fastio_reg_override=-1; + int offset_reg = -1; + int fastio_reg_override = -1; u_int reglist=get_host_reglist(i_regs->regmap); tl=get_reg(i_regs->regmap,dops[i].rt1); s=get_reg(i_regs->regmap,dops[i].rs1); @@ -2865,13 +2940,12 @@ static void loadlr_assemble(int i, const struct regstat *i_regs) }else{ emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR } - jaddr=emit_fastpath_cmp_jump(i,temp2,&fastio_reg_override); + jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2, + &offset_reg, &fastio_reg_override); } else { - if(ram_offset&&memtarget) { - host_tempreg_acquire(); - emit_addimm(temp2,ram_offset,HOST_TEMPREG); - fastio_reg_override=HOST_TEMPREG; + if (ram_offset && memtarget) { + offset_reg = get_ro_reg(i_regs, 0); } if (dops[i].opcode==0x22||dops[i].opcode==0x26) { emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR @@ -2881,14 +2955,16 @@ static void loadlr_assemble(int i, const struct regstat *i_regs) } if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR if(!c||memtarget) { - int a=temp2; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_readword_indexed(0,a,temp2); - if(fastio_reg_override==HOST_TEMPREG) host_tempreg_release(); - if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj[i],reglist); + int a = temp2; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_load_word(a, temp2, offset_reg); + if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) + host_tempreg_release(); + if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist); } else - inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist); + inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist); if(dops[i].rt1) { assert(tl>=0); emit_andimm(temp,24,temp); @@ -2914,16 +2990,17 @@ static void loadlr_assemble(int i, const struct regstat *i_regs) } #endif -void store_assemble(int i, const struct regstat *i_regs) +static void store_assemble(int i, const struct regstat *i_regs, int ccadj_) { int s,tl; int addr,temp; int offset; void *jaddr=0; - enum stub_type type; + enum stub_type type=0; int memtarget=0,c=0; int agr=AGEN1+(i&1); - int fastio_reg_override=-1; + int offset_reg = -1; + int fastio_reg_override = -1; u_int reglist=get_host_reglist(i_regs->regmap); tl=get_reg(i_regs->regmap,dops[i].rs2); s=get_reg(i_regs->regmap,dops[i].rs1); @@ -2941,51 +3018,54 @@ void store_assemble(int i, const struct regstat *i_regs) if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<=0) a=fastio_reg_override; - emit_writebyte_indexed(tl,x,a); - } - type=STOREB_STUB; - } - if (dops[i].opcode==0x29) { // SH + int a = temp; + if (!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_store_byte(a, tl, offset_reg); + } + type = STOREB_STUB; + break; + case 0x29: // SH if(!c||memtarget) { - int x=0,a=temp; - if(!c) a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_writehword_indexed(tl,x,a); - } - type=STOREH_STUB; - } - if (dops[i].opcode==0x2B) { // SW + int a = temp; + if (!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_store_hword(a, 0, tl, offset_reg, 1); + } + type = STOREH_STUB; + break; + case 0x2B: // SW if(!c||memtarget) { - int a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_writeword_indexed(tl,0,a); - } - type=STOREW_STUB; - } - if (dops[i].opcode==0x3F) { // SD + int a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_store_word(a, 0, tl, offset_reg, 1); + } + type = STOREW_STUB; + break; + case 0x3F: // SD + default: assert(0); - type=STORED_STUB; } - if(fastio_reg_override==HOST_TEMPREG) + if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) host_tempreg_release(); if(jaddr) { // PCSX store handlers don't check invcode again reglist|=1<waswritten&(1<regmap,dops[i].rs2,ccadj[i],reglist); + inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist); } // basic current block modification detection.. // not looking back as that should be in mips cache already @@ -3035,16 +3115,17 @@ void store_assemble(int i, const struct regstat *i_regs) } } -static void storelr_assemble(int i, const struct regstat *i_regs) +static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_) { int s,tl; int temp; int offset; void *jaddr=0; - void *case1, *case2, *case3; + void *case1, *case23, *case3; void *done0, *done1, *done2; int memtarget=0,c=0; int agr=AGEN1+(i&1); + int offset_reg = -1; u_int reglist=get_host_reglist(i_regs->regmap); tl=get_reg(i_regs->regmap,dops[i].rs2); s=get_reg(i_regs->regmap,dops[i].rs1); @@ -3072,86 +3153,85 @@ static void storelr_assemble(int i, const struct regstat *i_regs) emit_jmp(0); } } - if(ram_offset) - emit_addimm_no_flags(ram_offset,temp); + if (ram_offset) + offset_reg = get_ro_reg(i_regs, 0); if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR assert(0); } - emit_xorimm(temp,3,temp); emit_testimm(temp,2); - case2=out; + case23=out; emit_jne(0); emit_testimm(temp,1); case1=out; emit_jne(0); // 0 - if (dops[i].opcode==0x2A) { // SWL - emit_writeword_indexed(tl,0,temp); + if (dops[i].opcode == 0x2A) { // SWL + // Write msb into least significant byte + if (dops[i].rs2) emit_rorimm(tl, 24, tl); + do_store_byte(temp, tl, offset_reg); + if (dops[i].rs2) emit_rorimm(tl, 8, tl); } - else if (dops[i].opcode==0x2E) { // SWR - emit_writebyte_indexed(tl,3,temp); + else if (dops[i].opcode == 0x2E) { // SWR + // Write entire word + do_store_word(temp, 0, tl, offset_reg, 1); } - else - assert(0); - done0=out; + done0 = out; emit_jmp(0); // 1 set_jump_target(case1, out); - if (dops[i].opcode==0x2A) { // SWL - // Write 3 msb into three least significant bytes - if(dops[i].rs2) emit_rorimm(tl,8,tl); - emit_writehword_indexed(tl,-1,temp); - if(dops[i].rs2) emit_rorimm(tl,16,tl); - emit_writebyte_indexed(tl,1,temp); - if(dops[i].rs2) emit_rorimm(tl,8,tl); + if (dops[i].opcode == 0x2A) { // SWL + // Write two msb into two least significant bytes + if (dops[i].rs2) emit_rorimm(tl, 16, tl); + do_store_hword(temp, -1, tl, offset_reg, 0); + if (dops[i].rs2) emit_rorimm(tl, 16, tl); } - else if (dops[i].opcode==0x2E) { // SWR - // Write two lsb into two most significant bytes - emit_writehword_indexed(tl,1,temp); + else if (dops[i].opcode == 0x2E) { // SWR + // Write 3 lsb into three most significant bytes + do_store_byte(temp, tl, offset_reg); + if (dops[i].rs2) emit_rorimm(tl, 8, tl); + do_store_hword(temp, 1, tl, offset_reg, 0); + if (dops[i].rs2) emit_rorimm(tl, 24, tl); } done1=out; emit_jmp(0); - // 2 - set_jump_target(case2, out); + // 2,3 + set_jump_target(case23, out); emit_testimm(temp,1); - case3=out; + case3 = out; emit_jne(0); + // 2 if (dops[i].opcode==0x2A) { // SWL - // Write two msb into two least significant bytes - if(dops[i].rs2) emit_rorimm(tl,16,tl); - emit_writehword_indexed(tl,-2,temp); - if(dops[i].rs2) emit_rorimm(tl,16,tl); + // Write 3 msb into three least significant bytes + if (dops[i].rs2) emit_rorimm(tl, 8, tl); + do_store_hword(temp, -2, tl, offset_reg, 1); + if (dops[i].rs2) emit_rorimm(tl, 16, tl); + do_store_byte(temp, tl, offset_reg); + if (dops[i].rs2) emit_rorimm(tl, 8, tl); } - else if (dops[i].opcode==0x2E) { // SWR - // Write 3 lsb into three most significant bytes - emit_writebyte_indexed(tl,-1,temp); - if(dops[i].rs2) emit_rorimm(tl,8,tl); - emit_writehword_indexed(tl,0,temp); - if(dops[i].rs2) emit_rorimm(tl,24,tl); + else if (dops[i].opcode == 0x2E) { // SWR + // Write two lsb into two most significant bytes + do_store_hword(temp, 0, tl, offset_reg, 1); } - done2=out; + done2 = out; emit_jmp(0); // 3 set_jump_target(case3, out); - if (dops[i].opcode==0x2A) { // SWL - // Write msb into least significant byte - if(dops[i].rs2) emit_rorimm(tl,24,tl); - emit_writebyte_indexed(tl,-3,temp); - if(dops[i].rs2) emit_rorimm(tl,8,tl); + if (dops[i].opcode == 0x2A) { // SWL + do_store_word(temp, -3, tl, offset_reg, 0); } - else if (dops[i].opcode==0x2E) { // SWR - // Write entire word - emit_writeword_indexed(tl,-3,temp); + else if (dops[i].opcode == 0x2E) { // SWR + do_store_byte(temp, tl, offset_reg); } set_jump_target(done0, out); set_jump_target(done1, out); set_jump_target(done2, out); + if (offset_reg == HOST_TEMPREG) + host_tempreg_release(); if(!c||!memtarget) - add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj[i],reglist); + add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist); if(!(i_regs->waswritten&(1<regmap,INVCP); assert(ir>=0); @@ -3169,7 +3249,7 @@ static void storelr_assemble(int i, const struct regstat *i_regs) } } -static void cop0_assemble(int i,struct regstat *i_regs) +static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_) { if(dops[i].opcode2==0) // MFC0 { @@ -3190,7 +3270,7 @@ static void cop0_assemble(int i,struct regstat *i_regs) emit_readword(&last_count,HOST_TEMPREG); emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG); - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); + emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG); emit_writeword(HOST_CCREG,&Count); } // What a mess. The status register (12) can enable interrupts, @@ -3225,7 +3305,7 @@ static void cop0_assemble(int i,struct regstat *i_regs) if(copr==9||copr==11||copr==12||copr==13) { emit_readword(&Count,HOST_CCREG); emit_readword(&next_interupt,HOST_TEMPREG); - emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG); + emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG); emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG); emit_writeword(HOST_TEMPREG,&last_count); emit_storereg(CCREG,HOST_CCREG); @@ -3258,7 +3338,7 @@ static void cop0_assemble(int i,struct regstat *i_regs) } } -static void cop1_unusable(int i,struct regstat *i_regs) +static void cop1_unusable(int i, const struct regstat *i_regs) { // XXX: should just just do the exception instead //if(!cop1_usable) @@ -3269,12 +3349,12 @@ static void cop1_unusable(int i,struct regstat *i_regs) } } -static void cop1_assemble(int i,struct regstat *i_regs) +static void cop1_assemble(int i, const struct regstat *i_regs) { cop1_unusable(i, i_regs); } -static void c1ls_assemble(int i,struct regstat *i_regs) +static void c1ls_assemble(int i, const struct regstat *i_regs) { cop1_unusable(i, i_regs); } @@ -3297,7 +3377,7 @@ static void do_cop1stub(int n) wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty); if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); emit_movimm(start+(i-ds)*4,EAX); // Get PC - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle... + emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle... emit_far_jump(ds?fp_exception_ds:fp_exception); } @@ -3333,7 +3413,7 @@ static void emit_log_gte_stall(int i, int stall, u_int reglist) emit_movimm(stall, 0); else emit_mov(HOST_TEMPREG, 0); - emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]), 1); + emit_addimm(HOST_CCREG, ccadj[i], 1); emit_far_call(log_gte_stall); restore_regs(reglist); } @@ -3356,10 +3436,12 @@ static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u //if (dops[j].is_ds) break; if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt) break; + if (j > 0 && ccadj[j - 1] > ccadj[j]) + break; } j = max(j, 0); } - cycles_passed = CLOCK_ADJUST(ccadj[i] - ccadj[j]); + cycles_passed = ccadj[i] - ccadj[j]; if (other_gte_op_cycles >= 0) stall = other_gte_op_cycles - cycles_passed; else if (cycles_passed >= 44) @@ -3370,13 +3452,13 @@ static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u #if 0 // too slow save_regs(reglist); emit_movimm(gte_cycletab[op], 0); - emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]), 1); + emit_addimm(HOST_CCREG, ccadj[i], 1); emit_far_call(call_gteStall); restore_regs(reglist); #else host_tempreg_acquire(); emit_readword(&psxRegs.gteBusyCycle, rtmp); - emit_addimm(rtmp, -CLOCK_ADJUST(ccadj[i]), rtmp); + emit_addimm(rtmp, -ccadj[i], rtmp); emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG); emit_cmpimm(HOST_TEMPREG, 44); emit_cmovb_reg(rtmp, HOST_CCREG); @@ -3396,7 +3478,7 @@ static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u for (j = i + 1; j < slen; j++) { if (cop2_is_stalling_op(j, &other_gte_op_cycles)) break; - if (is_jump(j)) { + if (dops[j].is_jump) { // check ds if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles)) j++; @@ -3406,7 +3488,7 @@ static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u if (other_gte_op_cycles >= 0) // will handle stall when assembling that op return; - cycles_passed = CLOCK_ADJUST(ccadj[min(j, slen -1)] - ccadj[i]); + cycles_passed = ccadj[min(j, slen -1)] - ccadj[i]; if (cycles_passed >= 44) return; assem_debug("; save gteBusyCycle\n"); @@ -3414,11 +3496,11 @@ static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u #if 0 emit_readword(&last_count, HOST_TEMPREG); emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG); - emit_addimm(HOST_TEMPREG, CLOCK_ADJUST(ccadj[i]), HOST_TEMPREG); + emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG); emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG); emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle); #else - emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]) + gte_cycletab[op], HOST_TEMPREG); + emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG); emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle); #endif host_tempreg_release(); @@ -3440,7 +3522,7 @@ static int check_multdiv(int i, int *cycles) return 1; } -static void multdiv_prepare_stall(int i, const struct regstat *i_regs) +static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_) { int j, found = 0, c = 0; if (HACK_ENABLED(NDHACK_NO_STALLS)) @@ -3454,7 +3536,7 @@ static void multdiv_prepare_stall(int i, const struct regstat *i_regs) break; if ((found = is_mflohi(j))) break; - if (is_jump(j)) { + if (dops[j].is_jump) { // check ds if (j + 1 < slen && (found = is_mflohi(j + 1))) j++; @@ -3468,7 +3550,7 @@ static void multdiv_prepare_stall(int i, const struct regstat *i_regs) assert(c > 0); assem_debug("; muldiv prepare stall %d\n", c); host_tempreg_acquire(); - emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]) + c, HOST_TEMPREG); + emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG); emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle); host_tempreg_release(); } @@ -3490,16 +3572,18 @@ static void multdiv_do_stall(int i, const struct regstat *i_regs) if (!dops[i].bt) { for (j = i - 1; j >= 0; j--) { if (dops[j].is_ds) break; - if (check_multdiv(j, &known_cycles) || dops[j].bt) + if (check_multdiv(j, &known_cycles)) break; if (is_mflohi(j)) // already handled by this op return; + if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j])) + break; } j = max(j, 0); } if (known_cycles > 0) { - known_cycles -= CLOCK_ADJUST(ccadj[i] - ccadj[j]); + known_cycles -= ccadj[i] - ccadj[j]; assem_debug("; muldiv stall resolved %d\n", known_cycles); if (known_cycles > 0) emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG); @@ -3508,7 +3592,7 @@ static void multdiv_do_stall(int i, const struct regstat *i_regs) assem_debug("; muldiv stall unresolved\n"); host_tempreg_acquire(); emit_readword(&psxRegs.muldivBusyCycle, rtmp); - emit_addimm(rtmp, -CLOCK_ADJUST(ccadj[i]), rtmp); + emit_addimm(rtmp, -ccadj[i], rtmp); emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG); emit_cmpimm(HOST_TEMPREG, 37); emit_cmovb_reg(rtmp, HOST_CCREG); @@ -3599,7 +3683,7 @@ static void cop2_put_dreg(u_int copr,signed char sl,signed char temp) } } -static void c2ls_assemble(int i, const struct regstat *i_regs) +static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_) { int s,tl; int ar; @@ -3608,7 +3692,8 @@ static void c2ls_assemble(int i, const struct regstat *i_regs) void *jaddr2=NULL; enum stub_type type; int agr=AGEN1+(i&1); - int fastio_reg_override=-1; + int offset_reg = -1; + int fastio_reg_override = -1; u_int reglist=get_host_reglist(i_regs->regmap); u_int copr=(source[i]>>16)&0x1f; s=get_reg(i_regs->regmap,dops[i].rs1); @@ -3648,31 +3733,38 @@ static void c2ls_assemble(int i, const struct regstat *i_regs) } else { if(!c) { - jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override); - } - else if(ram_offset&&memtarget) { - host_tempreg_acquire(); - emit_addimm(ar,ram_offset,HOST_TEMPREG); - fastio_reg_override=HOST_TEMPREG; - } - if (dops[i].opcode==0x32) { // LWC2 - int a=ar; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_readword_indexed(0,a,tl); + jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar, + &offset_reg, &fastio_reg_override); + } + else if (ram_offset && memtarget) { + offset_reg = get_ro_reg(i_regs, 0); + } + switch (dops[i].opcode) { + case 0x32: { // LWC2 + int a = ar; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_load_word(a, tl, offset_reg); + break; } - if (dops[i].opcode==0x3a) { // SWC2 + case 0x3a: { // SWC2 #ifdef DESTRUCTIVE_SHIFT if(!offset&&!c&&s>=0) emit_mov(s,ar); #endif - int a=ar; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_writeword_indexed(tl,0,a); + int a = ar; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_store_word(a, 0, tl, offset_reg, 1); + break; + } + default: + assert(0); } } - if(fastio_reg_override==HOST_TEMPREG) + if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) host_tempreg_release(); if(jaddr2) - add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj[i],reglist); + add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist); if(dops[i].opcode==0x3a) // SWC2 if(!(i_regs->waswritten&(1<regmap,CCREG); assert(ccreg==HOST_CCREG); @@ -3822,33 +3914,33 @@ static void call_c_cpu_handler(int i, const struct regstat *i_regs, u_int pc, vo emit_movimm(pc,3); // Get PC emit_readword(&last_count,2); emit_writeword(3,&psxRegs.pc); - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX + emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG); emit_add(2,HOST_CCREG,2); emit_writeword(2,&psxRegs.cycle); emit_far_call(func); emit_far_jump(jump_to_new_pc); } -static void syscall_assemble(int i,struct regstat *i_regs) +static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_) { emit_movimm(0x20,0); // cause code emit_movimm(0,1); // not in delay slot - call_c_cpu_handler(i,i_regs,start+i*4,psxException); + call_c_cpu_handler(i, i_regs, ccadj_, start+i*4, psxException); } -static void hlecall_assemble(int i,struct regstat *i_regs) +static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_) { void *hlefunc = psxNULL; uint32_t hleCode = source[i] & 0x03ffffff; if (hleCode < ARRAY_SIZE(psxHLEt)) hlefunc = psxHLEt[hleCode]; - call_c_cpu_handler(i,i_regs,start+i*4+4,hlefunc); + call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc); } -static void intcall_assemble(int i,struct regstat *i_regs) +static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_) { - call_c_cpu_handler(i,i_regs,start+i*4,execI); + call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI); } static void speculate_mov(int rs,int rt) @@ -3943,45 +4035,109 @@ static void speculate_register_values(int i) #endif } -static void ds_assemble(int i,struct regstat *i_regs) +static void ujump_assemble(int i, const struct regstat *i_regs); +static void rjump_assemble(int i, const struct regstat *i_regs); +static void cjump_assemble(int i, const struct regstat *i_regs); +static void sjump_assemble(int i, const struct regstat *i_regs); +static void pagespan_assemble(int i, const struct regstat *i_regs); + +static int assemble(int i, const struct regstat *i_regs, int ccadj_) { - speculate_register_values(i); - is_delayslot=1; - switch(dops[i].itype) { + int ds = 0; + switch (dops[i].itype) { case ALU: - alu_assemble(i,i_regs);break; + alu_assemble(i, i_regs); + break; case IMM16: - imm16_assemble(i,i_regs);break; + imm16_assemble(i, i_regs); + break; case SHIFT: - shift_assemble(i,i_regs);break; + shift_assemble(i, i_regs); + break; case SHIFTIMM: - shiftimm_assemble(i,i_regs);break; + shiftimm_assemble(i, i_regs); + break; case LOAD: - load_assemble(i,i_regs);break; + load_assemble(i, i_regs, ccadj_); + break; case LOADLR: - loadlr_assemble(i,i_regs);break; + loadlr_assemble(i, i_regs, ccadj_); + break; case STORE: - store_assemble(i,i_regs);break; + store_assemble(i, i_regs, ccadj_); + break; case STORELR: - storelr_assemble(i,i_regs);break; + storelr_assemble(i, i_regs, ccadj_); + break; case COP0: - cop0_assemble(i,i_regs);break; + cop0_assemble(i, i_regs, ccadj_); + break; case COP1: - cop1_assemble(i,i_regs);break; + cop1_assemble(i, i_regs); + break; case C1LS: - c1ls_assemble(i,i_regs);break; + c1ls_assemble(i, i_regs); + break; case COP2: - cop2_assemble(i,i_regs);break; + cop2_assemble(i, i_regs); + break; case C2LS: - c2ls_assemble(i,i_regs);break; + c2ls_assemble(i, i_regs, ccadj_); + break; case C2OP: - c2op_assemble(i,i_regs);break; + c2op_assemble(i, i_regs); + break; case MULTDIV: - multdiv_assemble(i,i_regs); - multdiv_prepare_stall(i,i_regs); + multdiv_assemble(i, i_regs); + multdiv_prepare_stall(i, i_regs, ccadj_); break; case MOV: - mov_assemble(i,i_regs);break; + mov_assemble(i, i_regs); + break; + case SYSCALL: + syscall_assemble(i, i_regs, ccadj_); + break; + case HLECALL: + hlecall_assemble(i, i_regs, ccadj_); + break; + case INTCALL: + intcall_assemble(i, i_regs, ccadj_); + break; + case UJUMP: + ujump_assemble(i, i_regs); + ds = 1; + break; + case RJUMP: + rjump_assemble(i, i_regs); + ds = 1; + break; + case CJUMP: + cjump_assemble(i, i_regs); + ds = 1; + break; + case SJUMP: + sjump_assemble(i, i_regs); + ds = 1; + break; + case SPAN: + pagespan_assemble(i, i_regs); + break; + case NOP: + case OTHER: + case NI: + // not handled, just skip + break; + default: + assert(0); + } + return ds; +} + +static void ds_assemble(int i, const struct regstat *i_regs) +{ + speculate_register_values(i); + is_delayslot = 1; + switch (dops[i].itype) { case SYSCALL: case HLECALL: case INTCALL: @@ -3991,8 +4147,11 @@ static void ds_assemble(int i,struct regstat *i_regs) case CJUMP: case SJUMP: SysPrintf("Jump in the delay slot. This is probably a bug.\n"); + break; + default: + assemble(i, i_regs, ccadj[i]); } - is_delayslot=0; + is_delayslot = 0; } // Is the branch target a valid internal jump? @@ -4096,9 +4255,9 @@ static void loop_preload(signed char pre[],signed char entry[]) // Generate address for load/store instruction // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads -void address_generation(int i,struct regstat *i_regs,signed char entry[]) +void address_generation(int i, const struct regstat *i_regs, signed char entry[]) { - if(dops[i].itype==LOAD||dops[i].itype==LOADLR||dops[i].itype==STORE||dops[i].itype==STORELR||dops[i].itype==C1LS||dops[i].itype==C2LS) { + if (dops[i].is_load || dops[i].is_store) { int ra=-1; int agr=AGEN1+(i&1); if(dops[i].itype==LOAD) { @@ -4113,7 +4272,7 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[]) ra=get_reg(i_regs->regmap,agr); if(ra<0) ra=get_reg(i_regs->regmap,-1); } - if(dops[i].itype==C1LS||dops[i].itype==C2LS) { + if(dops[i].itype==C2LS) { if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2 ra=get_reg(i_regs->regmap,FTEMP); else { // SWC1/SDC1/SWC2/SDC2 @@ -4167,7 +4326,7 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[]) } } // Preload constants for next instruction - if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS||dops[i+1].itype==C2LS) { + if (dops[i+1].is_load || dops[i+1].is_store) { int agr,ra; // Actual address agr=AGEN1+((i+1)&1); @@ -4210,12 +4369,12 @@ static int get_final_value(int hr, int i, int *value) i++; } if(i>hr)&1)) { @@ -4295,7 +4454,7 @@ static void load_consts(signed char pre[],signed char regmap[],int i) } } -void load_all_consts(signed char regmap[], u_int dirty, int i) +static void load_all_consts(const signed char regmap[], u_int dirty, int i) { int hr; // Load 32-bit regs @@ -4316,7 +4475,7 @@ void load_all_consts(signed char regmap[], u_int dirty, int i) } // Write out all dirty registers (except cycle count) -static void wb_dirtys(signed char i_regmap[],uint64_t i_dirty) +static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty) { int hr; for(hr=0;hr>2; @@ -4356,7 +4515,7 @@ void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr) } // Load all registers (except cycle count) -void load_all_regs(signed char i_regmap[]) +static void load_all_regs(const signed char i_regmap[]) { int hr; for(hr=0;hr0&&(dops[t-1].itype==RJUMP||dops[t-1].itype==UJUMP||dops[t-1].itype==CJUMP||dops[t-1].itype==SJUMP)) return 0; + //if(t>0&&(dops[t-1].is_jump) return 0; // Delay slots require additional processing, so do not match if(dops[t].is_ds) return 0; } @@ -4553,7 +4712,7 @@ static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr) } #ifdef DRC_DBG -static void drc_dbg_emit_do_cmp(int i) +static void drc_dbg_emit_do_cmp(int i, int ccadj_) { extern void do_insn_cmp(); //extern int cycle; @@ -4564,7 +4723,7 @@ static void drc_dbg_emit_do_cmp(int i) // write out changed consts to match the interpreter if (i > 0 && !dops[i].bt) { for (hr = 0; hr < HOST_REGS; hr++) { - int reg = regs[i-1].regmap[hr]; + int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr]; if (hr == EXCLUDE_REG || reg < 0) continue; if (!((regs[i-1].isconst >> hr) & 1)) @@ -4577,6 +4736,11 @@ static void drc_dbg_emit_do_cmp(int i) } emit_movimm(start+i*4,0); emit_writeword(0,&pcaddr); + int cc = get_reg(regs[i].regmap_entry, CCREG); + if (cc < 0) + emit_loadreg(CCREG, cc = 0); + emit_addimm(cc, ccadj_, 0); + emit_writeword(0, &psxRegs.cycle); emit_far_call(do_insn_cmp); //emit_readword(&cycle,0); //emit_addimm(0,2,0); @@ -4586,60 +4750,29 @@ static void drc_dbg_emit_do_cmp(int i) assem_debug("\\\\do_insn_cmp\n"); } #else -#define drc_dbg_emit_do_cmp(x) +#define drc_dbg_emit_do_cmp(x,y) #endif // Used when a branch jumps into the delay slot of another branch static void ds_assemble_entry(int i) { - int t=(ba[i]-start)>>2; + int t = (ba[i] - start) >> 2; + int ccadj_ = -CLOCK_ADJUST(1); if (!instr_addr[t]) instr_addr[t] = out; assem_debug("Assemble delay slot at %x\n",ba[i]); assem_debug("<->\n"); - drc_dbg_emit_do_cmp(t); + drc_dbg_emit_do_cmp(t, ccadj_); if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG) wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty); load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2); address_generation(t,®s[t],regs[t].regmap_entry); - if(dops[t].itype==STORE||dops[t].itype==STORELR||(dops[t].opcode&0x3b)==0x39||(dops[t].opcode&0x3b)==0x3a) + if (ram_offset && (dops[t].is_load || dops[t].is_store)) + load_regs(regs[t].regmap_entry,regs[t].regmap,ROREG,ROREG); + if (dops[t].is_store) load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP); is_delayslot=0; - switch(dops[t].itype) { - case ALU: - alu_assemble(t,®s[t]);break; - case IMM16: - imm16_assemble(t,®s[t]);break; - case SHIFT: - shift_assemble(t,®s[t]);break; - case SHIFTIMM: - shiftimm_assemble(t,®s[t]);break; - case LOAD: - load_assemble(t,®s[t]);break; - case LOADLR: - loadlr_assemble(t,®s[t]);break; - case STORE: - store_assemble(t,®s[t]);break; - case STORELR: - storelr_assemble(t,®s[t]);break; - case COP0: - cop0_assemble(t,®s[t]);break; - case COP1: - cop1_assemble(t,®s[t]);break; - case C1LS: - c1ls_assemble(t,®s[t]);break; - case COP2: - cop2_assemble(t,®s[t]);break; - case C2LS: - c2ls_assemble(t,®s[t]);break; - case C2OP: - c2op_assemble(t,®s[t]);break; - case MULTDIV: - multdiv_assemble(t,®s[t]); - multdiv_prepare_stall(i,®s[t]); - break; - case MOV: - mov_assemble(t,®s[t]);break; + switch (dops[t].itype) { case SYSCALL: case HLECALL: case INTCALL: @@ -4649,6 +4782,9 @@ static void ds_assemble_entry(int i) case CJUMP: case SJUMP: SysPrintf("Jump in the delay slot. This is probably a bug.\n"); + break; + default: + assemble(t, ®s[t], ccadj_); } store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4); load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4); @@ -4678,9 +4814,10 @@ static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2) emit_movimm_from(imm1,rt1,imm2,rt2); } -void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert) +static void do_cc(int i, const signed char i_regmap[], int *adj, + int addr, int taken, int invert) { - int count; + int count, count_plus2; void *jaddr; void *idle=NULL; int t=0; @@ -4692,14 +4829,15 @@ void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert) if(internal_branch(ba[i])) { t=(ba[i]-start)>>2; - if(dops[t].is_ds) *adj=-1; // Branch into delay slot adds an extra cycle + if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle else *adj=ccadj[t]; } else { *adj=0; } - count=ccadj[i]; + count = ccadj[i]; + count_plus2 = count + CLOCK_ADJUST(2); if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) { // Idle loop if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG); @@ -4710,26 +4848,26 @@ void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert) emit_jmp(0); } else if(*adj==0||invert) { - int cycles=CLOCK_ADJUST(count+2); + int cycles = count_plus2; // faster loop HACK #if 0 if (t&&*adj) { int rel=t-i; if(-NO_CYCLE_PENALTY_THR>2].regmap_entry); @@ -4984,7 +5122,7 @@ static void ujump_assemble_write_ra(int i) } } -static void ujump_assemble(int i,struct regstat *i_regs) +static void ujump_assemble(int i, const struct regstat *i_regs) { int ra_done=0; if(i==(ba[i]-start)>>2) assem_debug("idle loop\n"); @@ -5018,7 +5156,7 @@ static void ujump_assemble(int i,struct regstat *i_regs) if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp); #endif do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); - if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal_branch(ba[i])) assem_debug("branch: internal\n"); @@ -5054,7 +5192,7 @@ static void rjump_assemble_write_ra(int i) #endif } -static void rjump_assemble(int i,struct regstat *i_regs) +static void rjump_assemble(int i, const struct regstat *i_regs) { int temp; int rs,cc; @@ -5129,7 +5267,7 @@ static void rjump_assemble(int i,struct regstat *i_regs) //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN); //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen //assert(adj==0); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG); add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs); if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10) // special case for RFE @@ -5151,9 +5289,9 @@ static void rjump_assemble(int i,struct regstat *i_regs) #endif } -static void cjump_assemble(int i,struct regstat *i_regs) +static void cjump_assemble(int i, const struct regstat *i_regs) { - signed char *i_regmap=i_regs->regmap; + const signed char *i_regmap = i_regs->regmap; int cc; int match; match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); @@ -5219,7 +5357,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) if(unconditional) { do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); if(i!=(ba[i]-start)>>2 || source[i+1]!=0) { - if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) assem_debug("branch: internal\n"); @@ -5238,7 +5376,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) } } else if(nop) { - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); void *jaddr=out; emit_jns(0); add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); @@ -5246,7 +5384,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) else { void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL; do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); - if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); assert(s1l>=0); @@ -5301,7 +5439,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) { if(adj) { - emit_addimm(cc,-CLOCK_ADJUST(adj),cc); + emit_addimm(cc,-adj,cc); add_to_linker(out,ba[i],internal); }else{ emit_addnop(13); @@ -5311,7 +5449,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) }else #endif { - if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc); + if(adj) emit_addimm(cc,-adj,cc); store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) @@ -5331,16 +5469,13 @@ static void cjump_assemble(int i,struct regstat *i_regs) if(nottaken1) set_jump_target(nottaken1, out); if(adj) { - if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc); + if(!invert) emit_addimm(cc,adj,cc); } } // (!unconditional) } // if(ooo) else { // In-order execution (branch first) - //if(dops[i].likely) printf("IOL\n"); - //else - //printf("IOE\n"); void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL; if(!unconditional&&!nop) { //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); @@ -5384,6 +5519,8 @@ static void cjump_assemble(int i,struct regstat *i_regs) // load regs load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); address_generation(i+1,&branch_regs[i],0); + if (ram_offset) + load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG); load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); ds_assemble(i+1,&branch_regs[i]); cc=get_reg(branch_regs[i].regmap,CCREG); @@ -5395,7 +5532,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); do_cc(i,i_regmap,&adj,ba[i],TAKEN,0); assem_debug("cycle count (adj)\n"); - if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) assem_debug("branch: internal\n"); @@ -5414,18 +5551,19 @@ static void cjump_assemble(int i,struct regstat *i_regs) if(nottaken1) set_jump_target(nottaken1, out); set_jump_target(nottaken, out); assem_debug("2:\n"); - if(!dops[i].likely) { - wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); - load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); - address_generation(i+1,&branch_regs[i],0); - load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG); - ds_assemble(i+1,&branch_regs[i]); - } + wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); + // load regs + load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); + address_generation(i+1,&branch_regs[i],0); + if (ram_offset) + load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG); + load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); + ds_assemble(i+1,&branch_regs[i]); cc=get_reg(branch_regs[i].regmap,CCREG); - if(cc==-1&&!dops[i].likely) { + if (cc == -1) { // Cycle count isn't in a register, temporarily load it then write it out emit_loadreg(CCREG,HOST_CCREG); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG); void *jaddr=out; emit_jns(0); add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); @@ -5434,18 +5572,18 @@ static void cjump_assemble(int i,struct regstat *i_regs) else{ cc=get_reg(i_regmap,CCREG); assert(cc==HOST_CCREG); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); void *jaddr=out; emit_jns(0); - add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,dops[i].likely?NULLDS:NOTTAKEN,0); + add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); } } } } -static void sjump_assemble(int i,struct regstat *i_regs) +static void sjump_assemble(int i, const struct regstat *i_regs) { - signed char *i_regmap=i_regs->regmap; + const signed char *i_regmap = i_regs->regmap; int cc; int match; match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); @@ -5517,7 +5655,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) if(unconditional) { do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); if(i!=(ba[i]-start)>>2 || source[i+1]!=0) { - if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) assem_debug("branch: internal\n"); @@ -5536,7 +5674,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) } } else if(nevertaken) { - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); void *jaddr=out; emit_jns(0); add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); @@ -5544,7 +5682,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) else { void *nottaken = NULL; do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); - if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); { assert(s1l>=0); if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL @@ -5575,7 +5713,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) { if(adj) { - emit_addimm(cc,-CLOCK_ADJUST(adj),cc); + emit_addimm(cc,-adj,cc); add_to_linker(out,ba[i],internal); }else{ emit_addnop(13); @@ -5585,7 +5723,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) }else #endif { - if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc); + if(adj) emit_addimm(cc,-adj,cc); store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) @@ -5604,7 +5742,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) } if(adj) { - if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc); + if(!invert) emit_addimm(cc,adj,cc); } } // (!unconditional) } // if(ooo) @@ -5652,6 +5790,8 @@ static void sjump_assemble(int i,struct regstat *i_regs) // load regs load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); address_generation(i+1,&branch_regs[i],0); + if (ram_offset) + load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG); load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); ds_assemble(i+1,&branch_regs[i]); cc=get_reg(branch_regs[i].regmap,CCREG); @@ -5663,7 +5803,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); do_cc(i,i_regmap,&adj,ba[i],TAKEN,0); assem_debug("cycle count (adj)\n"); - if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) assem_debug("branch: internal\n"); @@ -5681,18 +5821,16 @@ static void sjump_assemble(int i,struct regstat *i_regs) if(!unconditional) { set_jump_target(nottaken, out); assem_debug("1:\n"); - if(!dops[i].likely) { - wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); - load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); - address_generation(i+1,&branch_regs[i],0); - load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG); - ds_assemble(i+1,&branch_regs[i]); - } + wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); + load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); + address_generation(i+1,&branch_regs[i],0); + load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG); + ds_assemble(i+1,&branch_regs[i]); cc=get_reg(branch_regs[i].regmap,CCREG); - if(cc==-1&&!dops[i].likely) { + if (cc == -1) { // Cycle count isn't in a register, temporarily load it then write it out emit_loadreg(CCREG,HOST_CCREG); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG); void *jaddr=out; emit_jns(0); add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); @@ -5701,16 +5839,16 @@ static void sjump_assemble(int i,struct regstat *i_regs) else{ cc=get_reg(i_regmap,CCREG); assert(cc==HOST_CCREG); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); void *jaddr=out; emit_jns(0); - add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,dops[i].likely?NULLDS:NOTTAKEN,0); + add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); } } } } -static void pagespan_assemble(int i,struct regstat *i_regs) +static void pagespan_assemble(int i, const struct regstat *i_regs) { int s1l=get_reg(i_regs->regmap,dops[i].rs1); int s2l=get_reg(i_regs->regmap,dops[i].rs2); @@ -5768,7 +5906,7 @@ static void pagespan_assemble(int i,struct regstat *i_regs) if((dops[i].opcode&0x2e)==4||dops[i].opcode==0x11) { // BEQ/BNE/BEQL/BNEL/BC1 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG); } - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); + emit_addimm(HOST_CCREG, ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG); if(dops[i].opcode==2) // J { unconditional=1; @@ -5894,7 +6032,7 @@ static void pagespan_assemble(int i,struct regstat *i_regs) assert(i_regs->regmap[HOST_CCREG]==CCREG); wb_dirtys(regs[i].regmap,regs[i].dirty); - if(dops[i].likely||unconditional) + if(unconditional) { emit_movimm(ba[i],HOST_BTREG); } @@ -5913,22 +6051,6 @@ static void pagespan_assemble(int i,struct regstat *i_regs) add_jump_out(target_addr,stub); } else set_jump_target(branch_addr, stub); - if(dops[i].likely) { - // Not-taken path - set_jump_target(nottaken, out); - wb_dirtys(regs[i].regmap,regs[i].dirty); - void *branch_addr=out; - emit_jmp(0); - int target_addr=start+i*4+8; - void *stub=out; - void *compiled_target_addr=check_addr(target_addr); - emit_extjump_ds(branch_addr, target_addr); - if(compiled_target_addr) { - set_jump_target(branch_addr, compiled_target_addr); - add_jump_out(target_addr,stub); - } - else set_jump_target(branch_addr, stub); - } } // Assemble the delay slot for the above @@ -5948,44 +6070,12 @@ static void pagespan_ds() emit_writeword(HOST_BTREG,&branch_target); load_regs(regs[0].regmap_entry,regs[0].regmap,dops[0].rs1,dops[0].rs2); address_generation(0,®s[0],regs[0].regmap_entry); - if(dops[0].itype==STORE||dops[0].itype==STORELR||(dops[0].opcode&0x3b)==0x39||(dops[0].opcode&0x3b)==0x3a) + if (ram_offset && (dops[0].is_load || dops[0].is_store)) + load_regs(regs[0].regmap_entry,regs[0].regmap,ROREG,ROREG); + if (dops[0].is_store) load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP); is_delayslot=0; - switch(dops[0].itype) { - case ALU: - alu_assemble(0,®s[0]);break; - case IMM16: - imm16_assemble(0,®s[0]);break; - case SHIFT: - shift_assemble(0,®s[0]);break; - case SHIFTIMM: - shiftimm_assemble(0,®s[0]);break; - case LOAD: - load_assemble(0,®s[0]);break; - case LOADLR: - loadlr_assemble(0,®s[0]);break; - case STORE: - store_assemble(0,®s[0]);break; - case STORELR: - storelr_assemble(0,®s[0]);break; - case COP0: - cop0_assemble(0,®s[0]);break; - case COP1: - cop1_assemble(0,®s[0]);break; - case C1LS: - c1ls_assemble(0,®s[0]);break; - case COP2: - cop2_assemble(0,®s[0]);break; - case C2LS: - c2ls_assemble(0,®s[0]);break; - case C2OP: - c2op_assemble(0,®s[0]);break; - case MULTDIV: - multdiv_assemble(0,®s[0]); - multdiv_prepare_stall(0,®s[0]); - break; - case MOV: - mov_assemble(0,®s[0]);break; + switch (dops[0].itype) { case SYSCALL: case HLECALL: case INTCALL: @@ -5995,6 +6085,9 @@ static void pagespan_ds() case CJUMP: case SJUMP: SysPrintf("Jump in the delay slot. This is probably a bug.\n"); + break; + default: + assemble(0, ®s[0], 0); } int btaddr=get_reg(regs[0].regmap,BTREG); if(btaddr<0) { @@ -6041,7 +6134,7 @@ void unneeded_registers(int istart,int iend,int r) for (i=iend;i>=istart;i--) { //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r); - if(dops[i].itype==RJUMP||dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP) + if(dops[i].is_jump) { // If subroutine call, flag return address as a possible branch target if(dops[i].rt1==31 && i>2].bt=1; if(ba[i]<=start+i*4) { // Backward branch - if(is_ujump(i)) + if(dops[i].is_ujump) { // Unconditional branch temp_u=1; @@ -6094,19 +6174,6 @@ void unneeded_registers(int istart,int iend,int r) temp_u|=1; temp_gte_u|=gte_rt[i+1]; temp_gte_u&=~gte_rs[i+1]; - // If branch is "likely" (and conditional) - // then we skip the delay slot on the fall-thru path - if(dops[i].likely) { - if(i>2]=gte_u_unknown; } } /*else*/ if(1) { - if (is_ujump(i)) + if (dops[i].is_ujump) { // Unconditional branch u=unneeded_reg[(ba[i]-start)>>2]; @@ -6146,19 +6213,8 @@ void unneeded_registers(int istart,int iend,int r) b|=1; gte_b|=gte_rt[i+1]; gte_b&=~gte_rs[i+1]; - // If branch is "likely" then we skip the - // delay slot on the fall-thru path - if(dops[i].likely) { - u=b; - gte_u=gte_b; - if(i=istart;i--) { - if(dops[i].itype==RJUMP||dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP) + if(dops[i].is_jump) { if(ba[i]=(start+slen*4)) { // Branch out of this block, flush all regs - if (is_ujump(i)) + if (dops[i].is_ujump) { // Unconditional branch will_dirty_i=0; @@ -6266,7 +6322,7 @@ void clean_registers(int istart,int iend,int wr) // Merge in delay slot (will dirty) for(r=0;ristart) { - if(dops[i].itype!=RJUMP&&dops[i].itype!=UJUMP&&dops[i].itype!=CJUMP&&dops[i].itype!=SJUMP) + if (!dops[i].is_jump) { // Don't store a register immediately after writing it, // may prevent dual-issue. @@ -6557,9 +6613,9 @@ void clean_registers(int istart,int iend,int wr) regs[i].dirty|=will_dirty_i; #ifndef DESTRUCTIVE_WRITEBACK regs[i].dirty&=wont_dirty_i; - if(dops[i].itype==RJUMP||dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP) + if(dops[i].is_jump) { - if (i < iend-1 && !is_ujump(i)) { + if (i < iend-1 && !dops[i].is_ujump) { for(r=0;rtranslation_cache); + #elif defined(_MSC_VER) + ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE, + PAGE_EXECUTE_READWRITE); #else uintptr_t desired_addr = 0; #ifdef __ELF__ @@ -6823,9 +6888,7 @@ void new_dynarec_init(void) #endif arch_init(); new_dynarec_test(); -#ifndef RAM_FIXED ram_offset=(uintptr_t)rdram-0x80000000; -#endif if (ram_offset!=0) SysPrintf("warning: RAM is not directly mapped, performance will suffer\n"); } @@ -6852,9 +6915,6 @@ void new_dynarec_cleanup(void) static u_int *get_source_start(u_int addr, u_int *limit) { - if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M)) - cycle_multiplier_override = 0; - if (addr < 0x00200000 || (0xa0000000 <= addr && addr < 0xa0200000)) { @@ -6869,7 +6929,7 @@ static u_int *get_source_start(u_int addr, u_int *limit) // BIOS. The multiplier should be much higher as it's uncached 8bit mem, // but timings in PCSX are too tied to the interpreter's BIAS if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M)) - cycle_multiplier_override = 200; + cycle_multiplier_active = 200; *limit = (addr & 0xfff00000) | 0x80000; return (u_int *)((u_char *)psxR + (addr&0x7ffff)); @@ -6981,6 +7041,42 @@ void new_dynarec_load_blocks(const void *save, int size) memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save)); } +static void apply_hacks(void) +{ + int i; + if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS)) + return; + /* special hack(s) */ + for (i = 0; i < slen - 4; i++) + { + // lui a4, 0xf200; jal ; addu a0, 2; slti v0, 28224 + if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP + && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a + && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2) + { + SysPrintf("PE2 hack @%08x\n", start + (i+3)*4); + dops[i + 3].itype = NOP; + } + } + i = slen; + if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008 + && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809 + && dops[i-7].itype == STORE) + { + i = i-8; + if (dops[i].itype == IMM16) + i--; + // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6 + if (dops[i].itype == STORELR && dops[i].rs1 == 6 + && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6) + { + SysPrintf("F1 hack from %08x\n", start); + if (f1_hack == 0) + f1_hack = ~0u; + } + } +} + int new_recompile_block(u_int addr) { u_int pagelimit = 0; @@ -7016,6 +7112,30 @@ int new_recompile_block(u_int addr) ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning); return 0; } + else if (f1_hack == ~0u || (f1_hack != 0 && start == f1_hack)) { + void *beginning = start_block(); + u_int page = get_page(start); + emit_readword(&psxRegs.GPR.n.sp, 0); + emit_readptr(&mem_rtab, 1); + emit_shrimm(0, 12, 2); + emit_readptr_dualindexedx_ptrlen(1, 2, 1); + emit_addimm(0, 0x18, 0); + emit_adds_ptr(1, 1, 1); + emit_ldr_dualindexed(1, 0, 0); + emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp) + emit_far_call(get_addr_ht); + emit_jmpreg(0); // jr k0 + literal_pool(0); + end_block(beginning); + + ll_add_flags(jump_in + page, start, state_rflags, beginning); + SysPrintf("F1 hack to %08x\n", start); + f1_hack = start; + return 0; + } + + cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT + ? cycle_multiplier_override : cycle_multiplier; source = get_source_start(start, &pagelimit); if (source == NULL) { @@ -7042,10 +7162,9 @@ int new_recompile_block(u_int addr) /* Pass 1 disassembly */ - for(i=0;!done;i++) { - dops[i].bt=0; - dops[i].likely=0; - dops[i].ooo=0; + for (i = 0; !done; i++) + { + memset(&dops[i], 0, sizeof(dops[i])); op2=0; minimum_free_regs[i]=0; dops[i].opcode=op=source[i]>>26; @@ -7302,7 +7421,6 @@ int new_recompile_block(u_int addr) if(op&2) { // BGTZ/BLEZ dops[i].rs2=0; } - dops[i].likely=(op>>4)?1:0; break; case SJUMP: dops[i].rs1=(source[i]>>21)&0x1f; @@ -7313,7 +7431,6 @@ int new_recompile_block(u_int addr) dops[i].rt1=31; // NOTE: If the branch is not taken, r31 is still overwritten } - dops[i].likely=(op2&2)?1:0; break; case ALU: dops[i].rs1=(source[i]>>21)&0x1f; // source @@ -7457,11 +7574,16 @@ int new_recompile_block(u_int addr) else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1)) dops[i].itype = type = UJUMP; + dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP); + dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0 + dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2 + dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2 + /* messy cases to just pass over to the interpreter */ - if (i > 0 && is_jump(i-1)) { + if (i > 0 && dops[i-1].is_jump) { int do_in_intrp=0; // branch in delay slot? - if (is_jump(i)) { + if (dops[i].is_jump) { // don't handle first branch and call interpreter if it's hit SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr); do_in_intrp=1; @@ -7476,24 +7598,24 @@ int new_recompile_block(u_int addr) dops[t+1].bt=1; // expected return from interpreter } else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&& - !(i>=3&&is_jump(i-3))) { + !(i>=3&&dops[i-3].is_jump)) { // v0 overwrite like this is a sign of trouble, bail out SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr); do_in_intrp=1; } } - if(do_in_intrp) { - dops[i-1].rs1=CCREG; - dops[i-1].rs2=dops[i-1].rt1=dops[i-1].rt2=0; - ba[i-1]=-1; - dops[i-1].itype=INTCALL; - done=2; + if (do_in_intrp) { + memset(&dops[i-1], 0, sizeof(dops[i-1])); + dops[i-1].itype = INTCALL; + dops[i-1].rs1 = CCREG; + ba[i-1] = -1; + done = 2; i--; // don't compile the DS } } /* Is this the end of the block? */ - if (i > 0 && is_ujump(i-1)) { + if (i > 0 && dops[i-1].is_ujump) { if(dops[i-1].rt1==0) { // Continue past subroutine call (JAL) done=2; } @@ -7529,13 +7651,15 @@ int new_recompile_block(u_int addr) } } slen=i; - if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP||dops[i-1].itype==RJUMP) { + if (dops[i-1].is_jump) { if(start+i*4==pagelimit) { dops[i-1].itype=SPAN; } } assert(slen>0); + apply_hacks(); + /* Pass 2 - Register dependencies and branch targets */ unneeded_registers(0,slen-1,0); @@ -7582,7 +7706,7 @@ int new_recompile_block(u_int addr) regs[i].wasconst=current.isconst; regs[i].wasdirty=current.dirty; regs[i].loadedconst=0; - if(dops[i].itype!=UJUMP&&dops[i].itype!=CJUMP&&dops[i].itype!=SJUMP&&dops[i].itype!=RJUMP) { + if (!dops[i].is_jump) { if(i+10&&(dops[i-1].itype==RJUMP||dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP||dops[i].itype==SYSCALL||dops[i].itype==HLECALL)) + ccadj[i] = CLOCK_ADJUST(cc); + if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL)) { cc=0; } @@ -8198,7 +8325,7 @@ int new_recompile_block(u_int addr) for (i=slen-1;i>=0;i--) { int hr; - if(dops[i].itype==RJUMP||dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP) + if(dops[i].is_jump) { if(ba[i]=(start+slen*4)) { @@ -8219,7 +8346,7 @@ int new_recompile_block(u_int addr) } } // Conditional branch may need registers for following instructions - if (!is_ujump(i)) + if (!dops[i].is_ujump) { if(i>hr)&1)) { if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1; - if((regs[i].regmap[hr]&63)!=dops[i].rs1 && (regs[i].regmap[hr]&63)!=dops[i].rs2 && - (regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 && - (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG) - { - if (!is_ujump(i)) - { - if(dops[i].likely) { - regs[i].regmap[hr]=-1; - regs[i].isconst&=~(1<0) { - int map=-1,temp=-1; - if(dops[i].itype==STORE || dops[i].itype==STORELR || - (dops[i].opcode&0x3b)==0x39 || (dops[i].opcode&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2 - map=INVCP; - } - if(dops[i].itype==LOADLR || dops[i].itype==STORELR || - dops[i].itype==C1LS || dops[i].itype==C2LS) - temp=FTEMP; + int map1 = -1, map2 = -1, temp=-1; + if (dops[i].is_load || dops[i].is_store) + map1 = ROREG; + if (dops[i].is_store) + map2 = INVCP; + if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS) + temp = FTEMP; if((regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 && regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 && - (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map && - (dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)) + (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 && + //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG) + regs[i].regmap[hr] != CCREG) { if(i>2; - if(t>0&&(dops[t-1].itype!=UJUMP&&dops[t-1].itype!=RJUMP&&dops[t-1].itype!=CJUMP&&dops[t-1].itype!=SJUMP)) // loop_preload can't handle jumps into delay slots + if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated for(hr=0;hr\n"); - drc_dbg_emit_do_cmp(i); + drc_dbg_emit_do_cmp(i, ccadj[i]); // load regs if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG) @@ -9091,14 +9205,16 @@ int new_recompile_block(u_int addr) load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2); address_generation(i,®s[i],regs[i].regmap_entry); load_consts(regmap_pre[i],regs[i].regmap,i); - if(dops[i].itype==RJUMP||dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP) + if(dops[i].is_jump) { // Load the delay slot registers if necessary if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0)) load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1); if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0)) load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2); - if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) + if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) + load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG); + if (dops[i+1].is_store) load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP); } else if(i+1 1) { - if(!is_ujump(i-2)&&dops[i-1].itype!=SPAN) { - assert(dops[i-1].itype!=UJUMP&&dops[i-1].itype!=CJUMP&&dops[i-1].itype!=SJUMP&&dops[i-1].itype!=RJUMP); + if (!dops[i-2].is_ujump && dops[i-1].itype != SPAN) { + assert(!dops[i-1].is_jump); assert(i==slen); if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) { store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4); if(regs[i-1].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG); + emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG); } - else if(!dops[i-2].likely) + else { store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4); assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG); } - else - { - store_regs_bt(regs[i-2].regmap,regs[i-2].dirty,start+i*4); - assert(regs[i-2].regmap[HOST_CCREG]==CCREG); - } add_to_linker(out,start+i*4,0); emit_jmp(0); } @@ -9209,11 +9272,11 @@ int new_recompile_block(u_int addr) else { assert(i>0); - assert(dops[i-1].itype!=UJUMP&&dops[i-1].itype!=CJUMP&&dops[i-1].itype!=SJUMP&&dops[i-1].itype!=RJUMP); + assert(!dops[i-1].is_jump); store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4); if(regs[i-1].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG); + emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG); add_to_linker(out,start+i*4,0); emit_jmp(0); } @@ -9406,6 +9469,9 @@ int new_recompile_block(u_int addr) } expirep=(expirep+1)&65535; } +#ifdef ASSEM_PRINT + fflush(stdout); +#endif return 0; }