X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fnew_dynarec.c;h=9ce1f069a92bdd5766adb1db2e175aedf489c746;hp=78a342d262b71cbfc703894cfc4d28104235b62b;hb=3968e69e7fa8f9cb0d44ac79477d5929b9649271;hpb=ad49de8937ff55b6295a8065d1b942c29726a363

diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c
index 78a342d2..9ce1f069 100644
--- a/libpcsxcore/new_dynarec/new_dynarec.c
+++ b/libpcsxcore/new_dynarec/new_dynarec.c
@@ -35,9 +35,11 @@ static int sceBlock;
 #endif
 
 #include "new_dynarec_config.h"
-#include "../psxhle.h" //emulator interface
+#include "../psxhle.h"
+#include "../psxinterpreter.h"
 #include "emu_if.h" //emulator interface
 
+#define noinline __attribute__((noinline,noclone))
 #ifndef ARRAY_SIZE
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
 #endif
@@ -57,6 +59,9 @@ static int sceBlock;
 #ifdef __arm__
 #include "assem_arm.h"
 #endif
+#ifdef __aarch64__
+#include "assem_arm64.h"
+#endif
 
 #define MAXBLOCK 4096
 #define MAX_OUTPUT_BLOCK_SIZE 262144
@@ -144,8 +149,6 @@ struct link_entry
   static u_char rs2[MAXBLOCK];
   static u_char rt1[MAXBLOCK];
   static u_char rt2[MAXBLOCK];
-  static u_char us1[MAXBLOCK];
-  static u_char us2[MAXBLOCK];
   static u_char dep1[MAXBLOCK];
   static u_char dep2[MAXBLOCK];
   static u_char lt1[MAXBLOCK];
@@ -164,7 +167,7 @@ struct link_entry
   static char ooo[MAXBLOCK];
   static uint64_t unneeded_reg[MAXBLOCK];
   static uint64_t branch_unneeded_reg[MAXBLOCK];
-  static signed char regmap_pre[MAXBLOCK][HOST_REGS];
+  static signed char regmap_pre[MAXBLOCK][HOST_REGS]; // pre-instruction i?
   static uint64_t current_constmap[HOST_REGS];
   static uint64_t constmap[MAXBLOCK][HOST_REGS];
   static struct regstat regs[MAXBLOCK];
@@ -195,13 +198,19 @@ struct link_entry
 
   int new_dynarec_hacks;
   int new_dynarec_did_compile;
+
+  extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
+  extern int last_count;  // last absolute target, often = next_interupt
+  extern int pcaddr;
+  extern int pending_exception;
+  extern int branch_target;
+  extern uintptr_t mini_ht[32][2];
   extern u_char restore_candidate[512];
-  extern int cycle_count;
 
   /* registers that may be allocated */
   /* 1-31 gpr */
-#define HIREG 32 // hi
-#define LOREG 33 // lo
+#define LOREG 32 // lo
+#define HIREG 33 // hi
 //#define FSREG 34 // FPU status (FCSR)
 #define CSREG 35 // Coprocessor status
 #define CCREG 36 // Cycle count
@@ -260,8 +269,11 @@ struct link_entry
 #define NOTTAKEN 2
 #define NULLDS 3
 
+#define DJT_1 (void *)1l // no function, just a label in assem_debug log
+#define DJT_2 (void *)2l
+
 // asm linkage
-int new_recompile_block(int addr);
+int new_recompile_block(u_int addr);
 void *get_addr_ht(u_int vaddr);
 void invalidate_block(u_int block);
 void invalidate_addr(u_int addr);
@@ -269,14 +281,11 @@ void remove_hash(int vaddr);
 void dyna_linker();
 void dyna_linker_ds();
 void verify_code();
-void verify_code_vm();
 void verify_code_ds();
 void cc_interrupt();
 void fp_exception();
 void fp_exception_ds();
-void jump_syscall_hle();
-void jump_hlecall();
-void jump_intcall();
+void jump_to_new_pc();
 void new_dyna_leave();
 
 // Needed by assembler
@@ -288,13 +297,17 @@ static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 static void load_regs_entry(int t);
 static void load_all_consts(signed char regmap[],u_int dirty,int i);
 
-static int verify_dirty(u_int *ptr);
+static int verify_dirty(const u_int *ptr);
 static int get_final_value(int hr, int i, int *value);
 static void add_stub(enum stub_type type, void *addr, void *retaddr,
   u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
   int i, int addr_reg, struct regstat *i_regs, int ccadj, u_int reglist);
 static void add_to_linker(void *addr, u_int target, int ext);
+static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override);
+static void *get_direct_memhandler(void *table, u_int addr,
+  enum stub_type type, uintptr_t *addr_host);
+static void pass_args(int a0, int a1);
 
 static void mprotect_w_x(void *start, void *end, int is_x)
 {
@@ -337,6 +350,8 @@ static void end_tcache_write(void *start, void *end)
   __clear_cache(start, end);
   #endif
   (void)len;
+#else
+  __clear_cache(start, end);
 #endif
 
   mprotect_w_x(start, end, 1);
@@ -406,7 +421,7 @@ static int doesnt_expire_soon(void *tcaddr)
 
 // Get address from virtual address
 // This is called from the recompiled JR/JALR instructions
-void *get_addr(u_int vaddr)
+void noinline *get_addr(u_int vaddr)
 {
   u_int page=get_page(vaddr);
   u_int vpage=get_vpage(vaddr);
@@ -474,7 +489,7 @@ void clear_all_regs(signed char regmap[])
   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 }
 
-signed char get_reg(signed char regmap[],int r)
+static signed char get_reg(const signed char regmap[],int r)
 {
   int hr;
   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
@@ -482,7 +497,7 @@ signed char get_reg(signed char regmap[],int r)
 }
 
 // Find a register that is available for two consecutive cycles
-signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
+static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
 {
   int hr;
   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
@@ -522,10 +537,6 @@ void set_const(struct regstat *cur,signed char reg,uint64_t value)
       cur->isconst|=1<<hr;
       current_constmap[hr]=value;
     }
-    else if((cur->regmap[hr]^64)==reg) {
-      cur->isconst|=1<<hr;
-      current_constmap[hr]=value>>32;
-    }
   }
 }
 
@@ -562,7 +573,7 @@ uint64_t get_const(struct regstat *cur,signed char reg)
     }
   }
   SysPrintf("Unknown constant in r%d\n",reg);
-  exit(1);
+  abort();
 }
 
 // Least soon needed registers
@@ -783,6 +794,65 @@ void alloc_all(struct regstat *cur,int i)
   }
 }
 
+#ifndef NDEBUG
+static int host_tempreg_in_use;
+
+static void host_tempreg_acquire(void)
+{
+  assert(!host_tempreg_in_use);
+  host_tempreg_in_use = 1;
+}
+
+static void host_tempreg_release(void)
+{
+  host_tempreg_in_use = 0;
+}
+#else
+static void host_tempreg_acquire(void) {}
+static void host_tempreg_release(void) {}
+#endif
+
+#ifdef DRC_DBG
+extern void gen_interupt();
+extern void do_insn_cmp();
+#define FUNCNAME(f) { f, " " #f }
+static const struct {
+  void *addr;
+  const char *name;
+} function_names[] = {
+  FUNCNAME(cc_interrupt),
+  FUNCNAME(gen_interupt),
+  FUNCNAME(get_addr_ht),
+  FUNCNAME(get_addr),
+  FUNCNAME(jump_handler_read8),
+  FUNCNAME(jump_handler_read16),
+  FUNCNAME(jump_handler_read32),
+  FUNCNAME(jump_handler_write8),
+  FUNCNAME(jump_handler_write16),
+  FUNCNAME(jump_handler_write32),
+  FUNCNAME(invalidate_addr),
+  FUNCNAME(jump_to_new_pc),
+  FUNCNAME(new_dyna_leave),
+  FUNCNAME(pcsx_mtc0),
+  FUNCNAME(pcsx_mtc0_ds),
+  FUNCNAME(do_insn_cmp),
+#ifdef __arm__
+  FUNCNAME(verify_code),
+#endif
+};
+
+static const char *func_name(const void *a)
+{
+  int i;
+  for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
+    if (function_names[i].addr == a)
+      return function_names[i].name;
+  return "";
+}
+#else
+#define func_name(x) ""
+#endif
+
 #ifdef __i386__
 #include "assem_x86.c"
 #endif
@@ -792,6 +862,9 @@ void alloc_all(struct regstat *cur,int i)
 #ifdef __arm__
 #include "assem_arm.c"
 #endif
+#ifdef __aarch64__
+#include "assem_arm64.c"
+#endif
 
 // Add virtual address mapping to linked list
 void ll_add(struct ll_entry **head,int vaddr,void *addr)
@@ -920,7 +993,7 @@ static void ll_kill_pointers(struct ll_entry *head,uintptr_t addr,int shift)
     {
       inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
       void *host_addr=find_extjump_insn(head->addr);
-      #ifdef __arm__
+      #if defined(__arm__) || defined(__aarch64__)
         mark_clear_cache(host_addr);
       #endif
       set_jump_target(host_addr, head->addr);
@@ -930,7 +1003,7 @@ static void ll_kill_pointers(struct ll_entry *head,uintptr_t addr,int shift)
 }
 
 // This is called when we write to a compiled block (see do_invstub)
-void invalidate_page(u_int page)
+static void invalidate_page(u_int page)
 {
   struct ll_entry *head;
   struct ll_entry *next;
@@ -948,7 +1021,7 @@ void invalidate_page(u_int page)
   while(head!=NULL) {
     inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
     void *host_addr=find_extjump_insn(head->addr);
-    #ifdef __arm__
+    #if defined(__arm__) || defined(__aarch64__)
       mark_clear_cache(host_addr);
     #endif
     set_jump_target(host_addr, head->addr);
@@ -973,7 +1046,7 @@ static void invalidate_block_range(u_int block, u_int first, u_int last)
   for(first=page+1;first<last;first++) {
     invalidate_page(first);
   }
-  #ifdef __arm__
+  #if defined(__arm__) || defined(__aarch64__)
     do_clear_cache();
   #endif
 
@@ -1087,14 +1160,25 @@ void invalidate_all_pages()
   #endif
 }
 
+static void do_invstub(int n)
+{
+  literal_pool(20);
+  u_int reglist=stubs[n].a;
+  set_jump_target(stubs[n].addr, out);
+  save_regs(reglist);
+  if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
+  emit_call(invalidate_addr);
+  restore_regs(reglist);
+  emit_jmp(stubs[n].retaddr); // return address
+}
+
 // Add an entry to jump_out after making a link
+// src should point to code by emit_extjump2()
 void add_link(u_int vaddr,void *src)
 {
   u_int page=get_page(vaddr);
   inv_debug("add_link: %p -> %x (%d)\n",src,vaddr,page);
-  int *ptr=(int *)(src+4);
-  assert((*ptr&0x0fff0000)==0x059f0000);
-  (void)ptr;
+  check_extjump2(src);
   ll_add(jump_out+page,vaddr,src);
   //void *ptr=get_pointer(src);
   //inv_debug("add_link: Pointer is to %p\n",ptr);
@@ -1149,6 +1233,240 @@ void clean_blocks(u_int page)
   }
 }
 
+/* Register allocation */
+
+// Note: registers are allocated clean (unmodified state)
+// if you intend to modify the register, you must call dirty_reg().
+static void alloc_reg(struct regstat *cur,int i,signed char reg)
+{
+  int r,hr;
+  int preferred_reg = (reg&7);
+  if(reg==CCREG) preferred_reg=HOST_CCREG;
+  if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
+
+  // Don't allocate unused registers
+  if((cur->u>>reg)&1) return;
+
+  // see if it's already allocated
+  for(hr=0;hr<HOST_REGS;hr++)
+  {
+    if(cur->regmap[hr]==reg) return;
+  }
+
+  // Keep the same mapping if the register was already allocated in a loop
+  preferred_reg = loop_reg(i,reg,preferred_reg);
+
+  // Try to allocate the preferred register
+  if(cur->regmap[preferred_reg]==-1) {
+    cur->regmap[preferred_reg]=reg;
+    cur->dirty&=~(1<<preferred_reg);
+    cur->isconst&=~(1<<preferred_reg);
+    return;
+  }
+  r=cur->regmap[preferred_reg];
+  assert(r < 64);
+  if((cur->u>>r)&1) {
+    cur->regmap[preferred_reg]=reg;
+    cur->dirty&=~(1<<preferred_reg);
+    cur->isconst&=~(1<<preferred_reg);
+    return;
+  }
+
+  // Clear any unneeded registers
+  // We try to keep the mapping consistent, if possible, because it
+  // makes branches easier (especially loops).  So we try to allocate
+  // first (see above) before removing old mappings.  If this is not
+  // possible then go ahead and clear out the registers that are no
+  // longer needed.
+  for(hr=0;hr<HOST_REGS;hr++)
+  {
+    r=cur->regmap[hr];
+    if(r>=0) {
+      assert(r < 64);
+      if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
+    }
+  }
+  // Try to allocate any available register, but prefer
+  // registers that have not been used recently.
+  if(i>0) {
+    for(hr=0;hr<HOST_REGS;hr++) {
+      if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
+        if(regs[i-1].regmap[hr]!=rs1[i-1]&&regs[i-1].regmap[hr]!=rs2[i-1]&&regs[i-1].regmap[hr]!=rt1[i-1]&&regs[i-1].regmap[hr]!=rt2[i-1]) {
+          cur->regmap[hr]=reg;
+          cur->dirty&=~(1<<hr);
+          cur->isconst&=~(1<<hr);
+          return;
+        }
+      }
+    }
+  }
+  // Try to allocate any available register
+  for(hr=0;hr<HOST_REGS;hr++) {
+    if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
+      cur->regmap[hr]=reg;
+      cur->dirty&=~(1<<hr);
+      cur->isconst&=~(1<<hr);
+      return;
+    }
+  }
+
+  // Ok, now we have to evict someone
+  // Pick a register we hopefully won't need soon
+  u_char hsn[MAXREG+1];
+  memset(hsn,10,sizeof(hsn));
+  int j;
+  lsn(hsn,i,&preferred_reg);
+  //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
+  //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
+  if(i>0) {
+    // Don't evict the cycle count at entry points, otherwise the entry
+    // stub will have to write it.
+    if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
+    if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP)) hsn[CCREG]=2;
+    for(j=10;j>=3;j--)
+    {
+      // Alloc preferred register if available
+      if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
+        for(hr=0;hr<HOST_REGS;hr++) {
+          // Evict both parts of a 64-bit register
+          if((cur->regmap[hr]&63)==r) {
+            cur->regmap[hr]=-1;
+            cur->dirty&=~(1<<hr);
+            cur->isconst&=~(1<<hr);
+          }
+        }
+        cur->regmap[preferred_reg]=reg;
+        return;
+      }
+      for(r=1;r<=MAXREG;r++)
+      {
+        if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
+          for(hr=0;hr<HOST_REGS;hr++) {
+            if(hr!=HOST_CCREG||j<hsn[CCREG]) {
+              if(cur->regmap[hr]==r) {
+                cur->regmap[hr]=reg;
+                cur->dirty&=~(1<<hr);
+                cur->isconst&=~(1<<hr);
+                return;
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+  for(j=10;j>=0;j--)
+  {
+    for(r=1;r<=MAXREG;r++)
+    {
+      if(hsn[r]==j) {
+        for(hr=0;hr<HOST_REGS;hr++) {
+          if(cur->regmap[hr]==r) {
+            cur->regmap[hr]=reg;
+            cur->dirty&=~(1<<hr);
+            cur->isconst&=~(1<<hr);
+            return;
+          }
+        }
+      }
+    }
+  }
+  SysPrintf("This shouldn't happen (alloc_reg)");abort();
+}
+
+// Allocate a temporary register.  This is done without regard to
+// dirty status or whether the register we request is on the unneeded list
+// Note: This will only allocate one register, even if called multiple times
+static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
+{
+  int r,hr;
+  int preferred_reg = -1;
+
+  // see if it's already allocated
+  for(hr=0;hr<HOST_REGS;hr++)
+  {
+    if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
+  }
+
+  // Try to allocate any available register
+  for(hr=HOST_REGS-1;hr>=0;hr--) {
+    if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
+      cur->regmap[hr]=reg;
+      cur->dirty&=~(1<<hr);
+      cur->isconst&=~(1<<hr);
+      return;
+    }
+  }
+
+  // Find an unneeded register
+  for(hr=HOST_REGS-1;hr>=0;hr--)
+  {
+    r=cur->regmap[hr];
+    if(r>=0) {
+      assert(r < 64);
+      if((cur->u>>r)&1) {
+        if(i==0||((unneeded_reg[i-1]>>r)&1)) {
+          cur->regmap[hr]=reg;
+          cur->dirty&=~(1<<hr);
+          cur->isconst&=~(1<<hr);
+          return;
+        }
+      }
+    }
+  }
+
+  // Ok, now we have to evict someone
+  // Pick a register we hopefully won't need soon
+  // TODO: we might want to follow unconditional jumps here
+  // TODO: get rid of dupe code and make this into a function
+  u_char hsn[MAXREG+1];
+  memset(hsn,10,sizeof(hsn));
+  int j;
+  lsn(hsn,i,&preferred_reg);
+  //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
+  if(i>0) {
+    // Don't evict the cycle count at entry points, otherwise the entry
+    // stub will have to write it.
+    if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
+    if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP)) hsn[CCREG]=2;
+    for(j=10;j>=3;j--)
+    {
+      for(r=1;r<=MAXREG;r++)
+      {
+        if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
+          for(hr=0;hr<HOST_REGS;hr++) {
+            if(hr!=HOST_CCREG||hsn[CCREG]>2) {
+              if(cur->regmap[hr]==r) {
+                cur->regmap[hr]=reg;
+                cur->dirty&=~(1<<hr);
+                cur->isconst&=~(1<<hr);
+                return;
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+  for(j=10;j>=0;j--)
+  {
+    for(r=1;r<=MAXREG;r++)
+    {
+      if(hsn[r]==j) {
+        for(hr=0;hr<HOST_REGS;hr++) {
+          if(cur->regmap[hr]==r) {
+            cur->regmap[hr]=reg;
+            cur->dirty&=~(1<<hr);
+            cur->isconst&=~(1<<hr);
+            return;
+          }
+        }
+      }
+    }
+  }
+  SysPrintf("This shouldn't happen");abort();
+}
+
 static void mov_alloc(struct regstat *current,int i)
 {
   // Note: Don't need to actually alloc the source registers
@@ -1529,7 +1847,7 @@ void delayslot_alloc(struct regstat *current,int i)
     case SYSCALL:
     case HLECALL:
     case SPAN:
-      assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
+      assem_debug("jump in the delay slot.  this shouldn't happen.\n");//abort();
       SysPrintf("Disabled speculative precompilation\n");
       stop_after_jal=1;
       break;
@@ -1617,7 +1935,7 @@ static void pagespan_alloc(struct regstat *current,int i)
 static void add_stub(enum stub_type type, void *addr, void *retaddr,
   u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
 {
-  assert(a < ARRAY_SIZE(stubs));
+  assert(stubcount < ARRAY_SIZE(stubs));
   stubs[stubcount].type = type;
   stubs[stubcount].addr = addr;
   stubs[stubcount].retaddr = retaddr;
@@ -1651,16 +1969,47 @@ static void wb_register(signed char r,signed char regmap[],uint64_t dirty)
   }
 }
 
-void rlist()
+static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
 {
-  int i;
-  printf("TRACE: ");
-  for(i=0;i<32;i++)
-    printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
-  printf("\n");
+  //if(dirty_pre==dirty) return;
+  int hr,reg;
+  for(hr=0;hr<HOST_REGS;hr++) {
+    if(hr!=EXCLUDE_REG) {
+      reg=pre[hr];
+      if(((~u)>>(reg&63))&1) {
+        if(reg>0) {
+          if(((dirty_pre&~dirty)>>hr)&1) {
+            if(reg>0&&reg<34) {
+              emit_storereg(reg,hr);
+            }
+            else if(reg>=64) {
+              assert(0);
+            }
+          }
+        }
+      }
+    }
+  }
 }
 
-void alu_assemble(int i,struct regstat *i_regs)
+// trashes r2
+static void pass_args(int a0, int a1)
+{
+  if(a0==1&&a1==0) {
+    // must swap
+    emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
+  }
+  else if(a0!=0&&a1==0) {
+    emit_mov(a1,1);
+    if (a0>=0) emit_mov(a0,0);
+  }
+  else {
+    if(a0>=0&&a0!=0) emit_mov(a0,0);
+    if(a1>=0&&a1!=1) emit_mov(a1,1);
+  }
+}
+
+static void alu_assemble(int i,struct regstat *i_regs)
 {
   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
     if(rt1[i]) {
@@ -1843,24 +2192,15 @@ void imm16_assemble(int i,struct regstat *i_regs)
   }
   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
     if(rt1[i]) {
-      signed char sh,sl,th,tl;
-      th=get_reg(i_regs->regmap,rt1[i]|64);
+      signed char sl,tl;
       tl=get_reg(i_regs->regmap,rt1[i]);
-      sh=get_reg(i_regs->regmap,rs1[i]|64);
       sl=get_reg(i_regs->regmap,rs1[i]);
       if(tl>=0) {
         if(rs1[i]) {
-          assert(sh>=0);
           assert(sl>=0);
-          if(th>=0) {
-            emit_addimm64_32(sh,sl,imm[i],th,tl);
-          }
-          else {
-            emit_addimm(sl,imm[i],tl);
-          }
+          emit_addimm(sl,imm[i],tl);
         } else {
           emit_movimm(imm[i],tl);
-          if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
         }
       }
     }
@@ -1907,10 +2247,8 @@ void imm16_assemble(int i,struct regstat *i_regs)
   }
   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
     if(rt1[i]) {
-      signed char sh,sl,th,tl;
-      th=get_reg(i_regs->regmap,rt1[i]|64);
+      signed char sl,tl;
       tl=get_reg(i_regs->regmap,rt1[i]);
-      sh=get_reg(i_regs->regmap,rs1[i]|64);
       sl=get_reg(i_regs->regmap,rs1[i]);
       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
         if(opcode[i]==0x0c) //ANDI
@@ -1928,7 +2266,6 @@ void imm16_assemble(int i,struct regstat *i_regs)
           }
           else
             emit_zeroreg(tl);
-          if(th>=0) emit_zeroreg(th);
         }
         else
         {
@@ -1936,13 +2273,6 @@ void imm16_assemble(int i,struct regstat *i_regs)
             if(sl<0) {
               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
             }
-            if(th>=0) {
-              if(sh<0) {
-                emit_loadreg(rs1[i]|64,th);
-              }else{
-                emit_mov(sh,th);
-              }
-            }
             if(opcode[i]==0x0d) { // ORI
               if(sl<0) {
                 emit_orimm(tl,imm[i],tl);
@@ -1966,7 +2296,6 @@ void imm16_assemble(int i,struct regstat *i_regs)
           }
           else {
             emit_movimm(imm[i],tl);
-            if(th>=0) emit_zeroreg(th);
           }
         }
       }
@@ -2032,22 +2361,177 @@ void shiftimm_assemble(int i,struct regstat *i_regs)
 }
 
 #ifndef shift_assemble
-void shift_assemble(int i,struct regstat *i_regs)
+static void shift_assemble(int i,struct regstat *i_regs)
 {
-  printf("Need shift_assemble for this architecture.\n");
-  exit(1);
+  signed char s,t,shift;
+  if (rt1[i] == 0)
+    return;
+  assert(opcode2[i]<=0x07); // SLLV/SRLV/SRAV
+  t = get_reg(i_regs->regmap, rt1[i]);
+  s = get_reg(i_regs->regmap, rs1[i]);
+  shift = get_reg(i_regs->regmap, rs2[i]);
+  if (t < 0)
+    return;
+
+  if(rs1[i]==0)
+    emit_zeroreg(t);
+  else if(rs2[i]==0) {
+    assert(s>=0);
+    if(s!=t) emit_mov(s,t);
+  }
+  else {
+    host_tempreg_acquire();
+    emit_andimm(shift,31,HOST_TEMPREG);
+    switch(opcode2[i]) {
+    case 4: // SLLV
+      emit_shl(s,HOST_TEMPREG,t);
+      break;
+    case 6: // SRLV
+      emit_shr(s,HOST_TEMPREG,t);
+      break;
+    case 7: // SRAV
+      emit_sar(s,HOST_TEMPREG,t);
+      break;
+    default:
+      assert(0);
+    }
+    host_tempreg_release();
+  }
 }
+
 #endif
 
-void load_assemble(int i,struct regstat *i_regs)
+enum {
+  MTYPE_8000 = 0,
+  MTYPE_8020,
+  MTYPE_0000,
+  MTYPE_A000,
+  MTYPE_1F80,
+};
+
+static int get_ptr_mem_type(u_int a)
+{
+  if(a < 0x00200000) {
+    if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
+      // return wrong, must use memhandler for BIOS self-test to pass
+      // 007 does similar stuff from a00 mirror, weird stuff
+      return MTYPE_8000;
+    return MTYPE_0000;
+  }
+  if(0x1f800000 <= a && a < 0x1f801000)
+    return MTYPE_1F80;
+  if(0x80200000 <= a && a < 0x80800000)
+    return MTYPE_8020;
+  if(0xa0000000 <= a && a < 0xa0200000)
+    return MTYPE_A000;
+  return MTYPE_8000;
+}
+
+static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override)
+{
+  void *jaddr = NULL;
+  int type=0;
+  int mr=rs1[i];
+  if(((smrv_strong|smrv_weak)>>mr)&1) {
+    type=get_ptr_mem_type(smrv[mr]);
+    //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
+  }
+  else {
+    // use the mirror we are running on
+    type=get_ptr_mem_type(start);
+    //printf("set nospec   @%08x r%d %d\n", start+i*4, mr, type);
+  }
+
+  if(type==MTYPE_8020) { // RAM 80200000+ mirror
+    host_tempreg_acquire();
+    emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
+    addr=*addr_reg_override=HOST_TEMPREG;
+    type=0;
+  }
+  else if(type==MTYPE_0000) { // RAM 0 mirror
+    host_tempreg_acquire();
+    emit_orimm(addr,0x80000000,HOST_TEMPREG);
+    addr=*addr_reg_override=HOST_TEMPREG;
+    type=0;
+  }
+  else if(type==MTYPE_A000) { // RAM A mirror
+    host_tempreg_acquire();
+    emit_andimm(addr,~0x20000000,HOST_TEMPREG);
+    addr=*addr_reg_override=HOST_TEMPREG;
+    type=0;
+  }
+  else if(type==MTYPE_1F80) { // scratchpad
+    if (psxH == (void *)0x1f800000) {
+      host_tempreg_acquire();
+      emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
+      emit_cmpimm(HOST_TEMPREG,0x1000);
+      host_tempreg_release();
+      jaddr=out;
+      emit_jc(0);
+    }
+    else {
+      // do the usual RAM check, jump will go to the right handler
+      type=0;
+    }
+  }
+
+  if(type==0)
+  {
+    emit_cmpimm(addr,RAM_SIZE);
+    jaddr=out;
+    #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
+    // Hint to branch predictor that the branch is unlikely to be taken
+    if(rs1[i]>=28)
+      emit_jno_unlikely(0);
+    else
+    #endif
+      emit_jno(0);
+    if(ram_offset!=0) {
+      host_tempreg_acquire();
+      emit_addimm(addr,ram_offset,HOST_TEMPREG);
+      addr=*addr_reg_override=HOST_TEMPREG;
+    }
+  }
+
+  return jaddr;
+}
+
+// return memhandler, or get directly accessable address and return 0
+static void *get_direct_memhandler(void *table, u_int addr,
+  enum stub_type type, uintptr_t *addr_host)
 {
-  int s,th,tl,addr;
+  uintptr_t l1, l2 = 0;
+  l1 = ((uintptr_t *)table)[addr>>12];
+  if ((l1 & (1ul << (sizeof(l1)*8-1))) == 0) {
+    uintptr_t v = l1 << 1;
+    *addr_host = v + addr;
+    return NULL;
+  }
+  else {
+    l1 <<= 1;
+    if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
+      l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
+    else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
+      l2=((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
+    else
+      l2=((uintptr_t *)l1)[(addr&0xfff)/4];
+    if ((l2 & (1<<31)) == 0) {
+      uintptr_t v = l2 << 1;
+      *addr_host = v + (addr&0xfff);
+      return NULL;
+    }
+    return (void *)(l2 << 1);
+  }
+}
+
+static void load_assemble(int i,struct regstat *i_regs)
+{
+  int s,tl,addr;
   int offset;
   void *jaddr=0;
   int memtarget=0,c=0;
-  int fastload_reg_override=0;
+  int fastio_reg_override=-1;
   u_int hr,reglist=0;
-  th=get_reg(i_regs->regmap,rt1[i]|64);
   tl=get_reg(i_regs->regmap,rt1[i]);
   s=get_reg(i_regs->regmap,rs1[i]);
   offset=imm[i];
@@ -2080,19 +2564,19 @@ void load_assemble(int i,struct regstat *i_regs)
   //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
   reglist&=~(1<<tl);
-  if(th>=0) reglist&=~(1<<th);
   if(!c) {
     #ifdef R29_HACK
     // Strmnnrmn's speed hack
     if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
     #endif
     {
-      jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
+      jaddr=emit_fastpath_cmp_jump(i,addr,&fastio_reg_override);
     }
   }
   else if(ram_offset&&memtarget) {
+    host_tempreg_acquire();
     emit_addimm(addr,ram_offset,HOST_TEMPREG);
-    fastload_reg_override=HOST_TEMPREG;
+    fastio_reg_override=HOST_TEMPREG;
   }
   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
   if (opcode[i]==0x20) { // LB
@@ -2101,7 +2585,7 @@ void load_assemble(int i,struct regstat *i_regs)
         {
           int x=0,a=tl;
           if(!c) a=addr;
-          if(fastload_reg_override) a=fastload_reg_override;
+          if(fastio_reg_override>=0) a=fastio_reg_override;
 
           emit_movsbl_indexed(x,a,tl);
         }
@@ -2117,7 +2601,7 @@ void load_assemble(int i,struct regstat *i_regs)
       if(!dummy) {
         int x=0,a=tl;
         if(!c) a=addr;
-        if(fastload_reg_override) a=fastload_reg_override;
+        if(fastio_reg_override>=0) a=fastio_reg_override;
         emit_movswl_indexed(x,a,tl);
       }
       if(jaddr)
@@ -2130,7 +2614,7 @@ void load_assemble(int i,struct regstat *i_regs)
     if(!c||memtarget) {
       if(!dummy) {
         int a=addr;
-        if(fastload_reg_override) a=fastload_reg_override;
+        if(fastio_reg_override>=0) a=fastio_reg_override;
         emit_readword_indexed(0,a,tl);
       }
       if(jaddr)
@@ -2144,7 +2628,7 @@ void load_assemble(int i,struct regstat *i_regs)
       if(!dummy) {
         int x=0,a=tl;
         if(!c) a=addr;
-        if(fastload_reg_override) a=fastload_reg_override;
+        if(fastio_reg_override>=0) a=fastio_reg_override;
 
         emit_movzbl_indexed(x,a,tl);
       }
@@ -2159,7 +2643,7 @@ void load_assemble(int i,struct regstat *i_regs)
       if(!dummy) {
         int x=0,a=tl;
         if(!c) a=addr;
-        if(fastload_reg_override) a=fastload_reg_override;
+        if(fastio_reg_override>=0) a=fastio_reg_override;
         emit_movzwl_indexed(x,a,tl);
       }
       if(jaddr)
@@ -2169,32 +2653,97 @@ void load_assemble(int i,struct regstat *i_regs)
       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
   }
   if (opcode[i]==0x27) { // LWU
-    assert(th>=0);
-    if(!c||memtarget) {
-      if(!dummy) {
-        int a=addr;
-        if(fastload_reg_override) a=fastload_reg_override;
-        emit_readword_indexed(0,a,tl);
-      }
-      if(jaddr)
-        add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
-    }
-    else {
-      inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
-    }
-    emit_zeroreg(th);
+    assert(0);
   }
   if (opcode[i]==0x37) { // LD
     assert(0);
   }
  }
+ if (fastio_reg_override == HOST_TEMPREG)
+   host_tempreg_release();
 }
 
 #ifndef loadlr_assemble
-void loadlr_assemble(int i,struct regstat *i_regs)
+static void loadlr_assemble(int i,struct regstat *i_regs)
 {
-  printf("Need loadlr_assemble for this architecture.\n");
-  exit(1);
+  int s,tl,temp,temp2,addr;
+  int offset;
+  void *jaddr=0;
+  int memtarget=0,c=0;
+  int fastio_reg_override=-1;
+  u_int hr,reglist=0;
+  tl=get_reg(i_regs->regmap,rt1[i]);
+  s=get_reg(i_regs->regmap,rs1[i]);
+  temp=get_reg(i_regs->regmap,-1);
+  temp2=get_reg(i_regs->regmap,FTEMP);
+  addr=get_reg(i_regs->regmap,AGEN1+(i&1));
+  assert(addr<0);
+  offset=imm[i];
+  for(hr=0;hr<HOST_REGS;hr++) {
+    if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
+  }
+  reglist|=1<<temp;
+  if(offset||s<0||c) addr=temp2;
+  else addr=s;
+  if(s>=0) {
+    c=(i_regs->wasconst>>s)&1;
+    if(c) {
+      memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
+    }
+  }
+  if(!c) {
+    emit_shlimm(addr,3,temp);
+    if (opcode[i]==0x22||opcode[i]==0x26) {
+      emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
+    }else{
+      emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
+    }
+    jaddr=emit_fastpath_cmp_jump(i,temp2,&fastio_reg_override);
+  }
+  else {
+    if(ram_offset&&memtarget) {
+      host_tempreg_acquire();
+      emit_addimm(temp2,ram_offset,HOST_TEMPREG);
+      fastio_reg_override=HOST_TEMPREG;
+    }
+    if (opcode[i]==0x22||opcode[i]==0x26) {
+      emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
+    }else{
+      emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
+    }
+  }
+  if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
+    if(!c||memtarget) {
+      int a=temp2;
+      if(fastio_reg_override>=0) a=fastio_reg_override;
+      emit_readword_indexed(0,a,temp2);
+      if(fastio_reg_override==HOST_TEMPREG) host_tempreg_release();
+      if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj[i],reglist);
+    }
+    else
+      inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
+    if(rt1[i]) {
+      assert(tl>=0);
+      emit_andimm(temp,24,temp);
+      if (opcode[i]==0x22) // LWL
+        emit_xorimm(temp,24,temp);
+      host_tempreg_acquire();
+      emit_movimm(-1,HOST_TEMPREG);
+      if (opcode[i]==0x26) {
+        emit_shr(temp2,temp,temp2);
+        emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
+      }else{
+        emit_shl(temp2,temp,temp2);
+        emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
+      }
+      host_tempreg_release();
+      emit_or(temp2,tl,tl);
+    }
+    //emit_storereg(rt1[i],tl); // DEBUG
+  }
+  if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
+    assert(0);
+  }
 }
 #endif
 
@@ -2207,7 +2756,7 @@ void store_assemble(int i,struct regstat *i_regs)
   enum stub_type type;
   int memtarget=0,c=0;
   int agr=AGEN1+(i&1);
-  int faststore_reg_override=0;
+  int fastio_reg_override=-1;
   u_int hr,reglist=0;
   tl=get_reg(i_regs->regmap,rs2[i]);
   s=get_reg(i_regs->regmap,rs1[i]);
@@ -2229,18 +2778,19 @@ void store_assemble(int i,struct regstat *i_regs)
   if(offset||s<0||c) addr=temp;
   else addr=s;
   if(!c) {
-    jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
+    jaddr=emit_fastpath_cmp_jump(i,addr,&fastio_reg_override);
   }
   else if(ram_offset&&memtarget) {
+    host_tempreg_acquire();
     emit_addimm(addr,ram_offset,HOST_TEMPREG);
-    faststore_reg_override=HOST_TEMPREG;
+    fastio_reg_override=HOST_TEMPREG;
   }
 
   if (opcode[i]==0x28) { // SB
     if(!c||memtarget) {
       int x=0,a=temp;
       if(!c) a=addr;
-      if(faststore_reg_override) a=faststore_reg_override;
+      if(fastio_reg_override>=0) a=fastio_reg_override;
       emit_writebyte_indexed(tl,x,a);
     }
     type=STOREB_STUB;
@@ -2249,7 +2799,7 @@ void store_assemble(int i,struct regstat *i_regs)
     if(!c||memtarget) {
       int x=0,a=temp;
       if(!c) a=addr;
-      if(faststore_reg_override) a=faststore_reg_override;
+      if(fastio_reg_override>=0) a=fastio_reg_override;
       emit_writehword_indexed(tl,x,a);
     }
     type=STOREH_STUB;
@@ -2257,7 +2807,7 @@ void store_assemble(int i,struct regstat *i_regs)
   if (opcode[i]==0x2B) { // SW
     if(!c||memtarget) {
       int a=addr;
-      if(faststore_reg_override) a=faststore_reg_override;
+      if(fastio_reg_override>=0) a=fastio_reg_override;
       emit_writeword_indexed(tl,0,a);
     }
     type=STOREW_STUB;
@@ -2266,6 +2816,8 @@ void store_assemble(int i,struct regstat *i_regs)
     assert(0);
     type=STORED_STUB;
   }
+  if(fastio_reg_override==HOST_TEMPREG)
+    host_tempreg_release();
   if(jaddr) {
     // PCSX store handlers don't check invcode again
     reglist|=1<<addr;
@@ -2303,6 +2855,7 @@ void store_assemble(int i,struct regstat *i_regs)
   }
   // basic current block modification detection..
   // not looking back as that should be in mips cache already
+  // (see Spyro2 title->attract mode)
   if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
     SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
     assert(i_regs->regmap==regs[i].regmap); // not delay slot
@@ -2311,12 +2864,14 @@ void store_assemble(int i,struct regstat *i_regs)
       wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
       emit_movimm(start+i*4+4,0);
       emit_writeword(0,&pcaddr);
-      emit_jmp(do_interrupt);
+      emit_addimm(HOST_CCREG,2,HOST_CCREG);
+      emit_call(get_addr_ht);
+      emit_jmpreg(0);
     }
   }
 }
 
-void storelr_assemble(int i,struct regstat *i_regs)
+static void storelr_assemble(int i,struct regstat *i_regs)
 {
   int s,tl;
   int temp;
@@ -2356,7 +2911,8 @@ void storelr_assemble(int i,struct regstat *i_regs)
       emit_jmp(0);
     }
   }
-  emit_addimm_no_flags(ram_offset,temp);
+  if(ram_offset)
+    emit_addimm_no_flags(ram_offset,temp);
 
   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
     assert(0);
@@ -2373,15 +2929,11 @@ void storelr_assemble(int i,struct regstat *i_regs)
   if (opcode[i]==0x2A) { // SWL
     emit_writeword_indexed(tl,0,temp);
   }
-  if (opcode[i]==0x2E) { // SWR
+  else if (opcode[i]==0x2E) { // SWR
     emit_writebyte_indexed(tl,3,temp);
   }
-  if (opcode[i]==0x2C) { // SDL
-    assert(0);
-  }
-  if (opcode[i]==0x2D) { // SDR
+  else
     assert(0);
-  }
   done0=out;
   emit_jmp(0);
   // 1
@@ -2394,16 +2946,10 @@ void storelr_assemble(int i,struct regstat *i_regs)
     emit_writebyte_indexed(tl,1,temp);
     if(rs2[i]) emit_rorimm(tl,8,tl);
   }
-  if (opcode[i]==0x2E) { // SWR
+  else if (opcode[i]==0x2E) { // SWR
     // Write two lsb into two most significant bytes
     emit_writehword_indexed(tl,1,temp);
   }
-  if (opcode[i]==0x2C) { // SDL
-    assert(0);
-  }
-  if (opcode[i]==0x2D) { // SDR
-    assert(0);
-  }
   done1=out;
   emit_jmp(0);
   // 2
@@ -2417,19 +2963,13 @@ void storelr_assemble(int i,struct regstat *i_regs)
     emit_writehword_indexed(tl,-2,temp);
     if(rs2[i]) emit_rorimm(tl,16,tl);
   }
-  if (opcode[i]==0x2E) { // SWR
+  else if (opcode[i]==0x2E) { // SWR
     // Write 3 lsb into three most significant bytes
     emit_writebyte_indexed(tl,-1,temp);
     if(rs2[i]) emit_rorimm(tl,8,tl);
     emit_writehword_indexed(tl,0,temp);
     if(rs2[i]) emit_rorimm(tl,24,tl);
   }
-  if (opcode[i]==0x2C) { // SDL
-    assert(0);
-  }
-  if (opcode[i]==0x2D) { // SDR
-    assert(0);
-  }
   done2=out;
   emit_jmp(0);
   // 3
@@ -2440,25 +2980,13 @@ void storelr_assemble(int i,struct regstat *i_regs)
     emit_writebyte_indexed(tl,-3,temp);
     if(rs2[i]) emit_rorimm(tl,8,tl);
   }
-  if (opcode[i]==0x2E) { // SWR
+  else if (opcode[i]==0x2E) { // SWR
     // Write entire word
     emit_writeword_indexed(tl,-3,temp);
   }
-  if (opcode[i]==0x2C) { // SDL
-    assert(0);
-  }
-  if (opcode[i]==0x2D) { // SDR
-    assert(0);
-  }
   set_jump_target(done0, out);
   set_jump_target(done1, out);
   set_jump_target(done2, out);
-  if (opcode[i]==0x2C) { // SDL
-    assert(0);
-  }
-  if (opcode[i]==0x2D) { // SDR
-    assert(0);
-  }
   if(!c||!memtarget)
     add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj[i],reglist);
   if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
@@ -2480,12 +3008,224 @@ void storelr_assemble(int i,struct regstat *i_regs)
   }
 }
 
-void c1ls_assemble(int i,struct regstat *i_regs)
+static void cop0_assemble(int i,struct regstat *i_regs)
+{
+  if(opcode2[i]==0) // MFC0
+  {
+    signed char t=get_reg(i_regs->regmap,rt1[i]);
+    u_int copr=(source[i]>>11)&0x1f;
+    //assert(t>=0); // Why does this happen?  OOT is weird
+    if(t>=0&&rt1[i]!=0) {
+      emit_readword(&reg_cop0[copr],t);
+    }
+  }
+  else if(opcode2[i]==4) // MTC0
+  {
+    signed char s=get_reg(i_regs->regmap,rs1[i]);
+    char copr=(source[i]>>11)&0x1f;
+    assert(s>=0);
+    wb_register(rs1[i],i_regs->regmap,i_regs->dirty);
+    if(copr==9||copr==11||copr==12||copr==13) {
+      emit_readword(&last_count,HOST_TEMPREG);
+      emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
+      emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
+      emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
+      emit_writeword(HOST_CCREG,&Count);
+    }
+    // What a mess.  The status register (12) can enable interrupts,
+    // so needs a special case to handle a pending interrupt.
+    // The interrupt must be taken immediately, because a subsequent
+    // instruction might disable interrupts again.
+    if(copr==12||copr==13) {
+      if (is_delayslot) {
+        // burn cycles to cause cc_interrupt, which will
+        // reschedule next_interupt. Relies on CCREG from above.
+        assem_debug("MTC0 DS %d\n", copr);
+        emit_writeword(HOST_CCREG,&last_count);
+        emit_movimm(0,HOST_CCREG);
+        emit_storereg(CCREG,HOST_CCREG);
+        emit_loadreg(rs1[i],1);
+        emit_movimm(copr,0);
+        emit_call(pcsx_mtc0_ds);
+        emit_loadreg(rs1[i],s);
+        return;
+      }
+      emit_movimm(start+i*4+4,HOST_TEMPREG);
+      emit_writeword(HOST_TEMPREG,&pcaddr);
+      emit_movimm(0,HOST_TEMPREG);
+      emit_writeword(HOST_TEMPREG,&pending_exception);
+    }
+    //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
+    //else
+    if(s==HOST_CCREG)
+      emit_loadreg(rs1[i],1);
+    else if(s!=1)
+      emit_mov(s,1);
+    emit_movimm(copr,0);
+    emit_call(pcsx_mtc0);
+    if(copr==9||copr==11||copr==12||copr==13) {
+      emit_readword(&Count,HOST_CCREG);
+      emit_readword(&next_interupt,HOST_TEMPREG);
+      emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
+      emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
+      emit_writeword(HOST_TEMPREG,&last_count);
+      emit_storereg(CCREG,HOST_CCREG);
+    }
+    if(copr==12||copr==13) {
+      assert(!is_delayslot);
+      emit_readword(&pending_exception,14);
+      emit_test(14,14);
+      void *jaddr = out;
+      emit_jeq(0);
+      emit_readword(&pcaddr, 0);
+      emit_addimm(HOST_CCREG,2,HOST_CCREG);
+      emit_call(get_addr_ht);
+      emit_jmpreg(0);
+      set_jump_target(jaddr, out);
+    }
+    emit_loadreg(rs1[i],s);
+  }
+  else
+  {
+    assert(opcode2[i]==0x10);
+    //if((source[i]&0x3f)==0x10) // RFE
+    {
+      emit_readword(&Status,0);
+      emit_andimm(0,0x3c,1);
+      emit_andimm(0,~0xf,0);
+      emit_orrshr_imm(1,2,0);
+      emit_writeword(0,&Status);
+    }
+  }
+}
+
+static void cop1_unusable(int i,struct regstat *i_regs)
+{
+  // XXX: should just just do the exception instead
+  //if(!cop1_usable)
+  {
+    void *jaddr=out;
+    emit_jmp(0);
+    add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
+  }
+}
+
+static void cop1_assemble(int i,struct regstat *i_regs)
+{
+  cop1_unusable(i, i_regs);
+}
+
+static void c1ls_assemble(int i,struct regstat *i_regs)
 {
   cop1_unusable(i, i_regs);
 }
 
-void c2ls_assemble(int i,struct regstat *i_regs)
+// FP_STUB
+static void do_cop1stub(int n)
+{
+  literal_pool(256);
+  assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
+  set_jump_target(stubs[n].addr, out);
+  int i=stubs[n].a;
+//  int rs=stubs[n].b;
+  struct regstat *i_regs=(struct regstat *)stubs[n].c;
+  int ds=stubs[n].d;
+  if(!ds) {
+    load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
+    //if(i_regs!=&regs[i]) printf("oops: regs[i]=%x i_regs=%x",(int)&regs[i],(int)i_regs);
+  }
+  //else {printf("fp exception in delay slot\n");}
+  wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
+  if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
+  emit_movimm(start+(i-ds)*4,EAX); // Get PC
+  emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
+  emit_jmp(ds?fp_exception_ds:fp_exception);
+}
+
+static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
+{
+  switch (copr) {
+    case 1:
+    case 3:
+    case 5:
+    case 8:
+    case 9:
+    case 10:
+    case 11:
+      emit_readword(&reg_cop2d[copr],tl);
+      emit_signextend16(tl,tl);
+      emit_writeword(tl,&reg_cop2d[copr]); // hmh
+      break;
+    case 7:
+    case 16:
+    case 17:
+    case 18:
+    case 19:
+      emit_readword(&reg_cop2d[copr],tl);
+      emit_andimm(tl,0xffff,tl);
+      emit_writeword(tl,&reg_cop2d[copr]);
+      break;
+    case 15:
+      emit_readword(&reg_cop2d[14],tl); // SXY2
+      emit_writeword(tl,&reg_cop2d[copr]);
+      break;
+    case 28:
+    case 29:
+      c2op_mfc2_29_assemble(tl,temp);
+      break;
+    default:
+      emit_readword(&reg_cop2d[copr],tl);
+      break;
+  }
+}
+
+static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
+{
+  switch (copr) {
+    case 15:
+      emit_readword(&reg_cop2d[13],temp);  // SXY1
+      emit_writeword(sl,&reg_cop2d[copr]);
+      emit_writeword(temp,&reg_cop2d[12]); // SXY0
+      emit_readword(&reg_cop2d[14],temp);  // SXY2
+      emit_writeword(sl,&reg_cop2d[14]);
+      emit_writeword(temp,&reg_cop2d[13]); // SXY1
+      break;
+    case 28:
+      emit_andimm(sl,0x001f,temp);
+      emit_shlimm(temp,7,temp);
+      emit_writeword(temp,&reg_cop2d[9]);
+      emit_andimm(sl,0x03e0,temp);
+      emit_shlimm(temp,2,temp);
+      emit_writeword(temp,&reg_cop2d[10]);
+      emit_andimm(sl,0x7c00,temp);
+      emit_shrimm(temp,3,temp);
+      emit_writeword(temp,&reg_cop2d[11]);
+      emit_writeword(sl,&reg_cop2d[28]);
+      break;
+    case 30:
+      emit_xorsar_imm(sl,sl,31,temp);
+#if defined(HAVE_ARMV5) || defined(__aarch64__)
+      emit_clz(temp,temp);
+#else
+      emit_movs(temp,HOST_TEMPREG);
+      emit_movimm(0,temp);
+      emit_jeq((int)out+4*4);
+      emit_addpl_imm(temp,1,temp);
+      emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
+      emit_jns((int)out-2*4);
+#endif
+      emit_writeword(sl,&reg_cop2d[30]);
+      emit_writeword(temp,&reg_cop2d[31]);
+      break;
+    case 31:
+      break;
+    default:
+      emit_writeword(sl,&reg_cop2d[copr]);
+      break;
+  }
+}
+
+static void c2ls_assemble(int i,struct regstat *i_regs)
 {
   int s,tl;
   int ar;
@@ -2494,7 +3234,7 @@ void c2ls_assemble(int i,struct regstat *i_regs)
   void *jaddr2=NULL;
   enum stub_type type;
   int agr=AGEN1+(i&1);
-  int fastio_reg_override=0;
+  int fastio_reg_override=-1;
   u_int hr,reglist=0;
   u_int copr=(source[i]>>16)&0x1f;
   s=get_reg(i_regs->regmap,rs1[i]);
@@ -2523,7 +3263,7 @@ void c2ls_assemble(int i,struct regstat *i_regs)
   assert(ar>=0);
 
   if (opcode[i]==0x3a) { // SWC2
-    cop2_get_dreg(copr,tl,HOST_TEMPREG);
+    cop2_get_dreg(copr,tl,-1);
     type=STOREW_STUB;
   }
   else
@@ -2538,12 +3278,13 @@ void c2ls_assemble(int i,struct regstat *i_regs)
       jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
     }
     else if(ram_offset&&memtarget) {
+      host_tempreg_acquire();
       emit_addimm(ar,ram_offset,HOST_TEMPREG);
       fastio_reg_override=HOST_TEMPREG;
     }
     if (opcode[i]==0x32) { // LWC2
       int a=ar;
-      if(fastio_reg_override) a=fastio_reg_override;
+      if(fastio_reg_override>=0) a=fastio_reg_override;
       emit_readword_indexed(0,a,tl);
     }
     if (opcode[i]==0x3a) { // SWC2
@@ -2551,10 +3292,12 @@ void c2ls_assemble(int i,struct regstat *i_regs)
       if(!offset&&!c&&s>=0) emit_mov(s,ar);
       #endif
       int a=ar;
-      if(fastio_reg_override) a=fastio_reg_override;
+      if(fastio_reg_override>=0) a=fastio_reg_override;
       emit_writeword_indexed(tl,0,a);
     }
   }
+  if(fastio_reg_override==HOST_TEMPREG)
+    host_tempreg_release();
   if(jaddr2)
     add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj[i],reglist);
   if(opcode[i]==0x3a) // SWC2
@@ -2575,80 +3318,297 @@ void c2ls_assemble(int i,struct regstat *i_regs)
     #endif
   }
   if (opcode[i]==0x32) { // LWC2
+    host_tempreg_acquire();
     cop2_put_dreg(copr,tl,HOST_TEMPREG);
+    host_tempreg_release();
+  }
+}
+
+static void cop2_assemble(int i,struct regstat *i_regs)
+{
+  u_int copr=(source[i]>>11)&0x1f;
+  signed char temp=get_reg(i_regs->regmap,-1);
+  if (opcode2[i]==0) { // MFC2
+    signed char tl=get_reg(i_regs->regmap,rt1[i]);
+    if(tl>=0&&rt1[i]!=0)
+      cop2_get_dreg(copr,tl,temp);
+  }
+  else if (opcode2[i]==4) { // MTC2
+    signed char sl=get_reg(i_regs->regmap,rs1[i]);
+    cop2_put_dreg(copr,sl,temp);
+  }
+  else if (opcode2[i]==2) // CFC2
+  {
+    signed char tl=get_reg(i_regs->regmap,rt1[i]);
+    if(tl>=0&&rt1[i]!=0)
+      emit_readword(&reg_cop2c[copr],tl);
+  }
+  else if (opcode2[i]==6) // CTC2
+  {
+    signed char sl=get_reg(i_regs->regmap,rs1[i]);
+    switch(copr) {
+      case 4:
+      case 12:
+      case 20:
+      case 26:
+      case 27:
+      case 29:
+      case 30:
+        emit_signextend16(sl,temp);
+        break;
+      case 31:
+        c2op_ctc2_31_assemble(sl,temp);
+        break;
+      default:
+        temp=sl;
+        break;
+    }
+    emit_writeword(temp,&reg_cop2c[copr]);
+    assert(sl>=0);
   }
 }
 
+static void do_unalignedwritestub(int n)
+{
+  assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
+  literal_pool(256);
+  set_jump_target(stubs[n].addr, out);
+
+  int i=stubs[n].a;
+  struct regstat *i_regs=(struct regstat *)stubs[n].c;
+  int addr=stubs[n].b;
+  u_int reglist=stubs[n].e;
+  signed char *i_regmap=i_regs->regmap;
+  int temp2=get_reg(i_regmap,FTEMP);
+  int rt;
+  rt=get_reg(i_regmap,rs2[i]);
+  assert(rt>=0);
+  assert(addr>=0);
+  assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
+  reglist|=(1<<addr);
+  reglist&=~(1<<temp2);
+
+#if 1
+  // don't bother with it and call write handler
+  save_regs(reglist);
+  pass_args(addr,rt);
+  int cc=get_reg(i_regmap,CCREG);
+  if(cc<0)
+    emit_loadreg(CCREG,2);
+  emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n].d+1),2);
+  emit_call((opcode[i]==0x2a?jump_handle_swl:jump_handle_swr));
+  emit_addimm(0,-CLOCK_ADJUST((int)stubs[n].d+1),cc<0?2:cc);
+  if(cc<0)
+    emit_storereg(CCREG,2);
+  restore_regs(reglist);
+  emit_jmp(stubs[n].retaddr); // return address
+#else
+  emit_andimm(addr,0xfffffffc,temp2);
+  emit_writeword(temp2,&address);
+
+  save_regs(reglist);
+  emit_shrimm(addr,16,1);
+  int cc=get_reg(i_regmap,CCREG);
+  if(cc<0) {
+    emit_loadreg(CCREG,2);
+  }
+  emit_movimm((u_int)readmem,0);
+  emit_addimm(cc<0?2:cc,2*stubs[n].d+2,2);
+  emit_call((int)&indirect_jump_indexed);
+  restore_regs(reglist);
+
+  emit_readword(&readmem_dword,temp2);
+  int temp=addr; //hmh
+  emit_shlimm(addr,3,temp);
+  emit_andimm(temp,24,temp);
+  if (opcode[i]==0x2a) // SWL
+    emit_xorimm(temp,24,temp);
+  emit_movimm(-1,HOST_TEMPREG);
+  if (opcode[i]==0x2a) { // SWL
+    emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
+    emit_orrshr(rt,temp,temp2);
+  }else{
+    emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
+    emit_orrshl(rt,temp,temp2);
+  }
+  emit_readword(&address,addr);
+  emit_writeword(temp2,&word);
+  //save_regs(reglist); // don't need to, no state changes
+  emit_shrimm(addr,16,1);
+  emit_movimm((u_int)writemem,0);
+  //emit_call((int)&indirect_jump_indexed);
+  emit_mov(15,14);
+  emit_readword_dualindexedx4(0,1,15);
+  emit_readword(&Count,HOST_TEMPREG);
+  emit_readword(&next_interupt,2);
+  emit_addimm(HOST_TEMPREG,-2*stubs[n].d-2,HOST_TEMPREG);
+  emit_writeword(2,&last_count);
+  emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
+  if(cc<0) {
+    emit_storereg(CCREG,HOST_TEMPREG);
+  }
+  restore_regs(reglist);
+  emit_jmp(stubs[n].retaddr); // return address
+#endif
+}
+
 #ifndef multdiv_assemble
 void multdiv_assemble(int i,struct regstat *i_regs)
 {
   printf("Need multdiv_assemble for this architecture.\n");
-  exit(1);
+  abort();
 }
 #endif
 
-void mov_assemble(int i,struct regstat *i_regs)
+static void mov_assemble(int i,struct regstat *i_regs)
 {
   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
   if(rt1[i]) {
-    signed char sh,sl,th,tl;
-    th=get_reg(i_regs->regmap,rt1[i]|64);
+    signed char sl,tl;
     tl=get_reg(i_regs->regmap,rt1[i]);
     //assert(tl>=0);
     if(tl>=0) {
-      sh=get_reg(i_regs->regmap,rs1[i]|64);
       sl=get_reg(i_regs->regmap,rs1[i]);
       if(sl>=0) emit_mov(sl,tl);
       else emit_loadreg(rs1[i],tl);
-      if(th>=0) {
-        if(sh>=0) emit_mov(sh,th);
-        else emit_loadreg(rs1[i]|64,th);
-      }
     }
   }
 }
 
-void syscall_assemble(int i,struct regstat *i_regs)
+// call interpreter, exception handler, things that change pc/regs/cycles ...
+static void call_c_cpu_handler(int i, const struct regstat *i_regs, u_int pc, void *func)
 {
   signed char ccreg=get_reg(i_regs->regmap,CCREG);
   assert(ccreg==HOST_CCREG);
   assert(!is_delayslot);
   (void)ccreg;
-  emit_movimm(start+i*4,EAX); // Get PC
-  emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
-  emit_jmp(jump_syscall_hle); // XXX
+
+  emit_movimm(pc,3); // Get PC
+  emit_readword(&last_count,2);
+  emit_writeword(3,&psxRegs.pc);
+  emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
+  emit_add(2,HOST_CCREG,2);
+  emit_writeword(2,&psxRegs.cycle);
+  emit_call(func);
+  emit_jmp(jump_to_new_pc);
 }
 
-void hlecall_assemble(int i,struct regstat *i_regs)
+static void syscall_assemble(int i,struct regstat *i_regs)
 {
-  extern void psxNULL();
-  signed char ccreg=get_reg(i_regs->regmap,CCREG);
-  assert(ccreg==HOST_CCREG);
-  assert(!is_delayslot);
-  (void)ccreg;
-  emit_movimm(start+i*4+4,0); // Get PC
+  emit_movimm(0x20,0); // cause code
+  emit_movimm(0,1);    // not in delay slot
+  call_c_cpu_handler(i,i_regs,start+i*4,psxException);
+}
+
+static void hlecall_assemble(int i,struct regstat *i_regs)
+{
+  void *hlefunc = psxNULL;
   uint32_t hleCode = source[i] & 0x03ffffff;
-  if (hleCode >= ARRAY_SIZE(psxHLEt))
-    emit_movimm((uintptr_t)psxNULL,1);
-  else
-    emit_movimm((uintptr_t)psxHLEt[hleCode],1);
-  emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
-  emit_jmp(jump_hlecall);
+  if (hleCode < ARRAY_SIZE(psxHLEt))
+    hlefunc = psxHLEt[hleCode];
+
+  call_c_cpu_handler(i,i_regs,start+i*4+4,hlefunc);
 }
 
-void intcall_assemble(int i,struct regstat *i_regs)
+static void intcall_assemble(int i,struct regstat *i_regs)
 {
-  signed char ccreg=get_reg(i_regs->regmap,CCREG);
-  assert(ccreg==HOST_CCREG);
-  assert(!is_delayslot);
-  (void)ccreg;
-  emit_movimm(start+i*4,0); // Get PC
-  emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
-  emit_jmp(jump_intcall);
+  call_c_cpu_handler(i,i_regs,start+i*4,execI);
+}
+
+static void speculate_mov(int rs,int rt)
+{
+  if(rt!=0) {
+    smrv_strong_next|=1<<rt;
+    smrv[rt]=smrv[rs];
+  }
+}
+
+static void speculate_mov_weak(int rs,int rt)
+{
+  if(rt!=0) {
+    smrv_weak_next|=1<<rt;
+    smrv[rt]=smrv[rs];
+  }
+}
+
+static void speculate_register_values(int i)
+{
+  if(i==0) {
+    memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
+    // gp,sp are likely to stay the same throughout the block
+    smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
+    smrv_weak_next=~smrv_strong_next;
+    //printf(" llr %08x\n", smrv[4]);
+  }
+  smrv_strong=smrv_strong_next;
+  smrv_weak=smrv_weak_next;
+  switch(itype[i]) {
+    case ALU:
+      if     ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
+      else if((smrv_strong>>rs2[i])&1) speculate_mov(rs2[i],rt1[i]);
+      else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
+      else if((smrv_weak>>rs2[i])&1) speculate_mov_weak(rs2[i],rt1[i]);
+      else {
+        smrv_strong_next&=~(1<<rt1[i]);
+        smrv_weak_next&=~(1<<rt1[i]);
+      }
+      break;
+    case SHIFTIMM:
+      smrv_strong_next&=~(1<<rt1[i]);
+      smrv_weak_next&=~(1<<rt1[i]);
+      // fallthrough
+    case IMM16:
+      if(rt1[i]&&is_const(&regs[i],rt1[i])) {
+        int value,hr=get_reg(regs[i].regmap,rt1[i]);
+        if(hr>=0) {
+          if(get_final_value(hr,i,&value))
+               smrv[rt1[i]]=value;
+          else smrv[rt1[i]]=constmap[i][hr];
+          smrv_strong_next|=1<<rt1[i];
+        }
+      }
+      else {
+        if     ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
+        else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
+      }
+      break;
+    case LOAD:
+      if(start<0x2000&&(rt1[i]==26||(smrv[rt1[i]]>>24)==0xa0)) {
+        // special case for BIOS
+        smrv[rt1[i]]=0xa0000000;
+        smrv_strong_next|=1<<rt1[i];
+        break;
+      }
+      // fallthrough
+    case SHIFT:
+    case LOADLR:
+    case MOV:
+      smrv_strong_next&=~(1<<rt1[i]);
+      smrv_weak_next&=~(1<<rt1[i]);
+      break;
+    case COP0:
+    case COP2:
+      if(opcode2[i]==0||opcode2[i]==2) { // MFC/CFC
+        smrv_strong_next&=~(1<<rt1[i]);
+        smrv_weak_next&=~(1<<rt1[i]);
+      }
+      break;
+    case C2LS:
+      if (opcode[i]==0x32) { // LWC2
+        smrv_strong_next&=~(1<<rt1[i]);
+        smrv_weak_next&=~(1<<rt1[i]);
+      }
+      break;
+  }
+#if 0
+  int r=4;
+  printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
+    ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
+#endif
 }
 
-void ds_assemble(int i,struct regstat *i_regs)
+static void ds_assemble(int i,struct regstat *i_regs)
 {
   speculate_register_values(i);
   is_delayslot=1;
@@ -3259,7 +4219,7 @@ static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
 static void drc_dbg_emit_do_cmp(int i)
 {
   extern void do_insn_cmp();
-  extern int cycle;
+  //extern int cycle;
   u_int hr,reglist=0;
 
   for(hr=0;hr<HOST_REGS;hr++)
@@ -3271,6 +4231,7 @@ static void drc_dbg_emit_do_cmp(int i)
   //emit_readword(&cycle,0);
   //emit_addimm(0,2,0);
   //emit_writeword(0,&cycle);
+  (void)get_reg2;
   restore_regs(reglist);
 }
 #else
@@ -3278,7 +4239,7 @@ static void drc_dbg_emit_do_cmp(int i)
 #endif
 
 // Used when a branch jumps into the delay slot of another branch
-void ds_assemble_entry(int i)
+static void ds_assemble_entry(int i)
 {
   int t=(ba[i]-start)>>2;
   if (!instr_addr[t])
@@ -3347,6 +4308,23 @@ void ds_assemble_entry(int i)
   emit_jmp(0);
 }
 
+static void emit_extjump(void *addr, u_int target)
+{
+  emit_extjump2(addr, target, dyna_linker);
+}
+
+static void emit_extjump_ds(void *addr, u_int target)
+{
+  emit_extjump2(addr, target, dyna_linker_ds);
+}
+
+// Load 2 immediates optimizing for small code size
+static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
+{
+  emit_movimm(imm1,rt1);
+  emit_movimm_from(imm1,rt1,imm2,rt2);
+}
+
 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
 {
   int count;
@@ -3402,7 +4380,7 @@ void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
 static void do_ccstub(int n)
 {
   literal_pool(256);
-  assem_debug("do_ccstub %x\n",start+stubs[n].b*4);
+  assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
   set_jump_target(stubs[n].addr, out);
   int i=stubs[n].b;
   if(stubs[n].d==NULLDS) {
@@ -3575,7 +4553,7 @@ static void do_ccstub(int n)
       }
       emit_writeword(r,&pcaddr);
     }
-    else {SysPrintf("Unknown branch type in do_ccstub\n");exit(1);}
+    else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
   }
   // Update cycle count
   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
@@ -3601,7 +4579,10 @@ static void do_ccstub(int n)
   }else{
     load_all_regs(branch_regs[i].regmap);
   }
-  emit_jmp(stubs[n].retaddr);
+  if (stubs[n].retaddr)
+    emit_jmp(stubs[n].retaddr);
+  else
+    do_jump_vaddr(stubs[n].e);
 }
 
 static void add_to_linker(void *addr, u_int target, int ext)
@@ -3648,7 +4629,7 @@ static void ujump_assemble_write_ra(int i)
   }
 }
 
-void ujump_assemble(int i,struct regstat *i_regs)
+static void ujump_assemble(int i,struct regstat *i_regs)
 {
   int ra_done=0;
   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
@@ -3718,7 +4699,7 @@ static void rjump_assemble_write_ra(int i)
   #endif
 }
 
-void rjump_assemble(int i,struct regstat *i_regs)
+static void rjump_assemble(int i,struct regstat *i_regs)
 {
   int temp;
   int rs,cc;
@@ -3794,7 +4775,7 @@ void rjump_assemble(int i,struct regstat *i_regs)
   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
   //assert(adj==0);
   emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
-  add_stub(CC_STUB,out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
+  add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
   if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
     // special case for RFE
     emit_jmp(0);
@@ -3808,14 +4789,14 @@ void rjump_assemble(int i,struct regstat *i_regs)
   else
   #endif
   {
-    emit_jmp(jump_vaddr_reg[rs]);
+    do_jump_vaddr(rs);
   }
   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
   #endif
 }
 
-void cjump_assemble(int i,struct regstat *i_regs)
+static void cjump_assemble(int i,struct regstat *i_regs)
 {
   signed char *i_regmap=i_regs->regmap;
   int cc;
@@ -3831,6 +4812,9 @@ void cjump_assemble(int i,struct regstat *i_regs)
   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
   if(i>(ba[i]-start)>>2) invert=1;
   #endif
+  #ifdef __aarch64__
+  invert=1; // because of near cond. branches
+  #endif
 
   if(ooo[i]) {
     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
@@ -3917,7 +4901,7 @@ void cjump_assemble(int i,struct regstat *i_regs)
         else emit_test(s1l,s1l);
         if(invert){
           nottaken=out;
-          emit_jne((void *)1l);
+          emit_jne(DJT_1);
         }else{
           add_to_linker(out,ba[i],internal);
           emit_jeq(0);
@@ -3929,7 +4913,7 @@ void cjump_assemble(int i,struct regstat *i_regs)
         else emit_test(s1l,s1l);
         if(invert){
           nottaken=out;
-          emit_jeq(1);
+          emit_jeq(DJT_1);
         }else{
           add_to_linker(out,ba[i],internal);
           emit_jne(0);
@@ -3940,7 +4924,7 @@ void cjump_assemble(int i,struct regstat *i_regs)
         emit_cmpimm(s1l,1);
         if(invert){
           nottaken=out;
-          emit_jge(1);
+          emit_jge(DJT_1);
         }else{
           add_to_linker(out,ba[i],internal);
           emit_jl(0);
@@ -3951,7 +4935,7 @@ void cjump_assemble(int i,struct regstat *i_regs)
         emit_cmpimm(s1l,1);
         if(invert){
           nottaken=out;
-          emit_jl(1);
+          emit_jl(DJT_1);
         }else{
           add_to_linker(out,ba[i],internal);
           emit_jge(0);
@@ -4011,26 +4995,26 @@ void cjump_assemble(int i,struct regstat *i_regs)
         if(s2l>=0) emit_cmp(s1l,s2l);
         else emit_test(s1l,s1l);
         nottaken=out;
-        emit_jne((void *)2l);
+        emit_jne(DJT_2);
       }
       if((opcode[i]&0x2f)==5) // BNE
       {
         if(s2l>=0) emit_cmp(s1l,s2l);
         else emit_test(s1l,s1l);
         nottaken=out;
-        emit_jeq(2);
+        emit_jeq(DJT_2);
       }
       if((opcode[i]&0x2f)==6) // BLEZ
       {
         emit_cmpimm(s1l,1);
         nottaken=out;
-        emit_jge(2);
+        emit_jge(DJT_2);
       }
       if((opcode[i]&0x2f)==7) // BGTZ
       {
         emit_cmpimm(s1l,1);
         nottaken=out;
-        emit_jl(2);
+        emit_jl(DJT_2);
       }
     } // if(!unconditional)
     int adj;
@@ -4104,7 +5088,7 @@ void cjump_assemble(int i,struct regstat *i_regs)
   }
 }
 
-void sjump_assemble(int i,struct regstat *i_regs)
+static void sjump_assemble(int i,struct regstat *i_regs)
 {
   signed char *i_regmap=i_regs->regmap;
   int cc;
@@ -4120,6 +5104,9 @@ void sjump_assemble(int i,struct regstat *i_regs)
   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
   if(i>(ba[i]-start)>>2) invert=1;
   #endif
+  #ifdef __aarch64__
+  invert=1; // because of near cond. branches
+  #endif
 
   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
@@ -4210,7 +5197,7 @@ void sjump_assemble(int i,struct regstat *i_regs)
           emit_test(s1l,s1l);
           if(invert){
             nottaken=out;
-            emit_jns(1);
+            emit_jns(DJT_1);
           }else{
             add_to_linker(out,ba[i],internal);
             emit_js(0);
@@ -4221,7 +5208,7 @@ void sjump_assemble(int i,struct regstat *i_regs)
           emit_test(s1l,s1l);
           if(invert){
             nottaken=out;
-            emit_js(1);
+            emit_js(DJT_1);
           }else{
             add_to_linker(out,ba[i],internal);
             emit_jns(0);
@@ -4290,13 +5277,13 @@ void sjump_assemble(int i,struct regstat *i_regs)
         {
           emit_test(s1l,s1l);
           nottaken=out;
-          emit_jns(1);
+          emit_jns(DJT_1);
         }
         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
         {
           emit_test(s1l,s1l);
           nottaken=out;
-          emit_js(1);
+          emit_js(DJT_1);
         }
     } // if(!unconditional)
     int adj;
@@ -4660,15 +5647,17 @@ static void pagespan_ds()
   assert(btaddr!=HOST_CCREG);
   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
 #ifdef HOST_IMM8
+  host_tempreg_acquire();
   emit_movimm(start+4,HOST_TEMPREG);
   emit_cmp(btaddr,HOST_TEMPREG);
+  host_tempreg_release();
 #else
   emit_cmpimm(btaddr,start+4);
 #endif
   void *branch = out;
   emit_jeq(0);
   store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
-  emit_jmp(jump_vaddr_reg[btaddr]);
+  do_jump_vaddr(btaddr);
   set_jump_target(branch, out);
   store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
   load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
@@ -5392,25 +6381,38 @@ static void disassemble_inst(int i) {}
 
 #define DRC_TEST_VAL 0x74657374
 
-static int new_dynarec_test(void)
+static void new_dynarec_test(void)
 {
-  int (*testfunc)(void) = (void *)out;
+  int (*testfunc)(void);
   void *beginning;
-  int ret;
+  int ret[2];
+  size_t i;
 
-  beginning = start_block();
-  emit_movimm(DRC_TEST_VAL,0); // test
-  emit_jmpreg(14);
-  literal_pool(0);
-  end_block(beginning);
-  SysPrintf("testing if we can run recompiled code..\n");
-  ret = testfunc();
-  if (ret == DRC_TEST_VAL)
+  // check structure linkage
+  if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
+  {
+    SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
+  }
+
+  SysPrintf("testing if we can run recompiled code...\n");
+  ((volatile u_int *)out)[0]++; // make cache dirty
+
+  for (i = 0; i < ARRAY_SIZE(ret); i++) {
+    out = translation_cache;
+    beginning = start_block();
+    emit_movimm(DRC_TEST_VAL + i, 0); // test
+    emit_ret();
+    literal_pool(0);
+    end_block(beginning);
+    testfunc = beginning;
+    ret[i] = testfunc();
+  }
+
+  if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
     SysPrintf("test passed.\n");
   else
-    SysPrintf("test failed: %08x\n", ret);
+    SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
   out = translation_cache;
-  return ret == DRC_TEST_VAL;
 }
 
 // clear the state completely, instead of just marking
@@ -5633,7 +6635,7 @@ void new_dynarec_load_blocks(const void *save, int size)
   memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
 }
 
-int new_recompile_block(int addr)
+int new_recompile_block(u_int addr)
 {
   u_int pagelimit = 0;
   u_int state_rflags = 0;
@@ -5651,7 +6653,7 @@ int new_recompile_block(int addr)
   }
 
   start = (u_int)addr&~3;
-  //assert(((u_int)addr&1)==0);
+  //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
   new_dynarec_did_compile=1;
   if (Config.HLE && start == 0x80001000) // hlecall
   {
@@ -5672,7 +6674,7 @@ int new_recompile_block(int addr)
   source = get_source_start(start, &pagelimit);
   if (source == NULL) {
     SysPrintf("Compile at bogus memory address: %08x\n", addr);
-    exit(1);
+    abort();
   }
 
   /* Pass 1: disassemble */
@@ -5854,7 +6856,7 @@ int new_recompile_block(int addr)
 #endif
       case 0x12: strcpy(insn[i],"COP2"); type=NI;
         op2=(source[i]>>21)&0x1f;
-        //if (op2 & 0x10) {
+        //if (op2 & 0x10)
         if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
           if (gte_handlers[source[i]&0x3f]!=NULL) {
             if (gte_regnames[source[i]&0x3f]!=NULL)
@@ -5883,8 +6885,6 @@ int new_recompile_block(int addr)
     opcode2[i]=op2;
     /* Get registers/immediates */
     lt1[i]=0;
-    us1[i]=0;
-    us2[i]=0;
     dep1[i]=0;
     dep2[i]=0;
     gte_rs[i]=gte_rt[i]=0;
@@ -5903,7 +6903,6 @@ int new_recompile_block(int addr)
         rt1[i]=0;
         rt2[i]=0;
         imm[i]=(short)source[i];
-        if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
         break;
       case LOADLR:
         // LWL/LWR only load part of the register,
@@ -5913,7 +6912,6 @@ int new_recompile_block(int addr)
         rt1[i]=(source[i]>>16)&0x1f;
         rt2[i]=0;
         imm[i]=(short)source[i];
-        if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
         if(op==0x26) dep1[i]=rt1[i]; // LWR
         break;
       case IMM16:
@@ -5927,8 +6925,6 @@ int new_recompile_block(int addr)
         }else{
           imm[i]=(short)source[i];
         }
-        if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
-        if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
         break;
       case UJUMP:
@@ -5961,8 +6957,6 @@ int new_recompile_block(int addr)
         if(op&2) { // BGTZ/BLEZ
           rs2[i]=0;
         }
-        us1[i]=rs1[i];
-        us2[i]=rs2[i];
         likely[i]=op>>4;
         break;
       case SJUMP:
@@ -5970,7 +6964,6 @@ int new_recompile_block(int addr)
         rs2[i]=CCREG;
         rt1[i]=0;
         rt2[i]=0;
-        us1[i]=rs1[i];
         if(op2&0x10) { // BxxAL
           rt1[i]=31;
           // NOTE: If the branch is not taken, r31 is still overwritten
@@ -5982,10 +6975,7 @@ int new_recompile_block(int addr)
         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
         rt1[i]=(source[i]>>11)&0x1f; // destination
         rt2[i]=0;
-        if(op2==0x2a||op2==0x2b) { // SLT/SLTU
-          us1[i]=rs1[i];us2[i]=rs2[i];
-        }
-        else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
+        if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
           dep1[i]=rs1[i];dep2[i]=rs2[i];
         }
         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
@@ -5997,9 +6987,6 @@ int new_recompile_block(int addr)
         rs2[i]=(source[i]>>16)&0x1f; // divisor
         rt1[i]=HIREG;
         rt2[i]=LOREG;
-        if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
-          us1[i]=rs1[i];us2[i]=rs2[i];
-        }
         break;
       case MOV:
         rs1[i]=0;
@@ -6019,8 +7006,6 @@ int new_recompile_block(int addr)
         rs2[i]=(source[i]>>21)&0x1f; // shift amount
         rt1[i]=(source[i]>>11)&0x1f; // destination
         rt2[i]=0;
-        // DSLLV/DSRLV/DSRAV are 64-bit
-        if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
         break;
       case SHIFTIMM:
         rs1[i]=(source[i]>>16)&0x1f;
@@ -6030,8 +7015,6 @@ int new_recompile_block(int addr)
         imm[i]=(source[i]>>6)&0x1f;
         // DSxx32 instructions
         if(op2>=0x3c) imm[i]|=0x20;
-        // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
-        if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
         break;
       case COP0:
         rs1[i]=0;
@@ -6050,7 +7033,6 @@ int new_recompile_block(int addr)
         rt2[i]=0;
         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
-        if(op2==5) us1[i]=rs1[i]; // DMTC1
         rs2[i]=CSREG;
         break;
       case COP2:
@@ -6243,23 +7225,6 @@ int new_recompile_block(int addr)
       current.isconst=0;
       current.waswritten=0;
     }
-    if(i>1)
-    {
-      if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
-      {
-        if(rs1[i-2]==0||rs2[i-2]==0)
-        {
-          if(rs1[i-2]) {
-            int hr=get_reg(current.regmap,rs1[i-2]|64);
-            if(hr>=0) current.regmap[hr]=-1;
-          }
-          if(rs2[i-2]) {
-            int hr=get_reg(current.regmap,rs2[i-2]|64);
-            if(hr>=0) current.regmap[hr]=-1;
-          }
-        }
-      }
-    }
 
     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
     regs[i].wasconst=current.isconst;
@@ -6277,7 +7242,7 @@ int new_recompile_block(int addr)
         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
         current.u|=1;
-      } else { SysPrintf("oops, branch at end of block with no delay slot\n");exit(1); }
+      } else { SysPrintf("oops, branch at end of block with no delay slot\n");abort(); }
     }
     is_ds[i]=ds;
     if(ds) {
@@ -6311,7 +7276,7 @@ int new_recompile_block(int addr)
           }
           else
           {
-            if(r<64){
+              assert(r < 64);
               if((current.u>>r)&1) {
                 regs[i].regmap_entry[hr]=-1;
                 regs[i].regmap[hr]=-1;
@@ -6319,10 +7284,6 @@ int new_recompile_block(int addr)
                 //current.regmap[hr]=-1;
               }else
                 regs[i].regmap_entry[hr]=r;
-            }
-            else {
-              assert(0);
-            }
           }
         } else {
           // First instruction expects CCREG to be allocated
@@ -6596,7 +7557,8 @@ int new_recompile_block(int addr)
               regs[i].regmap_entry[hr]=0;
             }
             else
-            if(r<64){
+            {
+              assert(r<64);
               if((current.u>>r)&1) {
                 regs[i].regmap_entry[hr]=-1;
                 //regs[i].regmap[hr]=-1;
@@ -6604,9 +7566,6 @@ int new_recompile_block(int addr)
               }else
                 regs[i].regmap_entry[hr]=r;
             }
-            else {
-              assert(0);
-            }
           }
         } else {
           // Branches expect CCREG to be allocated at the target
@@ -6931,12 +7890,8 @@ int new_recompile_block(int addr)
           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
         }
-        if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
-        if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
-        if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
-        if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
@@ -6973,12 +7928,8 @@ int new_recompile_block(int addr)
       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
       // Source registers are needed
-      if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
-      if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
-      if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
-      if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
@@ -6990,11 +7941,11 @@ int new_recompile_block(int addr)
       // But do so if this is a branch target, otherwise we
       // might have to load the register before the branch.
       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
-        if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
+        if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
         }
-        if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
+        if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
         }
@@ -7031,12 +7982,7 @@ int new_recompile_block(int addr)
         }
         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
         {
-          int d1=0,d2=0,map=0,temp=0;
-          if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
-          {
-            d1=dep1[i+1];
-            d2=dep2[i+1];
-          }
+          int map=0,temp=0;
           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
             map=INVCP;
@@ -7047,8 +7993,6 @@ int new_recompile_block(int addr)
           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
-             (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
-             (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
@@ -7060,8 +8004,6 @@ int new_recompile_block(int addr)
             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
-               (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
-               (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
@@ -7085,12 +8027,7 @@ int new_recompile_block(int addr)
           // Non-branch
           if(i>0)
           {
-            int d1=0,d2=0,map=-1,temp=-1;
-            if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
-            {
-              d1=dep1[i];
-              d2=dep2[i];
-            }
+            int map=-1,temp=-1;
             if(itype[i]==STORE || itype[i]==STORELR ||
                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
               map=INVCP;
@@ -7099,15 +8036,13 @@ int new_recompile_block(int addr)
                itype[i]==C1LS || itype[i]==C2LS)
               temp=FTEMP;
             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
-               (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
-               (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
             {
               if(i<slen-1&&!is_ds[i]) {
                 assert(regs[i].regmap[hr]<64);
-                if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
+                if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
                 {
                   SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
@@ -7122,8 +8057,8 @@ int new_recompile_block(int addr)
             }
           }
         }
-      }
-    }
+      } // if needed
+    } // for hr
   }
 
   /* Pass 5 - Pre-allocate registers */
@@ -7150,12 +8085,7 @@ int new_recompile_block(int addr)
         if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
         for(hr=0;hr<HOST_REGS;hr++)
         {
-          if(regs[i].regmap[hr]>64) {
-            if(!((regs[i].dirty>>hr)&1))
-              f_regmap[hr]=regs[i].regmap[hr];
-            else f_regmap[hr]=-1;
-          }
-          else if(regs[i].regmap[hr]>=0) {
+          if(regs[i].regmap[hr]>=0) {
             if(f_regmap[hr]!=regs[i].regmap[hr]) {
               // dealloc old register
               int n;
@@ -7167,12 +8097,7 @@ int new_recompile_block(int addr)
               f_regmap[hr]=regs[i].regmap[hr];
             }
           }
-          if(branch_regs[i].regmap[hr]>64) {
-            if(!((branch_regs[i].dirty>>hr)&1))
-              f_regmap[hr]=branch_regs[i].regmap[hr];
-            else f_regmap[hr]=-1;
-          }
-          else if(branch_regs[i].regmap[hr]>=0) {
+          if(branch_regs[i].regmap[hr]>=0) {
             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
               // dealloc old register
               int n;
@@ -7355,11 +8280,7 @@ int new_recompile_block(int addr)
       for(hr=0;hr<HOST_REGS;hr++)
       {
         if(hr!=EXCLUDE_REG) {
-          if(regs[i].regmap[hr]>64) {
-            if(!((regs[i].dirty>>hr)&1))
-              f_regmap[hr]=regs[i].regmap[hr];
-          }
-          else if(regs[i].regmap[hr]>=0) {
+          if(regs[i].regmap[hr]>=0) {
             if(f_regmap[hr]!=regs[i].regmap[hr]) {
               // dealloc old register
               int n;
@@ -7637,6 +8558,7 @@ int new_recompile_block(int addr)
     #ifdef __arm__
     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
     #endif
+    #if defined(__i386__) || defined(__x86_64__)
     printf("needs: ");
     if(needed_reg[i]&1) printf("eax ");
     if((needed_reg[i]>>1)&1) printf("ecx ");
@@ -7646,7 +8568,6 @@ int new_recompile_block(int addr)
     if((needed_reg[i]>>6)&1) printf("esi ");
     if((needed_reg[i]>>7)&1) printf("edi ");
     printf("\n");
-    #if defined(__i386__) || defined(__x86_64__)
     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
     printf("dirty: ");
     if(regs[i].wasdirty&1) printf("eax ");
@@ -7713,7 +8634,7 @@ int new_recompile_block(int addr)
       if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
       if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
       #endif
-      #ifdef __arm__
+      #if defined(__arm__) || defined(__aarch64__)
       int r;
       for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
         if ((regs[i].isconst >> r) & 1)
@@ -7763,7 +8684,7 @@ int new_recompile_block(int addr)
   void *instr_addr0_override = NULL;
 
   if (start == 0x80030000) {
-    // nasty hack for fastbios thing
+    // nasty hack for the fastbios thing
     // override block entry to this code
     instr_addr0_override = out;
     emit_movimm(start,0);
@@ -7773,7 +8694,12 @@ int new_recompile_block(int addr)
     emit_writeword(0,&pcaddr);
     emit_writeword(0,&address);
     emit_cmp(0,1);
+    #ifdef __aarch64__
+    emit_jeq(out + 4*2);
+    emit_jmp(new_dyna_leave);
+    #else
     emit_jne(new_dyna_leave);
+    #endif
   }
   for(i=0;i<slen;i++)
   {
@@ -8102,7 +9028,7 @@ int new_recompile_block(int addr)
         break;
       case 3:
         // Clear jump_out
-        #ifdef __arm__
+        #if defined(__arm__) || defined(__aarch64__)
         if((expirep&2047)==0)
           do_clear_cache();
         #endif