X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fnew_dynarec.c;h=9ce1f069a92bdd5766adb1db2e175aedf489c746;hp=8cf8dfbc0f19f53936cd1f2bab606e068abade09;hb=3968e69e7fa8f9cb0d44ac79477d5929b9649271;hpb=956f312925948e46da9c3596efadc4babc666a4d diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index 8cf8dfbc..9ce1f069 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -21,10 +21,29 @@ #include #include //include for uint64_t #include +#include #include +#ifdef __MACH__ +#include +#endif +#ifdef _3DS +#include <3ds_utils.h> +#endif +#ifdef VITA +#include +static int sceBlock; +#endif +#include "new_dynarec_config.h" +#include "../psxhle.h" +#include "../psxinterpreter.h" #include "emu_if.h" //emulator interface +#define noinline __attribute__((noinline,noclone)) +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) +#endif + //#define DISASM //#define assem_debug printf //#define inv_debug printf @@ -40,51 +59,99 @@ #ifdef __arm__ #include "assem_arm.h" #endif +#ifdef __aarch64__ +#include "assem_arm64.h" +#endif #define MAXBLOCK 4096 #define MAX_OUTPUT_BLOCK_SIZE 262144 +// stubs +enum stub_type { + CC_STUB = 1, + FP_STUB = 2, + LOADB_STUB = 3, + LOADH_STUB = 4, + LOADW_STUB = 5, + LOADD_STUB = 6, + LOADBU_STUB = 7, + LOADHU_STUB = 8, + STOREB_STUB = 9, + STOREH_STUB = 10, + STOREW_STUB = 11, + STORED_STUB = 12, + STORELR_STUB = 13, + INVCODE_STUB = 14, +}; + struct regstat { signed char regmap_entry[HOST_REGS]; signed char regmap[HOST_REGS]; - uint64_t was32; - uint64_t is32; uint64_t wasdirty; uint64_t dirty; uint64_t u; - uint64_t uu; u_int wasconst; u_int isconst; u_int loadedconst; // host regs that have constants loaded u_int waswritten; // MIPS regs that were used as store base before }; +// note: asm depends on this layout struct ll_entry { u_int vaddr; - u_int reg32; + u_int reg_sv_flags; void *addr; struct ll_entry *next; }; - u_int start; - u_int *source; - u_int pagelimit; - char insn[MAXBLOCK][10]; - u_char itype[MAXBLOCK]; - u_char opcode[MAXBLOCK]; - u_char opcode2[MAXBLOCK]; - u_char bt[MAXBLOCK]; - u_char rs1[MAXBLOCK]; - u_char rs2[MAXBLOCK]; - u_char rt1[MAXBLOCK]; - u_char rt2[MAXBLOCK]; - u_char us1[MAXBLOCK]; - u_char us2[MAXBLOCK]; - u_char dep1[MAXBLOCK]; - u_char dep2[MAXBLOCK]; - u_char lt1[MAXBLOCK]; +struct ht_entry +{ + u_int vaddr[2]; + void *tcaddr[2]; +}; + +struct code_stub +{ + enum stub_type type; + void *addr; + void *retaddr; + u_int a; + uintptr_t b; + uintptr_t c; + u_int d; + u_int e; +}; + +struct link_entry +{ + void *addr; + u_int target; + u_int ext; +}; + + // used by asm: + u_char *out; + struct ht_entry hash_table[65536] __attribute__((aligned(16))); + struct ll_entry *jump_in[4096] __attribute__((aligned(16))); + struct ll_entry *jump_dirty[4096]; + + static struct ll_entry *jump_out[4096]; + static u_int start; + static u_int *source; + static char insn[MAXBLOCK][10]; + static u_char itype[MAXBLOCK]; + static u_char opcode[MAXBLOCK]; + static u_char opcode2[MAXBLOCK]; + static u_char bt[MAXBLOCK]; + static u_char rs1[MAXBLOCK]; + static u_char rs2[MAXBLOCK]; + static u_char rt1[MAXBLOCK]; + static u_char rt2[MAXBLOCK]; + static u_char dep1[MAXBLOCK]; + static u_char dep2[MAXBLOCK]; + static u_char lt1[MAXBLOCK]; static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs static uint64_t gte_rt[MAXBLOCK]; static uint64_t gte_unneeded[MAXBLOCK]; @@ -93,79 +160,75 @@ struct ll_entry static u_int smrv_weak; // same, but somewhat less likely static u_int smrv_strong_next; // same, but after current insn executes static u_int smrv_weak_next; - int imm[MAXBLOCK]; - u_int ba[MAXBLOCK]; - char likely[MAXBLOCK]; - char is_ds[MAXBLOCK]; - char ooo[MAXBLOCK]; - uint64_t unneeded_reg[MAXBLOCK]; - uint64_t unneeded_reg_upper[MAXBLOCK]; - uint64_t branch_unneeded_reg[MAXBLOCK]; - uint64_t branch_unneeded_reg_upper[MAXBLOCK]; - uint64_t p32[MAXBLOCK]; - uint64_t pr32[MAXBLOCK]; - signed char regmap_pre[MAXBLOCK][HOST_REGS]; + static int imm[MAXBLOCK]; + static u_int ba[MAXBLOCK]; + static char likely[MAXBLOCK]; + static char is_ds[MAXBLOCK]; + static char ooo[MAXBLOCK]; + static uint64_t unneeded_reg[MAXBLOCK]; + static uint64_t branch_unneeded_reg[MAXBLOCK]; + static signed char regmap_pre[MAXBLOCK][HOST_REGS]; // pre-instruction i? static uint64_t current_constmap[HOST_REGS]; static uint64_t constmap[MAXBLOCK][HOST_REGS]; static struct regstat regs[MAXBLOCK]; static struct regstat branch_regs[MAXBLOCK]; - signed char minimum_free_regs[MAXBLOCK]; - u_int needed_reg[MAXBLOCK]; - uint64_t requires_32bit[MAXBLOCK]; - u_int wont_dirty[MAXBLOCK]; - u_int will_dirty[MAXBLOCK]; - int ccadj[MAXBLOCK]; - int slen; - u_int instr_addr[MAXBLOCK]; - u_int link_addr[MAXBLOCK][3]; - int linkcount; - u_int stubs[MAXBLOCK*3][8]; - int stubcount; - u_int literals[1024][2]; - int literalcount; - int is_delayslot; - int cop1_usable; - u_char *out; - struct ll_entry *jump_in[4096]; - struct ll_entry *jump_out[4096]; - struct ll_entry *jump_dirty[4096]; - u_int hash_table[65536][4] __attribute__((aligned(16))); - char shadow[1048576] __attribute__((aligned(16))); - void *copy; - int expirep; -#ifndef PCSX - u_int using_tlb; + static signed char minimum_free_regs[MAXBLOCK]; + static u_int needed_reg[MAXBLOCK]; + static u_int wont_dirty[MAXBLOCK]; + static u_int will_dirty[MAXBLOCK]; + static int ccadj[MAXBLOCK]; + static int slen; + static void *instr_addr[MAXBLOCK]; + static struct link_entry link_addr[MAXBLOCK]; + static int linkcount; + static struct code_stub stubs[MAXBLOCK*3]; + static int stubcount; + static u_int literals[1024][2]; + static int literalcount; + static int is_delayslot; + static char shadow[1048576] __attribute__((aligned(16))); + static void *copy; + static int expirep; + static u_int stop_after_jal; +#ifndef RAM_FIXED + static uintptr_t ram_offset; #else - static const u_int using_tlb=0; + static const uintptr_t ram_offset=0; #endif - int new_dynarec_did_compile; + int new_dynarec_hacks; - u_int stop_after_jal; + int new_dynarec_did_compile; + + extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 + extern int last_count; // last absolute target, often = next_interupt + extern int pcaddr; + extern int pending_exception; + extern int branch_target; + extern uintptr_t mini_ht[32][2]; extern u_char restore_candidate[512]; - extern int cycle_count; /* registers that may be allocated */ /* 1-31 gpr */ -#define HIREG 32 // hi -#define LOREG 33 // lo -#define FSREG 34 // FPU status (FCSR) +#define LOREG 32 // lo +#define HIREG 33 // hi +//#define FSREG 34 // FPU status (FCSR) #define CSREG 35 // Coprocessor status #define CCREG 36 // Cycle count #define INVCP 37 // Pointer to invalid_code -#define MMREG 38 // Pointer to memory_map -#define ROREG 39 // ram offset (if rdram!=0x80000000) +//#define MMREG 38 // Pointer to memory_map +//#define ROREG 39 // ram offset (if rdram!=0x80000000) #define TEMPREG 40 #define FTEMP 40 // FPU temporary register #define PTEMP 41 // Prefetch temporary register -#define TLREG 42 // TLB mapping offset +//#define TLREG 42 // TLB mapping offset #define RHASH 43 // Return address hash #define RHTBL 44 // Return address hash table address #define RTEMP 45 // JR/JALR address register #define MAXREG 45 #define AGEN1 46 // Address generation temporary register -#define AGEN2 47 // Address generation temporary register -#define MGEN1 48 // Maptable address generation temporary register -#define MGEN2 49 // Maptable address generation temporary register +//#define AGEN2 47 // Address generation temporary register +//#define MGEN1 48 // Maptable address generation temporary register +//#define MGEN2 49 // Maptable address generation temporary register #define BTREG 50 // Branch target temporary register /* instruction types */ @@ -174,7 +237,7 @@ struct ll_entry #define STORE 2 // Store #define LOADLR 3 // Unaligned load #define STORELR 4 // Unaligned store -#define MOV 5 // Move +#define MOV 5 // Move #define ALU 6 // Arithmetic/logic #define MULTDIV 7 // Multiply/divide #define SHIFT 8 // Shift by register @@ -187,10 +250,10 @@ struct ll_entry #define COP0 15 // Coprocessor 0 #define COP1 16 // Coprocessor 1 #define C1LS 17 // Coprocessor 1 load/store -#define FJUMP 18 // Conditional branch (floating point) -#define FLOAT 19 // Floating point unit -#define FCONV 20 // Convert integer to float -#define FCOMP 21 // Floating point compare (sets FSREG) +//#define FJUMP 18 // Conditional branch (floating point) +//#define FLOAT 19 // Floating point unit +//#define FCONV 20 // Convert integer to float +//#define FCOMP 21 // Floating point compare (sets FSREG) #define SYSCALL 22// SYSCALL #define OTHER 23 // Other #define SPAN 24 // Branch/delay slot spans 2 pages @@ -201,79 +264,117 @@ struct ll_entry #define C2OP 29 // Coprocessor 2 operation #define INTCALL 30// Call interpreter to handle rare corner cases - /* stubs */ -#define CC_STUB 1 -#define FP_STUB 2 -#define LOADB_STUB 3 -#define LOADH_STUB 4 -#define LOADW_STUB 5 -#define LOADD_STUB 6 -#define LOADBU_STUB 7 -#define LOADHU_STUB 8 -#define STOREB_STUB 9 -#define STOREH_STUB 10 -#define STOREW_STUB 11 -#define STORED_STUB 12 -#define STORELR_STUB 13 -#define INVCODE_STUB 14 - /* branch codes */ #define TAKEN 1 #define NOTTAKEN 2 #define NULLDS 3 +#define DJT_1 (void *)1l // no function, just a label in assem_debug log +#define DJT_2 (void *)2l + // asm linkage -int new_recompile_block(int addr); +int new_recompile_block(u_int addr); void *get_addr_ht(u_int vaddr); void invalidate_block(u_int block); void invalidate_addr(u_int addr); void remove_hash(int vaddr); -void jump_vaddr(); void dyna_linker(); void dyna_linker_ds(); void verify_code(); -void verify_code_vm(); void verify_code_ds(); void cc_interrupt(); void fp_exception(); void fp_exception_ds(); -void jump_syscall(); -void jump_syscall_hle(); -void jump_eret(); -void jump_hlecall(); -void jump_intcall(); +void jump_to_new_pc(); void new_dyna_leave(); -// TLB -void TLBWI_new(); -void TLBWR_new(); -void read_nomem_new(); -void read_nomemb_new(); -void read_nomemh_new(); -void read_nomemd_new(); -void write_nomem_new(); -void write_nomemb_new(); -void write_nomemh_new(); -void write_nomemd_new(); -void write_rdram_new(); -void write_rdramb_new(); -void write_rdramh_new(); -void write_rdramd_new(); -extern u_int memory_map[1048576]; - // Needed by assembler -void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32); -void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty); -void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr); -void load_all_regs(signed char i_regmap[]); -void load_needed_regs(signed char i_regmap[],signed char next_regmap[]); -void load_regs_entry(int t); -void load_all_consts(signed char regmap[],int is32,u_int dirty,int i); +static void wb_register(signed char r,signed char regmap[],uint64_t dirty); +static void wb_dirtys(signed char i_regmap[],uint64_t i_dirty); +static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr); +static void load_all_regs(signed char i_regmap[]); +static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]); +static void load_regs_entry(int t); +static void load_all_consts(signed char regmap[],u_int dirty,int i); + +static int verify_dirty(const u_int *ptr); +static int get_final_value(int hr, int i, int *value); +static void add_stub(enum stub_type type, void *addr, void *retaddr, + u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e); +static void add_stub_r(enum stub_type type, void *addr, void *retaddr, + int i, int addr_reg, struct regstat *i_regs, int ccadj, u_int reglist); +static void add_to_linker(void *addr, u_int target, int ext); +static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override); +static void *get_direct_memhandler(void *table, u_int addr, + enum stub_type type, uintptr_t *addr_host); +static void pass_args(int a0, int a1); + +static void mprotect_w_x(void *start, void *end, int is_x) +{ +#ifdef NO_WRITE_EXEC + #if defined(VITA) + // *Open* enables write on all memory that was + // allocated by sceKernelAllocMemBlockForVM()? + if (is_x) + sceKernelCloseVMDomain(); + else + sceKernelOpenVMDomain(); + #else + u_long mstart = (u_long)start & ~4095ul; + u_long mend = (u_long)end; + if (mprotect((void *)mstart, mend - mstart, + PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0) + SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno)); + #endif +#endif +} + +static void start_tcache_write(void *start, void *end) +{ + mprotect_w_x(start, end, 0); +} + +static void end_tcache_write(void *start, void *end) +{ +#ifdef __arm__ + size_t len = (char *)end - (char *)start; + #if defined(__BLACKBERRY_QNX__) + msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE); + #elif defined(__MACH__) + sys_cache_control(kCacheFunctionPrepareForExecution, start, len); + #elif defined(VITA) + sceKernelSyncVMDomain(sceBlock, start, len); + #elif defined(_3DS) + ctr_flush_invalidate_cache(); + #else + __clear_cache(start, end); + #endif + (void)len; +#else + __clear_cache(start, end); +#endif + + mprotect_w_x(start, end, 1); +} + +static void *start_block(void) +{ + u_char *end = out + MAX_OUTPUT_BLOCK_SIZE; + if (end > translation_cache + (1<nom, "GOLDENEYE",9) == 0) - { - u_int addr; - int n; - switch (ROM_HEADER->Country_code&0xFF) - { - case 0x45: // U - addr=0x34b30; - break; - case 0x4A: // J - addr=0x34b70; - break; - case 0x50: // E - addr=0x329f0; - break; - default: - // Unknown country code - addr=0; - break; - } - u_int rom_addr=(u_int)rom; - #ifdef ROM_COPY - // Since memory_map is 32-bit, on 64-bit systems the rom needs to be - // in the lower 4G of memory to use this hack. Copy it if necessary. - if((void *)rom>(void *)0xffffffff) { - munmap(ROM_COPY, 67108864); - if(mmap(ROM_COPY, 12582912, - PROT_READ | PROT_WRITE, - MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, - -1, 0) <= 0) {printf("mmap() failed\n");} - memcpy(ROM_COPY,rom,12582912); - rom_addr=(u_int)ROM_COPY; - } - #endif - if(addr) { - for(n=0x7F000;n<0x80000;n++) { - memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000; - } - } - } -#endif -} - static u_int get_page(u_int vaddr) { -#ifndef PCSX - u_int page=(vaddr^0x80000000)>>12; -#else u_int page=vaddr&~0xe0000000; if (page < 0x1000000) page &= ~0x0e00000; // RAM mirrors page>>=12; -#endif -#ifndef DISABLE_TLB - if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12; -#endif if(page>2048) page=2048+(page&2047); return page; } -#ifndef PCSX -static u_int get_vpage(u_int vaddr) -{ - u_int vpage=(vaddr^0x80000000)>>12; -#ifndef DISABLE_TLB - if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead -#endif - if(vpage>2048) vpage=2048+(vpage&2047); - return vpage; -} -#else // no virtual mem in PCSX static u_int get_vpage(u_int vaddr) { return get_page(vaddr); } -#endif + +static struct ht_entry *hash_table_get(u_int vaddr) +{ + return &hash_table[((vaddr>>16)^vaddr)&0xFFFF]; +} + +static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr) +{ + ht_bin->vaddr[1] = ht_bin->vaddr[0]; + ht_bin->tcaddr[1] = ht_bin->tcaddr[0]; + ht_bin->vaddr[0] = vaddr; + ht_bin->tcaddr[0] = tcaddr; +} + +// some messy ari64's code, seems to rely on unsigned 32bit overflow +static int doesnt_expire_soon(void *tcaddr) +{ + u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2); + return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2))); +} // Get address from virtual address // This is called from the recompiled JR/JALR instructions -void *get_addr(u_int vaddr) +void noinline *get_addr(u_int vaddr) { u_int page=get_page(vaddr); u_int vpage=get_vpage(vaddr); @@ -374,51 +429,33 @@ void *get_addr(u_int vaddr) //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page); head=jump_in[page]; while(head!=NULL) { - if(head->vaddr==vaddr&&head->reg32==0) { - //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr); - int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; - ht_bin[3]=ht_bin[1]; - ht_bin[2]=ht_bin[0]; - ht_bin[1]=(int)head->addr; - ht_bin[0]=vaddr; + if(head->vaddr==vaddr) { + //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr); + hash_table_add(hash_table_get(vaddr), vaddr, head->addr); return head->addr; } head=head->next; } head=jump_dirty[vpage]; while(head!=NULL) { - if(head->vaddr==vaddr&&head->reg32==0) { - //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr); + if(head->vaddr==vaddr) { + //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr); // Don't restore blocks which are about to expire from the cache - if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) - if(verify_dirty(head->addr)) { + if (doesnt_expire_soon(head->addr)) + if (verify_dirty(head->addr)) { //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]); invalid_code[vaddr>>12]=0; inv_code_start=inv_code_end=~0; -#ifndef DISABLE_TLB - memory_map[vaddr>>12]|=0x40000000; -#endif if(vpage<2048) { -#ifndef DISABLE_TLB - if(tlb_LUT_r[vaddr>>12]) { - invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0; - memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000; - } -#endif restore_candidate[vpage>>3]|=1<<(vpage&7); } else restore_candidate[page>>3]|=1<<(page&7); - int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; - if(ht_bin[0]==vaddr) { - ht_bin[1]=(int)head->addr; // Replace existing entry - } + struct ht_entry *ht_bin = hash_table_get(vaddr); + if (ht_bin->vaddr[0] == vaddr) + ht_bin->tcaddr[0] = head->addr; // Replace existing entry else - { - ht_bin[3]=ht_bin[1]; - ht_bin[2]=ht_bin[0]; - ht_bin[1]=(int)head->addr; - ht_bin[0]=vaddr; - } + hash_table_add(ht_bin, vaddr, head->addr); + return head->addr; } } @@ -440,98 +477,10 @@ void *get_addr(u_int vaddr) void *get_addr_ht(u_int vaddr) { //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr); - int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; - if(ht_bin[0]==vaddr) return (void *)ht_bin[1]; - if(ht_bin[2]==vaddr) return (void *)ht_bin[3]; - return get_addr(vaddr); -} - -void *get_addr_32(u_int vaddr,u_int flags) -{ -#ifdef FORCE32 + const struct ht_entry *ht_bin = hash_table_get(vaddr); + if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0]; + if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1]; return get_addr(vaddr); -#else - //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags); - int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; - if(ht_bin[0]==vaddr) return (void *)ht_bin[1]; - if(ht_bin[2]==vaddr) return (void *)ht_bin[3]; - u_int page=get_page(vaddr); - u_int vpage=get_vpage(vaddr); - struct ll_entry *head; - head=jump_in[page]; - while(head!=NULL) { - if(head->vaddr==vaddr&&(head->reg32&flags)==0) { - //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr); - if(head->reg32==0) { - int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; - if(ht_bin[0]==-1) { - ht_bin[1]=(int)head->addr; - ht_bin[0]=vaddr; - }else if(ht_bin[2]==-1) { - ht_bin[3]=(int)head->addr; - ht_bin[2]=vaddr; - } - //ht_bin[3]=ht_bin[1]; - //ht_bin[2]=ht_bin[0]; - //ht_bin[1]=(int)head->addr; - //ht_bin[0]=vaddr; - } - return head->addr; - } - head=head->next; - } - head=jump_dirty[vpage]; - while(head!=NULL) { - if(head->vaddr==vaddr&&(head->reg32&flags)==0) { - //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr); - // Don't restore blocks which are about to expire from the cache - if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) - if(verify_dirty(head->addr)) { - //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]); - invalid_code[vaddr>>12]=0; - inv_code_start=inv_code_end=~0; - memory_map[vaddr>>12]|=0x40000000; - if(vpage<2048) { -#ifndef DISABLE_TLB - if(tlb_LUT_r[vaddr>>12]) { - invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0; - memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000; - } -#endif - restore_candidate[vpage>>3]|=1<<(vpage&7); - } - else restore_candidate[page>>3]|=1<<(page&7); - if(head->reg32==0) { - int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; - if(ht_bin[0]==-1) { - ht_bin[1]=(int)head->addr; - ht_bin[0]=vaddr; - }else if(ht_bin[2]==-1) { - ht_bin[3]=(int)head->addr; - ht_bin[2]=vaddr; - } - //ht_bin[3]=ht_bin[1]; - //ht_bin[2]=ht_bin[0]; - //ht_bin[1]=(int)head->addr; - //ht_bin[0]=vaddr; - } - return head->addr; - } - } - head=head->next; - } - //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags); - int r=new_recompile_block(vaddr); - if(r==0) return get_addr(vaddr); - // Execute in unmapped page, generate pagefault execption - Status|=2; - Cause=(vaddr<<31)|0x8; - EPC=(vaddr&1)?vaddr-5:vaddr; - BadVAddr=(vaddr&~1); - Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0); - EntryHi=BadVAddr&0xFFFFE000; - return get_addr_ht(0x80000000); -#endif } void clear_all_regs(signed char regmap[]) @@ -540,7 +489,7 @@ void clear_all_regs(signed char regmap[]) for (hr=0;hrdirty>>hr)&1) { - reg=cur->regmap[hr]; - if(reg>=64) - if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1; - } - } -} - void set_const(struct regstat *cur,signed char reg,uint64_t value) { int hr; @@ -605,10 +537,6 @@ void set_const(struct regstat *cur,signed char reg,uint64_t value) cur->isconst|=1<regmap[hr]^64)==reg) { - cur->isconst|=1<>32; - } } } @@ -644,8 +572,8 @@ uint64_t get_const(struct regstat *cur,signed char reg) return current_constmap[hr]; } } - printf("Unknown constant in r%d\n",reg); - exit(1); + SysPrintf("Unknown constant in r%d\n",reg); + abort(); } // Least soon needed registers @@ -685,7 +613,7 @@ void lsn(u_char hsn[], int i, int *preferred_reg) hsn[INVCP]=j; } #endif - if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP)) + if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP)) { hsn[CCREG]=j; b=j; @@ -709,7 +637,7 @@ void lsn(u_char hsn[], int i, int *preferred_reg) // TODO: preferred register based on backward branch } // Delay slot should preferably not overwrite branch conditions or cycle count - if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) { + if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP)) { if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1; if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1; hsn[CCREG]=1; @@ -729,10 +657,6 @@ void lsn(u_char hsn[], int i, int *preferred_reg) if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { hsn[FTEMP]=0; } - // Don't remove the TLB registers either - if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) { - hsn[TLREG]=0; - } // Don't remove the miniht registers if(itype[i]==UJUMP||itype[i]==RJUMP) { @@ -747,7 +671,7 @@ int needed_again(int r, int i) int j; int b=-1; int rn=10; - + if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) { if(ba[i-1]start+slen*4-4) @@ -775,7 +699,7 @@ int needed_again(int r, int i) if(rs1[i+j]==r) rn=j; if(rs2[i+j]==r) rn=j; if((unneeded_reg[i+j]>>r)&1) rn=10; - if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP)) + if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP)) { b=j; } @@ -800,6 +724,7 @@ int needed_again(int r, int i) } }*/ if(rn<10) return 1; + (void)b; return 0; } @@ -823,14 +748,14 @@ int loop_reg(int i, int r, int hr) } k=0; if(i>0){ - if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) + if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP) k--; } for(;k>r)&1)) return hr; - if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr; - if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP)) + assert(r < 64); + if((unneeded_reg[i+k]>>r)&1) return hr; + if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP)) { if(ba[i+k]>=start && ba[i+k]<(start+i*4)) { @@ -850,7 +775,7 @@ int loop_reg(int i, int r, int hr) void alloc_all(struct regstat *cur,int i) { int hr; - + for(hr=0;hrregmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&& @@ -869,117 +794,63 @@ void alloc_all(struct regstat *cur,int i) } } -#ifndef FORCE32 -void div64(int64_t dividend,int64_t divisor) -{ - lo=dividend/divisor; - hi=dividend%divisor; - //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32) - // ,(int)reg[LOREG],(int)(reg[LOREG]>>32)); -} -void divu64(uint64_t dividend,uint64_t divisor) -{ - lo=dividend/divisor; - hi=dividend%divisor; - //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32) - // ,(int)reg[LOREG],(int)(reg[LOREG]>>32)); -} - -void mult64(uint64_t m1,uint64_t m2) -{ - unsigned long long int op1, op2, op3, op4; - unsigned long long int result1, result2, result3, result4; - unsigned long long int temp1, temp2, temp3, temp4; - int sign = 0; - - if (m1 < 0) - { - op2 = -m1; - sign = 1 - sign; - } - else op2 = m1; - if (m2 < 0) - { - op4 = -m2; - sign = 1 - sign; - } - else op4 = m2; - - op1 = op2 & 0xFFFFFFFF; - op2 = (op2 >> 32) & 0xFFFFFFFF; - op3 = op4 & 0xFFFFFFFF; - op4 = (op4 >> 32) & 0xFFFFFFFF; - - temp1 = op1 * op3; - temp2 = (temp1 >> 32) + op1 * op4; - temp3 = op2 * op3; - temp4 = (temp3 >> 32) + op2 * op4; - - result1 = temp1 & 0xFFFFFFFF; - result2 = temp2 + (temp3 & 0xFFFFFFFF); - result3 = (result2 >> 32) + temp4; - result4 = (result3 >> 32); - - lo = result1 | (result2 << 32); - hi = (result3 & 0xFFFFFFFF) | (result4 << 32); - if (sign) - { - hi = ~hi; - if (!lo) hi++; - else lo = ~lo + 1; - } -} - -void multu64(uint64_t m1,uint64_t m2) -{ - unsigned long long int op1, op2, op3, op4; - unsigned long long int result1, result2, result3, result4; - unsigned long long int temp1, temp2, temp3, temp4; - - op1 = m1 & 0xFFFFFFFF; - op2 = (m1 >> 32) & 0xFFFFFFFF; - op3 = m2 & 0xFFFFFFFF; - op4 = (m2 >> 32) & 0xFFFFFFFF; - - temp1 = op1 * op3; - temp2 = (temp1 >> 32) + op1 * op4; - temp3 = op2 * op3; - temp4 = (temp3 >> 32) + op2 * op4; - - result1 = temp1 & 0xFFFFFFFF; - result2 = temp2 + (temp3 & 0xFFFFFFFF); - result3 = (result2 >> 32) + temp4; - result4 = (result3 >> 32); - - lo = result1 | (result2 << 32); - hi = (result3 & 0xFFFFFFFF) | (result4 << 32); - - //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32) - // ,(int)reg[LOREG],(int)(reg[LOREG]>>32)); -} - -uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits) -{ - if(bits) { - original<<=64-bits; - original>>=64-bits; - loaded<<=bits; - original|=loaded; - } - else original=loaded; - return original; -} -uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits) -{ - if(bits^56) { - original>>=64-(bits^56); - original<<=64-(bits^56); - loaded>>=bits^56; - original|=loaded; - } - else original=loaded; - return original; +#ifndef NDEBUG +static int host_tempreg_in_use; + +static void host_tempreg_acquire(void) +{ + assert(!host_tempreg_in_use); + host_tempreg_in_use = 1; +} + +static void host_tempreg_release(void) +{ + host_tempreg_in_use = 0; +} +#else +static void host_tempreg_acquire(void) {} +static void host_tempreg_release(void) {} +#endif + +#ifdef DRC_DBG +extern void gen_interupt(); +extern void do_insn_cmp(); +#define FUNCNAME(f) { f, " " #f } +static const struct { + void *addr; + const char *name; +} function_names[] = { + FUNCNAME(cc_interrupt), + FUNCNAME(gen_interupt), + FUNCNAME(get_addr_ht), + FUNCNAME(get_addr), + FUNCNAME(jump_handler_read8), + FUNCNAME(jump_handler_read16), + FUNCNAME(jump_handler_read32), + FUNCNAME(jump_handler_write8), + FUNCNAME(jump_handler_write16), + FUNCNAME(jump_handler_write32), + FUNCNAME(invalidate_addr), + FUNCNAME(jump_to_new_pc), + FUNCNAME(new_dyna_leave), + FUNCNAME(pcsx_mtc0), + FUNCNAME(pcsx_mtc0_ds), + FUNCNAME(do_insn_cmp), +#ifdef __arm__ + FUNCNAME(verify_code), +#endif +}; + +static const char *func_name(const void *a) +{ + int i; + for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++) + if (function_names[i].addr == a) + return function_names[i].name; + return ""; } +#else +#define func_name(x) "" #endif #ifdef __i386__ @@ -991,6 +862,9 @@ uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits) #ifdef __arm__ #include "assem_arm.c" #endif +#ifdef __aarch64__ +#include "assem_arm64.c" +#endif // Add virtual address mapping to linked list void ll_add(struct ll_entry **head,int vaddr,void *addr) @@ -999,58 +873,55 @@ void ll_add(struct ll_entry **head,int vaddr,void *addr) new_entry=malloc(sizeof(struct ll_entry)); assert(new_entry!=NULL); new_entry->vaddr=vaddr; - new_entry->reg32=0; + new_entry->reg_sv_flags=0; new_entry->addr=addr; new_entry->next=*head; *head=new_entry; } -// Add virtual address mapping for 32-bit compiled block -void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr) +void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr) { ll_add(head,vaddr,addr); -#ifndef FORCE32 - (*head)->reg32=reg32; -#endif + (*head)->reg_sv_flags=reg_sv_flags; } // Check if an address is already compiled // but don't return addresses which are about to expire from the cache void *check_addr(u_int vaddr) { - u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF]; - if(ht_bin[0]==vaddr) { - if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) - if(isclean(ht_bin[1])) return (void *)ht_bin[1]; - } - if(ht_bin[2]==vaddr) { - if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) - if(isclean(ht_bin[3])) return (void *)ht_bin[3]; + struct ht_entry *ht_bin = hash_table_get(vaddr); + size_t i; + for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) { + if (ht_bin->vaddr[i] == vaddr) + if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE)) + if (isclean(ht_bin->tcaddr[i])) + return ht_bin->tcaddr[i]; } u_int page=get_page(vaddr); struct ll_entry *head; head=jump_in[page]; - while(head!=NULL) { - if(head->vaddr==vaddr&&head->reg32==0) { - if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) { + while (head != NULL) { + if (head->vaddr == vaddr) { + if (doesnt_expire_soon(head->addr)) { // Update existing entry with current address - if(ht_bin[0]==vaddr) { - ht_bin[1]=(int)head->addr; + if (ht_bin->vaddr[0] == vaddr) { + ht_bin->tcaddr[0] = head->addr; return head->addr; } - if(ht_bin[2]==vaddr) { - ht_bin[3]=(int)head->addr; + if (ht_bin->vaddr[1] == vaddr) { + ht_bin->tcaddr[1] = head->addr; return head->addr; } // Insert into hash table with low priority. // Don't evict existing entries, as they are probably // addresses that are being accessed frequently. - if(ht_bin[0]==-1) { - ht_bin[1]=(int)head->addr; - ht_bin[0]=vaddr; - }else if(ht_bin[2]==-1) { - ht_bin[3]=(int)head->addr; - ht_bin[2]=vaddr; + if (ht_bin->vaddr[0] == -1) { + ht_bin->vaddr[0] = vaddr; + ht_bin->tcaddr[0] = head->addr; + } + else if (ht_bin->vaddr[1] == -1) { + ht_bin->vaddr[1] = vaddr; + ht_bin->tcaddr[1] = head->addr; } return head->addr; } @@ -1063,25 +934,27 @@ void *check_addr(u_int vaddr) void remove_hash(int vaddr) { //printf("remove hash: %x\n",vaddr); - int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF]; - if(ht_bin[2]==vaddr) { - ht_bin[2]=ht_bin[3]=-1; + struct ht_entry *ht_bin = hash_table_get(vaddr); + if (ht_bin->vaddr[1] == vaddr) { + ht_bin->vaddr[1] = -1; + ht_bin->tcaddr[1] = NULL; } - if(ht_bin[0]==vaddr) { - ht_bin[0]=ht_bin[2]; - ht_bin[1]=ht_bin[3]; - ht_bin[2]=ht_bin[3]=-1; + if (ht_bin->vaddr[0] == vaddr) { + ht_bin->vaddr[0] = ht_bin->vaddr[1]; + ht_bin->tcaddr[0] = ht_bin->tcaddr[1]; + ht_bin->vaddr[1] = -1; + ht_bin->tcaddr[1] = NULL; } } -void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift) +void ll_remove_matching_addrs(struct ll_entry **head,uintptr_t addr,int shift) { struct ll_entry *next; while(*head) { - if(((u_int)((*head)->addr)>>shift)==(addr>>shift) || - ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)) + if(((uintptr_t)((*head)->addr)>>shift)==(addr>>shift) || + ((uintptr_t)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)) { - inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr); + inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr); remove_hash((*head)->vaddr); next=(*head)->next; free(*head); @@ -1099,7 +972,7 @@ void ll_clear(struct ll_entry **head) { struct ll_entry *cur; struct ll_entry *next; - if(cur=*head) { + if((cur=*head)) { *head=0; while(cur) { next=cur->next; @@ -1110,26 +983,27 @@ void ll_clear(struct ll_entry **head) } // Dereference the pointers and remove if it matches -void ll_kill_pointers(struct ll_entry *head,int addr,int shift) +static void ll_kill_pointers(struct ll_entry *head,uintptr_t addr,int shift) { while(head) { - int ptr=get_pointer(head->addr); - inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr); + uintptr_t ptr = (uintptr_t)get_pointer(head->addr); + inv_debug("EXP: Lookup pointer to %lx at %p (%x)\n",(long)ptr,head->addr,head->vaddr); if(((ptr>>shift)==(addr>>shift)) || (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))) { - inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr); - u_int host_addr=(u_int)kill_pointer(head->addr); - #ifdef __arm__ - needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31); + inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr); + void *host_addr=find_extjump_insn(head->addr); + #if defined(__arm__) || defined(__aarch64__) + mark_clear_cache(host_addr); #endif + set_jump_target(host_addr, head->addr); } head=head->next; } } // This is called when we write to a compiled block (see do_invstub) -void invalidate_page(u_int page) +static void invalidate_page(u_int page) { struct ll_entry *head; struct ll_entry *next; @@ -1145,11 +1019,12 @@ void invalidate_page(u_int page) head=jump_out[page]; jump_out[page]=0; while(head!=NULL) { - inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr); - u_int host_addr=(u_int)kill_pointer(head->addr); - #ifdef __arm__ - needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31); + inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr); + void *host_addr=find_extjump_insn(head->addr); + #if defined(__arm__) || defined(__aarch64__) + mark_clear_cache(host_addr); #endif + set_jump_target(host_addr, head->addr); next=head->next; free(head); head=next; @@ -1171,24 +1046,12 @@ static void invalidate_block_range(u_int block, u_int first, u_int last) for(first=page+1;first>2; - u_int real_block=tlb_LUT_w[block]>>12; - invalid_code[real_block]=1; - if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2; - } - else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2; -#endif #ifdef USE_MINI_HT memset(mini_ht,-1,sizeof(mini_ht)); @@ -1207,24 +1070,16 @@ void invalidate_block(u_int block) head=jump_dirty[vpage]; //printf("page=%d vpage=%d\n",page,vpage); while(head!=NULL) { - u_int start,end; if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision - get_bounds((int)head->addr,&start,&end); - //printf("start: %x end: %x\n",start,end); - if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) { - if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) { - if((((start-(u_int)rdram)>>12)&2047)>12)&2047; - if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047; - } - } -#ifndef DISABLE_TLB - if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) { - if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) { - if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)>12]-(u_int)rdram)>>12)&2047; - if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047; + u_char *start, *end; + get_bounds(head->addr, &start, &end); + //printf("start: %p end: %p\n", start, end); + if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) { + if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) { + if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047; + if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047; } } -#endif } head=head->next; } @@ -1233,7 +1088,6 @@ void invalidate_block(u_int block) void invalidate_addr(u_int addr) { -#ifdef PCSX //static int rhits; // this check is done by the caller //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; } @@ -1241,10 +1095,11 @@ void invalidate_addr(u_int addr) if(page<2048) { // RAM struct ll_entry *head; u_int addr_min=~0, addr_max=0; - int mask=RAM_SIZE-1; + u_int mask=RAM_SIZE-1; + u_int addr_main=0x80000000|(addr&mask); int pg1; - inv_code_start=addr&~0xfff; - inv_code_end=addr|0xfff; + inv_code_start=addr_main&~0xfff; + inv_code_end=addr_main|0xfff; pg1=page; if (pg1>0) { // must check previous page too because of spans.. @@ -1253,13 +1108,16 @@ void invalidate_addr(u_int addr) } for(;pg1<=page;pg1++) { for(head=jump_dirty[pg1];head!=NULL;head=head->next) { - u_int start,end; - get_bounds((int)head->addr,&start,&end); - if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) { + u_char *start_h, *end_h; + u_int start, end; + get_bounds(head->addr, &start_h, &end_h); + start = (uintptr_t)start_h - ram_offset; + end = (uintptr_t)end_h - ram_offset; + if(start<=addr_main&&addr_mainaddr_max) addr_max=end; } - else if(addr>12); } @@ -1288,7 +1147,7 @@ void invalidate_addr(u_int addr) // Anything could have changed, so invalidate everything. void invalidate_all_pages() { - u_int page,n; + u_int page; for(page=0;page<4096;page++) invalidate_page(page); for(page=0;page<1048576;page++) @@ -1296,37 +1155,33 @@ void invalidate_all_pages() restore_candidate[(page&2047)>>3]|=1<<(page&7); restore_candidate[((page&2047)>>3)+256]|=1<<(page&7); } - #ifdef __arm__ - __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<>2; - if(!tlb_LUT_w[page]||!invalid_code[page]) - memory_map[page]|=0x40000000; // Write protect - } - else memory_map[page]=-1; - if(page==0x80000) page=0xC0000; - } - tlb_hacks(); - #endif +} + +static void do_invstub(int n) +{ + literal_pool(20); + u_int reglist=stubs[n].a; + set_jump_target(stubs[n].addr, out); + save_regs(reglist); + if(stubs[n].b!=0) emit_mov(stubs[n].b,0); + emit_call(invalidate_addr); + restore_regs(reglist); + emit_jmp(stubs[n].retaddr); // return address } // Add an entry to jump_out after making a link +// src should point to code by emit_extjump2() void add_link(u_int vaddr,void *src) { u_int page=get_page(vaddr); - inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page); - int *ptr=(int *)(src+4); - assert((*ptr&0x0fff0000)==0x059f0000); + inv_debug("add_link: %p -> %x (%d)\n",src,vaddr,page); + check_extjump2(src); ll_add(jump_out+page,vaddr,src); - //int ptr=get_pointer(src); - //inv_debug("add_link: Pointer is to %x\n",(int)ptr); + //void *ptr=get_pointer(src); + //inv_debug("add_link: Pointer is to %p\n",ptr); } // If a code block was found to be unmodified (bit was set in @@ -1341,48 +1196,34 @@ void clean_blocks(u_int page) while(head!=NULL) { if(!invalid_code[head->vaddr>>12]) { // Don't restore blocks which are about to expire from the cache - if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) { - u_int start,end; - if(verify_dirty((int)head->addr)) { - //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr); + if (doesnt_expire_soon(head->addr)) { + if(verify_dirty(head->addr)) { + u_char *start, *end; + //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr); u_int i; u_int inv=0; - get_bounds((int)head->addr,&start,&end); - if(start-(u_int)rdram>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) { + get_bounds(head->addr, &start, &end); + if (start - rdram < RAM_SIZE) { + for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) { inv|=invalid_code[i]; } } -#ifndef DISABLE_TLB - if((signed int)head->vaddr>=(signed int)0xC0000000) { - u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2)); - //printf("addr=%x start=%x end=%x\n",addr,start,end); - if(addr=end) inv=1; - } -#endif else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) { inv=1; } if(!inv) { - void * clean_addr=(void *)get_clean_addr((int)head->addr); - if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) { + void *clean_addr = get_clean_addr(head->addr); + if (doesnt_expire_soon(clean_addr)) { u_int ppage=page; -#ifndef DISABLE_TLB - if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12; -#endif - inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr); + inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr); //printf("page=%x, addr=%x\n",page,head->vaddr); //assert(head->vaddr>>12==(page|0x80000)); - ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr); - int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF]; - if(!head->reg32) { - if(ht_bin[0]==head->vaddr) { - ht_bin[1]=(int)clean_addr; // Replace existing entry - } - if(ht_bin[2]==head->vaddr) { - ht_bin[3]=(int)clean_addr; // Replace existing entry - } - } + ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr); + struct ht_entry *ht_bin = hash_table_get(head->vaddr); + if (ht_bin->vaddr[0] == head->vaddr) + ht_bin->tcaddr[0] = clean_addr; // Replace existing entry + if (ht_bin->vaddr[1] == head->vaddr) + ht_bin->tcaddr[1] = clean_addr; // Replace existing entry } } } @@ -1392,115 +1233,307 @@ void clean_blocks(u_int page) } } +/* Register allocation */ -void mov_alloc(struct regstat *current,int i) +// Note: registers are allocated clean (unmodified state) +// if you intend to modify the register, you must call dirty_reg(). +static void alloc_reg(struct regstat *cur,int i,signed char reg) { - // Note: Don't need to actually alloc the source registers - if((~current->is32>>rs1[i])&1) { - //alloc_reg64(current,i,rs1[i]); - alloc_reg64(current,i,rt1[i]); - current->is32&=~(1LL<is32|=(1LL<is32|=1LL<>imm[i]); - if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]); - } - else clear_const(current,rt1[i]); - } - } - else - { - clear_const(current,rs1[i]); - clear_const(current,rt1[i]); - } + // Don't allocate unused registers + if((cur->u>>reg)&1) return; - if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA + // see if it's already allocated + for(hr=0;hris32&=~(1LL<regmap[hr]==reg) return; + } + + // Keep the same mapping if the register was already allocated in a loop + preferred_reg = loop_reg(i,reg,preferred_reg); + + // Try to allocate the preferred register + if(cur->regmap[preferred_reg]==-1) { + cur->regmap[preferred_reg]=reg; + cur->dirty&=~(1<isconst&=~(1<regmap[preferred_reg]; + assert(r < 64); + if((cur->u>>r)&1) { + cur->regmap[preferred_reg]=reg; + cur->dirty&=~(1<isconst&=~(1<is32&=~(1LL<regmap[hr]; + if(r>=0) { + assert(r < 64); + if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;} } } - if(opcode2[i]==0x3e) // DSRL32 - { - if(rt1[i]) { - alloc_reg64(current,i,rs1[i]); - if(imm[i]==32) { - alloc_reg64(current,i,rt1[i]); - current->is32&=~(1LL<is32|=1LL<0) { + for(hr=0;hrregmap[hr]==-1) { + if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) { + cur->regmap[hr]=reg; + cur->dirty&=~(1<isconst&=~(1<is32|=1LL<regmap[hr]==-1) { + cur->regmap[hr]=reg; + cur->dirty&=~(1<isconst&=~(1<regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]); + //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]); + if(i>0) { + // Don't evict the cycle count at entry points, otherwise the entry + // stub will have to write it. + if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2; + if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP)) hsn[CCREG]=2; + for(j=10;j>=3;j--) { - if(rs1[i]) alloc_reg(current,i,rs1[i]); - if(rs2[i]) alloc_reg(current,i,rs2[i]); - alloc_reg(current,i,rt1[i]); - if(rt1[i]==rs2[i]) { - alloc_reg_temp(current,i,-1); - minimum_free_regs[i]=1; + // Alloc preferred register if available + if(hsn[r=cur->regmap[preferred_reg]&63]==j) { + for(hr=0;hrregmap[hr]&63)==r) { + cur->regmap[hr]=-1; + cur->dirty&=~(1<isconst&=~(1<regmap[preferred_reg]=reg; + return; } - current->is32|=1LL<is32&=~(1LL<regmap[hr]==r) { + cur->regmap[hr]=reg; + cur->dirty&=~(1<isconst&=~(1<=0;j--) + { + for(r=1;r<=MAXREG;r++) + { + if(hsn[r]==j) { + for(hr=0;hrregmap[hr]==r) { + cur->regmap[hr]=reg; + cur->dirty&=~(1<isconst&=~(1<regmap[hr]==reg) return; + } + + // Try to allocate any available register + for(hr=HOST_REGS-1;hr>=0;hr--) { + if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) { + cur->regmap[hr]=reg; + cur->dirty&=~(1<isconst&=~(1<=0;hr--) + { + r=cur->regmap[hr]; + if(r>=0) { + assert(r < 64); + if((cur->u>>r)&1) { + if(i==0||((unneeded_reg[i-1]>>r)&1)) { + cur->regmap[hr]=reg; + cur->dirty&=~(1<isconst&=~(1<regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]); + if(i>0) { + // Don't evict the cycle count at entry points, otherwise the entry + // stub will have to write it. + if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2; + if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP)) hsn[CCREG]=2; + for(j=10;j>=3;j--) + { + for(r=1;r<=MAXREG;r++) { + if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) { + for(hr=0;hr2) { + if(cur->regmap[hr]==r) { + cur->regmap[hr]=reg; + cur->dirty&=~(1<isconst&=~(1<=0;j--) + { + for(r=1;r<=MAXREG;r++) + { + if(hsn[r]==j) { + for(hr=0;hrregmap[hr]==r) { + cur->regmap[hr]=reg; + cur->dirty&=~(1<isconst&=~(1<>imm[i]); + if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]); + } + else clear_const(current,rt1[i]); + } + } + else + { + clear_const(current,rs1[i]); + clear_const(current,rt1[i]); + } + + if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA + { + assert(0); + } + if(opcode2[i]==0x3c) // DSLL32 + { + assert(0); + } + if(opcode2[i]==0x3e) // DSRL32 + { + assert(0); + } + if(opcode2[i]==0x3f) // DSRA32 + { + assert(0); + } +} + +static void shift_alloc(struct regstat *current,int i) +{ + if(rt1[i]) { + if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV + { + if(rs1[i]) alloc_reg(current,i,rs1[i]); + if(rs2[i]) alloc_reg(current,i,rs2[i]); + alloc_reg(current,i,rt1[i]); + if(rt1[i]==rs2[i]) { alloc_reg_temp(current,i,-1); minimum_free_regs[i]=1; } + } else { // DSLLV/DSRLV/DSRAV + assert(0); } clear_const(current,rs1[i]); clear_const(current,rs2[i]); @@ -1509,7 +1542,7 @@ void shift_alloc(struct regstat *current,int i) } } -void alu_alloc(struct regstat *current,int i) +static void alu_alloc(struct regstat *current,int i) { if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU if(rt1[i]) { @@ -1523,22 +1556,13 @@ void alu_alloc(struct regstat *current,int i) } alloc_reg(current,i,rt1[i]); } - current->is32|=1LL<is32>>rs1[i])&(current->is32>>rs2[i])&1)) - { - alloc_reg64(current,i,rs1[i]); - alloc_reg64(current,i,rs2[i]); - alloc_reg(current,i,rt1[i]); - } else { - alloc_reg(current,i,rs1[i]); - alloc_reg(current,i,rs2[i]); - alloc_reg(current,i,rt1[i]); - } + alloc_reg(current,i,rs1[i]); + alloc_reg(current,i,rs2[i]); + alloc_reg(current,i,rt1[i]); } - current->is32|=1LL<=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR if(rt1[i]) { @@ -1552,78 +1576,10 @@ void alu_alloc(struct regstat *current,int i) if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]); } alloc_reg(current,i,rt1[i]); - if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1)) - { - if(!((current->uu>>rt1[i])&1)) { - alloc_reg64(current,i,rt1[i]); - } - if(get_reg(current->regmap,rt1[i]|64)>=0) { - if(rs1[i]&&rs2[i]) { - alloc_reg64(current,i,rs1[i]); - alloc_reg64(current,i,rs2[i]); - } - else - { - // Is is really worth it to keep 64-bit values in registers? - #ifdef NATIVE_64BIT - if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]); - if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]); - #endif - } - } - current->is32&=~(1LL<is32|=1LL<=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU - if(rt1[i]) { - if(rs1[i]&&rs2[i]) { - if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) { - alloc_reg64(current,i,rs1[i]); - alloc_reg64(current,i,rs2[i]); - alloc_reg64(current,i,rt1[i]); - } else { - alloc_reg(current,i,rs1[i]); - alloc_reg(current,i,rs2[i]); - alloc_reg(current,i,rt1[i]); - } - } - else { - alloc_reg(current,i,rt1[i]); - if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) { - // DADD used as move, or zeroing - // If we have a 64-bit source, then make the target 64 bits too - if(rs1[i]&&!((current->is32>>rs1[i])&1)) { - if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]); - alloc_reg64(current,i,rt1[i]); - } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) { - if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]); - alloc_reg64(current,i,rt1[i]); - } - if(opcode2[i]>=0x2e&&rs2[i]) { - // DSUB used as negation - 64-bit result - // If we have a 32-bit register, extend it to 64 bits - if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]); - alloc_reg64(current,i,rt1[i]); - } - } - } - if(rs1[i]&&rs2[i]) { - current->is32&=~(1LL<is32&=~(1LL<is32>>rs1[i])&1) - current->is32|=1LL<is32&=~(1LL<is32>>rs2[i])&1) - current->is32|=1LL<is32|=1LL<is32&=~(1LL<uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) { - // TODO: Could preserve the 32-bit flag if the immediate is zero - alloc_reg64(current,i,rt1[i]); - alloc_reg64(current,i,rs1[i]); - } - clear_const(current,rs1[i]); - clear_const(current,rt1[i]); + assert(0); } else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU - if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]); - current->is32|=1LL<=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI - if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) { - if(rs1[i]!=rt1[i]) { - if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]); - alloc_reg64(current,i,rt1[i]); - current->is32&=~(1LL<is32|=1LL<is32|=1LL<is32|=1LL<regmap,rt1[i])>=0); if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD { - current->is32&=~(1LL<is32&=~(1LL<is32|=1LL<is32|=1LL<is32|=1LL<u&=~(1LL<u&=~(1LL<uu&=~(1LL<uu&=~(1LL<10) alloc_reg64(current,i,LOREG); - alloc_reg64(current,i,rs1[i]); - alloc_reg64(current,i,rs2[i]); - alloc_all(current,i); - current->is32&=~(1LL<is32&=~(1LL<is32|=1LL<is32|=1LL<is32|=1LL<is32&=~(1LL<is32|=1LL<3) // MTC1/DMTC1/CTC1 + else if(opcode2[i]>3) // MTC1/CTC1 { if(rs1[i]){ clear_const(current,rs1[i]); - if(opcode2[i]==5) - alloc_reg64(current,i,rs1[i]); // DMTC1 - else - alloc_reg(current,i,rs1[i]); // MTC1/CTC1 - alloc_reg_temp(current,i,-1); + alloc_reg(current,i,rs1[i]); } else { current->u&=~1LL; alloc_reg(current,i,0); - alloc_reg_temp(current,i,-1); } + alloc_reg_temp(current,i,-1); } minimum_free_regs[i]=1; } -void fconv_alloc(struct regstat *current,int i) -{ - alloc_reg(current,i,CSREG); // Load status - alloc_reg_temp(current,i,-1); - minimum_free_regs[i]=1; -} -void float_alloc(struct regstat *current,int i) -{ - alloc_reg(current,i,CSREG); // Load status - alloc_reg_temp(current,i,-1); - minimum_free_regs[i]=1; -} + void c2op_alloc(struct regstat *current,int i) { alloc_reg_temp(current,i,-1); } -void fcomp_alloc(struct regstat *current,int i) -{ - alloc_reg(current,i,CSREG); // Load status - alloc_reg(current,i,FSREG); // Load flags - dirty_reg(current,FSREG); // Flag will be modified - alloc_reg_temp(current,i,-1); - minimum_free_regs[i]=1; -} void syscall_alloc(struct regstat *current,int i) { @@ -1973,12 +1844,11 @@ void delayslot_alloc(struct regstat *current,int i) case CJUMP: case SJUMP: case RJUMP: - case FJUMP: case SYSCALL: case HLECALL: case SPAN: - assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1); - printf("Disabled speculative precompilation\n"); + assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort(); + SysPrintf("Disabled speculative precompilation\n"); stop_after_jal=1; break; case IMM16: @@ -2012,7 +1882,7 @@ void delayslot_alloc(struct regstat *current,int i) break; case COP1: case COP2: - cop1_alloc(current,i); + cop12_alloc(current,i); break; case C1LS: c1ls_alloc(current,i); @@ -2020,15 +1890,6 @@ void delayslot_alloc(struct regstat *current,int i) case C2LS: c2ls_alloc(current,i); break; - case FCONV: - fconv_alloc(current,i); - break; - case FLOAT: - float_alloc(current,i); - break; - case FCOMP: - fcomp_alloc(current,i); - break; case C2OP: c2op_alloc(current,i); break; @@ -2062,141 +1923,93 @@ static void pagespan_alloc(struct regstat *current,int i) { if(rs1[i]) alloc_reg(current,i,rs1[i]); if(rs2[i]) alloc_reg(current,i,rs2[i]); - if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1)) - { - if(rs1[i]) alloc_reg64(current,i,rs1[i]); - if(rs2[i]) alloc_reg64(current,i,rs2[i]); - } } else if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL { if(rs1[i]) alloc_reg(current,i,rs1[i]); - if(!((current->is32>>rs1[i])&1)) - { - if(rs1[i]) alloc_reg64(current,i,rs1[i]); - } - } - else - if(opcode[i]==0x11) // BC1 - { - alloc_reg(current,i,FSREG); - alloc_reg(current,i,CSREG); } //else ... } -add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e) +static void add_stub(enum stub_type type, void *addr, void *retaddr, + u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e) { - stubs[stubcount][0]=type; - stubs[stubcount][1]=addr; - stubs[stubcount][2]=retaddr; - stubs[stubcount][3]=a; - stubs[stubcount][4]=b; - stubs[stubcount][5]=c; - stubs[stubcount][6]=d; - stubs[stubcount][7]=e; + assert(stubcount < ARRAY_SIZE(stubs)); + stubs[stubcount].type = type; + stubs[stubcount].addr = addr; + stubs[stubcount].retaddr = retaddr; + stubs[stubcount].a = a; + stubs[stubcount].b = b; + stubs[stubcount].c = c; + stubs[stubcount].d = d; + stubs[stubcount].e = e; stubcount++; } +static void add_stub_r(enum stub_type type, void *addr, void *retaddr, + int i, int addr_reg, struct regstat *i_regs, int ccadj, u_int reglist) +{ + add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist); +} + // Write out a single register -void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32) +static void wb_register(signed char r,signed char regmap[],uint64_t dirty) { int hr; for(hr=0;hr>hr)&1) { - if(regmap[hr]<64) { - emit_storereg(r,hr); -#ifndef FORCE32 - if((is32>>regmap[hr])&1) { - emit_sarimm(hr,31,hr); - emit_storereg(r|64,hr); - } -#endif - }else{ - emit_storereg(r|64,hr); - } + assert(regmap[hr]<64); + emit_storereg(r,hr); } } } } } -int mchecksum() +static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u) { - //if(!tracedebug) return 0; - int i; - int sum=0; - for(i=0;i<2097152;i++) { - unsigned int temp=sum; - sum<<=1; - sum|=(~temp)>>31; - sum^=((u_int *)rdram)[i]; + //if(dirty_pre==dirty) return; + int hr,reg; + for(hr=0;hr>(reg&63))&1) { + if(reg>0) { + if(((dirty_pre&~dirty)>>hr)&1) { + if(reg>0&®<34) { + emit_storereg(reg,hr); + } + else if(reg>=64) { + assert(0); + } + } + } + } + } } - return sum; -} -int rchecksum() -{ - int i; - int sum=0; - for(i=0;i<64;i++) - sum^=((u_int *)reg)[i]; - return sum; -} -void rlist() -{ - int i; - printf("TRACE: "); - for(i=0;i<32;i++) - printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]); - printf("\n"); -#ifndef DISABLE_COP1 - printf("TRACE: "); - for(i=0;i<32;i++) - printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i])); - printf("\n"); -#endif } -void enabletrace() +// trashes r2 +static void pass_args(int a0, int a1) { - tracedebug=1; -} - -void memdebug(int i) -{ - //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]); - //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum()); - //rlist(); - //if(tracedebug) { - //if(Count>=-2084597794) { - if((signed int)Count>=-2084597794&&(signed int)Count<0) { - //if(0) { - printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum()); - //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status); - //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]); - rlist(); - #ifdef __i386__ - printf("TRACE: %x\n",(&i)[-1]); - #endif - #ifdef __arm__ - int j; - printf("TRACE: %x \n",(&j)[10]); - printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]); - #endif - //fflush(stdout); + if(a0==1&&a1==0) { + // must swap + emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0); + } + else if(a0!=0&&a1==0) { + emit_mov(a1,1); + if (a0>=0) emit_mov(a0,0); + } + else { + if(a0>=0&&a0!=0) emit_mov(a0,0); + if(a1>=0&&a1!=1) emit_mov(a1,1); } - //printf("TRACE: %x\n",(&i)[-1]); -} - -void tlb_debug(u_int cause, u_int addr, u_int iaddr) -{ - printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause); } -void alu_assemble(int i,struct regstat *i_regs) +static void alu_assemble(int i,struct regstat *i_regs) { if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU if(rt1[i]) { @@ -2230,125 +2043,24 @@ void alu_assemble(int i,struct regstat *i_regs) } } if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU + assert(0); + } + if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU if(rt1[i]) { - signed char s1l,s2l,s1h,s2h,tl,th; - tl=get_reg(i_regs->regmap,rt1[i]); - th=get_reg(i_regs->regmap,rt1[i]|64); - if(tl>=0) { - s1l=get_reg(i_regs->regmap,rs1[i]); - s2l=get_reg(i_regs->regmap,rs2[i]); - s1h=get_reg(i_regs->regmap,rs1[i]|64); - s2h=get_reg(i_regs->regmap,rs2[i]|64); - if(rs1[i]&&rs2[i]) { - assert(s1l>=0); - assert(s2l>=0); - if(opcode2[i]&2) emit_subs(s1l,s2l,tl); - else emit_adds(s1l,s2l,tl); - if(th>=0) { - #ifdef INVERTED_CARRY - if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);} - #else - if(opcode2[i]&2) emit_sbc(s1h,s2h,th); - #endif - else emit_add(s1h,s2h,th); - } - } - else if(rs1[i]) { - if(s1l>=0) emit_mov(s1l,tl); - else emit_loadreg(rs1[i],tl); - if(th>=0) { - if(s1h>=0) emit_mov(s1h,th); - else emit_loadreg(rs1[i]|64,th); - } - } - else if(rs2[i]) { - if(s2l>=0) { - if(opcode2[i]&2) emit_negs(s2l,tl); - else emit_mov(s2l,tl); - } - else { - emit_loadreg(rs2[i],tl); - if(opcode2[i]&2) emit_negs(tl,tl); - } - if(th>=0) { - #ifdef INVERTED_CARRY - if(s2h>=0) emit_mov(s2h,th); - else emit_loadreg(rs2[i]|64,th); - if(opcode2[i]&2) { - emit_adcimm(-1,th); // x86 has inverted carry flag - emit_not(th,th); - } - #else - if(opcode2[i]&2) { - if(s2h>=0) emit_rscimm(s2h,0,th); - else { - emit_loadreg(rs2[i]|64,th); - emit_rscimm(th,0,th); - } - }else{ - if(s2h>=0) emit_mov(s2h,th); - else emit_loadreg(rs2[i]|64,th); - } - #endif - } - } - else { - emit_zeroreg(tl); - if(th>=0) emit_zeroreg(th); - } - } - } - } - if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU - if(rt1[i]) { - signed char s1l,s1h,s2l,s2h,t; - if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)) - { - t=get_reg(i_regs->regmap,rt1[i]); - //assert(t>=0); - if(t>=0) { - s1l=get_reg(i_regs->regmap,rs1[i]); - s1h=get_reg(i_regs->regmap,rs1[i]|64); - s2l=get_reg(i_regs->regmap,rs2[i]); - s2h=get_reg(i_regs->regmap,rs2[i]|64); - if(rs2[i]==0) // rx=0); - if(opcode2[i]==0x2a) // SLT - emit_shrimm(s1h,31,t); - else // SLTU (unsigned can not be less than zero) - emit_zeroreg(t); - } - else if(rs1[i]==0) // r0=0); - if(opcode2[i]==0x2a) // SLT - emit_set_gz64_32(s2h,s2l,t); - else // SLTU (set if not zero) - emit_set_nz64_32(s2h,s2l,t); - } - else { - assert(s1l>=0);assert(s1h>=0); - assert(s2l>=0);assert(s2h>=0); - if(opcode2[i]==0x2a) // SLT - emit_set_if_less64_32(s1h,s1l,s2h,s2l,t); - else // SLTU - emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t); - } - } - } else { - t=get_reg(i_regs->regmap,rt1[i]); - //assert(t>=0); - if(t>=0) { - s1l=get_reg(i_regs->regmap,rs1[i]); - s2l=get_reg(i_regs->regmap,rs2[i]); - if(rs2[i]==0) // rx=0); - if(opcode2[i]==0x2a) // SLT - emit_shrimm(s1l,31,t); - else // SLTU (unsigned can not be less than zero) - emit_zeroreg(t); + signed char s1l,s2l,t; + { + t=get_reg(i_regs->regmap,rt1[i]); + //assert(t>=0); + if(t>=0) { + s1l=get_reg(i_regs->regmap,rs1[i]); + s2l=get_reg(i_regs->regmap,rs2[i]); + if(rs2[i]==0) // rx=0); + if(opcode2[i]==0x2a) // SLT + emit_shrimm(s1l,31,t); + else // SLTU (unsigned can not be less than zero) + emit_zeroreg(t); } else if(rs1[i]==0) // r0=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR if(rt1[i]) { - signed char s1l,s1h,s2l,s2h,th,tl; + signed char s1l,s2l,tl; tl=get_reg(i_regs->regmap,rt1[i]); - th=get_reg(i_regs->regmap,rt1[i]|64); - if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0) - { - assert(tl>=0); - if(tl>=0) { - s1l=get_reg(i_regs->regmap,rs1[i]); - s1h=get_reg(i_regs->regmap,rs1[i]|64); - s2l=get_reg(i_regs->regmap,rs2[i]); - s2h=get_reg(i_regs->regmap,rs2[i]|64); - if(rs1[i]&&rs2[i]) { - assert(s1l>=0);assert(s1h>=0); - assert(s2l>=0);assert(s2h>=0); - if(opcode2[i]==0x24) { // AND - emit_and(s1l,s2l,tl); - emit_and(s1h,s2h,th); - } else - if(opcode2[i]==0x25) { // OR - emit_or(s1l,s2l,tl); - emit_or(s1h,s2h,th); - } else - if(opcode2[i]==0x26) { // XOR - emit_xor(s1l,s2l,tl); - emit_xor(s1h,s2h,th); - } else - if(opcode2[i]==0x27) { // NOR - emit_or(s1l,s2l,tl); - emit_or(s1h,s2h,th); - emit_not(tl,tl); - emit_not(th,th); - } - } - else - { - if(opcode2[i]==0x24) { // AND - emit_zeroreg(tl); - emit_zeroreg(th); - } else - if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR - if(rs1[i]){ - if(s1l>=0) emit_mov(s1l,tl); - else emit_loadreg(rs1[i],tl); - if(s1h>=0) emit_mov(s1h,th); - else emit_loadreg(rs1[i]|64,th); - } - else - if(rs2[i]){ - if(s2l>=0) emit_mov(s2l,tl); - else emit_loadreg(rs2[i],tl); - if(s2h>=0) emit_mov(s2h,th); - else emit_loadreg(rs2[i]|64,th); - } - else{ - emit_zeroreg(tl); - emit_zeroreg(th); - } - } else - if(opcode2[i]==0x27) { // NOR - if(rs1[i]){ - if(s1l>=0) emit_not(s1l,tl); - else{ - emit_loadreg(rs1[i],tl); - emit_not(tl,tl); - } - if(s1h>=0) emit_not(s1h,th); - else{ - emit_loadreg(rs1[i]|64,th); - emit_not(th,th); - } - } - else - if(rs2[i]){ - if(s2l>=0) emit_not(s2l,tl); - else{ - emit_loadreg(rs2[i],tl); - emit_not(tl,tl); - } - if(s2h>=0) emit_not(s2h,th); - else{ - emit_loadreg(rs2[i]|64,th); - emit_not(th,th); - } - } - else { - emit_movimm(-1,tl); - emit_movimm(-1,th); - } - } - } - } - } - else { - // 32 bit if(tl>=0) { s1l=get_reg(i_regs->regmap,rs1[i]); s2l=get_reg(i_regs->regmap,rs2[i]); @@ -2572,24 +2192,15 @@ void imm16_assemble(int i,struct regstat *i_regs) } if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU if(rt1[i]) { - signed char sh,sl,th,tl; - th=get_reg(i_regs->regmap,rt1[i]|64); + signed char sl,tl; tl=get_reg(i_regs->regmap,rt1[i]); - sh=get_reg(i_regs->regmap,rs1[i]|64); sl=get_reg(i_regs->regmap,rs1[i]); if(tl>=0) { if(rs1[i]) { - assert(sh>=0); assert(sl>=0); - if(th>=0) { - emit_addimm64_32(sh,sl,imm[i],th,tl); - } - else { - emit_addimm(sl,imm[i],tl); - } + emit_addimm(sl,imm[i],tl); } else { emit_movimm(imm[i],tl); - if(th>=0) emit_movimm(((signed int)imm[i])>>31,th); } } } @@ -2597,15 +2208,12 @@ void imm16_assemble(int i,struct regstat *i_regs) else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU if(rt1[i]) { //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug - signed char sh,sl,t; + signed char sl,t; t=get_reg(i_regs->regmap,rt1[i]); - sh=get_reg(i_regs->regmap,rs1[i]|64); sl=get_reg(i_regs->regmap,rs1[i]); //assert(t>=0); if(t>=0) { if(rs1[i]>0) { - if(sh<0) assert((i_regs->was32>>rs1[i])&1); - if(sh<0||((i_regs->was32>>rs1[i])&1)) { if(opcode[i]==0x0a) { // SLTI if(sl<0) { if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t); @@ -2622,13 +2230,6 @@ void imm16_assemble(int i,struct regstat *i_regs) emit_sltiu32(sl,imm[i],t); } } - }else{ // 64-bit - assert(sl>=0); - if(opcode[i]==0x0a) // SLTI - emit_slti64_32(sh,sl,imm[i],t); - else // SLTIU - emit_sltiu64_32(sh,sl,imm[i],t); - } }else{ // SLTI(U) with r0 is just stupid, // nonetheless examples can be found @@ -2646,10 +2247,8 @@ void imm16_assemble(int i,struct regstat *i_regs) } else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI if(rt1[i]) { - signed char sh,sl,th,tl; - th=get_reg(i_regs->regmap,rt1[i]|64); + signed char sl,tl; tl=get_reg(i_regs->regmap,rt1[i]); - sh=get_reg(i_regs->regmap,rs1[i]|64); sl=get_reg(i_regs->regmap,rs1[i]); if(tl>=0 && !((i_regs->isconst>>tl)&1)) { if(opcode[i]==0x0c) //ANDI @@ -2667,7 +2266,6 @@ void imm16_assemble(int i,struct regstat *i_regs) } else emit_zeroreg(tl); - if(th>=0) emit_zeroreg(th); } else { @@ -2675,35 +2273,29 @@ void imm16_assemble(int i,struct regstat *i_regs) if(sl<0) { if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl); } - if(th>=0) { - if(sh<0) { - emit_loadreg(rs1[i]|64,th); + if(opcode[i]==0x0d) { // ORI + if(sl<0) { + emit_orimm(tl,imm[i],tl); }else{ - emit_mov(sh,th); + if(!((i_regs->wasconst>>sl)&1)) + emit_orimm(sl,imm[i],tl); + else + emit_movimm(constmap[i][sl]|imm[i],tl); } } - if(opcode[i]==0x0d) //ORI - if(sl<0) { - emit_orimm(tl,imm[i],tl); - }else{ - if(!((i_regs->wasconst>>sl)&1)) - emit_orimm(sl,imm[i],tl); - else - emit_movimm(constmap[i][sl]|imm[i],tl); - } - if(opcode[i]==0x0e) //XORI - if(sl<0) { - emit_xorimm(tl,imm[i],tl); - }else{ - if(!((i_regs->wasconst>>sl)&1)) - emit_xorimm(sl,imm[i],tl); - else - emit_movimm(constmap[i][sl]^imm[i],tl); + if(opcode[i]==0x0e) { // XORI + if(sl<0) { + emit_xorimm(tl,imm[i],tl); + }else{ + if(!((i_regs->wasconst>>sl)&1)) + emit_xorimm(sl,imm[i],tl); + else + emit_movimm(constmap[i][sl]^imm[i],tl); + } } } else { emit_movimm(imm[i],tl); - if(th>=0) emit_zeroreg(th); } } } @@ -2752,120 +2344,194 @@ void shiftimm_assemble(int i,struct regstat *i_regs) } if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA { - if(rt1[i]) { - signed char sh,sl,th,tl; - th=get_reg(i_regs->regmap,rt1[i]|64); - tl=get_reg(i_regs->regmap,rt1[i]); - sh=get_reg(i_regs->regmap,rs1[i]|64); - sl=get_reg(i_regs->regmap,rs1[i]); - if(tl>=0) { - if(rs1[i]==0) - { - emit_zeroreg(tl); - if(th>=0) emit_zeroreg(th); - } - else - { - assert(sl>=0); - assert(sh>=0); - if(imm[i]) { - if(opcode2[i]==0x38) // DSLL - { - if(th>=0) emit_shldimm(sh,sl,imm[i],th); - emit_shlimm(sl,imm[i],tl); - } - if(opcode2[i]==0x3a) // DSRL - { - emit_shrdimm(sl,sh,imm[i],tl); - if(th>=0) emit_shrimm(sh,imm[i],th); - } - if(opcode2[i]==0x3b) // DSRA - { - emit_shrdimm(sl,sh,imm[i],tl); - if(th>=0) emit_sarimm(sh,imm[i],th); - } - }else{ - // Shift by zero - if(sl!=tl) emit_mov(sl,tl); - if(th>=0&&sh!=th) emit_mov(sh,th); - } - } - } - } + assert(0); } if(opcode2[i]==0x3c) // DSLL32 { - if(rt1[i]) { - signed char sl,tl,th; - tl=get_reg(i_regs->regmap,rt1[i]); - th=get_reg(i_regs->regmap,rt1[i]|64); - sl=get_reg(i_regs->regmap,rs1[i]); - if(th>=0||tl>=0){ - assert(tl>=0); - assert(th>=0); - assert(sl>=0); - emit_mov(sl,th); - emit_zeroreg(tl); - if(imm[i]>32) - { - emit_shlimm(th,imm[i]&31,th); - } - } - } + assert(0); } if(opcode2[i]==0x3e) // DSRL32 { - if(rt1[i]) { - signed char sh,tl,th; - tl=get_reg(i_regs->regmap,rt1[i]); - th=get_reg(i_regs->regmap,rt1[i]|64); - sh=get_reg(i_regs->regmap,rs1[i]|64); - if(tl>=0){ - assert(sh>=0); - emit_mov(sh,tl); - if(th>=0) emit_zeroreg(th); - if(imm[i]>32) - { - emit_shrimm(tl,imm[i]&31,tl); - } - } - } + assert(0); } if(opcode2[i]==0x3f) // DSRA32 { - if(rt1[i]) { - signed char sh,tl; - tl=get_reg(i_regs->regmap,rt1[i]); - sh=get_reg(i_regs->regmap,rs1[i]|64); - if(tl>=0){ - assert(sh>=0); - emit_mov(sh,tl); - if(imm[i]>32) - { - emit_sarimm(tl,imm[i]&31,tl); - } - } - } + assert(0); } } #ifndef shift_assemble -void shift_assemble(int i,struct regstat *i_regs) +static void shift_assemble(int i,struct regstat *i_regs) { - printf("Need shift_assemble for this architecture.\n"); - exit(1); + signed char s,t,shift; + if (rt1[i] == 0) + return; + assert(opcode2[i]<=0x07); // SLLV/SRLV/SRAV + t = get_reg(i_regs->regmap, rt1[i]); + s = get_reg(i_regs->regmap, rs1[i]); + shift = get_reg(i_regs->regmap, rs2[i]); + if (t < 0) + return; + + if(rs1[i]==0) + emit_zeroreg(t); + else if(rs2[i]==0) { + assert(s>=0); + if(s!=t) emit_mov(s,t); + } + else { + host_tempreg_acquire(); + emit_andimm(shift,31,HOST_TEMPREG); + switch(opcode2[i]) { + case 4: // SLLV + emit_shl(s,HOST_TEMPREG,t); + break; + case 6: // SRLV + emit_shr(s,HOST_TEMPREG,t); + break; + case 7: // SRAV + emit_sar(s,HOST_TEMPREG,t); + break; + default: + assert(0); + } + host_tempreg_release(); + } } + #endif -void load_assemble(int i,struct regstat *i_regs) +enum { + MTYPE_8000 = 0, + MTYPE_8020, + MTYPE_0000, + MTYPE_A000, + MTYPE_1F80, +}; + +static int get_ptr_mem_type(u_int a) +{ + if(a < 0x00200000) { + if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0)) + // return wrong, must use memhandler for BIOS self-test to pass + // 007 does similar stuff from a00 mirror, weird stuff + return MTYPE_8000; + return MTYPE_0000; + } + if(0x1f800000 <= a && a < 0x1f801000) + return MTYPE_1F80; + if(0x80200000 <= a && a < 0x80800000) + return MTYPE_8020; + if(0xa0000000 <= a && a < 0xa0200000) + return MTYPE_A000; + return MTYPE_8000; +} + +static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override) { - int s,th,tl,addr,map=-1; + void *jaddr = NULL; + int type=0; + int mr=rs1[i]; + if(((smrv_strong|smrv_weak)>>mr)&1) { + type=get_ptr_mem_type(smrv[mr]); + //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type); + } + else { + // use the mirror we are running on + type=get_ptr_mem_type(start); + //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type); + } + + if(type==MTYPE_8020) { // RAM 80200000+ mirror + host_tempreg_acquire(); + emit_andimm(addr,~0x00e00000,HOST_TEMPREG); + addr=*addr_reg_override=HOST_TEMPREG; + type=0; + } + else if(type==MTYPE_0000) { // RAM 0 mirror + host_tempreg_acquire(); + emit_orimm(addr,0x80000000,HOST_TEMPREG); + addr=*addr_reg_override=HOST_TEMPREG; + type=0; + } + else if(type==MTYPE_A000) { // RAM A mirror + host_tempreg_acquire(); + emit_andimm(addr,~0x20000000,HOST_TEMPREG); + addr=*addr_reg_override=HOST_TEMPREG; + type=0; + } + else if(type==MTYPE_1F80) { // scratchpad + if (psxH == (void *)0x1f800000) { + host_tempreg_acquire(); + emit_xorimm(addr,0x1f800000,HOST_TEMPREG); + emit_cmpimm(HOST_TEMPREG,0x1000); + host_tempreg_release(); + jaddr=out; + emit_jc(0); + } + else { + // do the usual RAM check, jump will go to the right handler + type=0; + } + } + + if(type==0) + { + emit_cmpimm(addr,RAM_SIZE); + jaddr=out; + #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK + // Hint to branch predictor that the branch is unlikely to be taken + if(rs1[i]>=28) + emit_jno_unlikely(0); + else + #endif + emit_jno(0); + if(ram_offset!=0) { + host_tempreg_acquire(); + emit_addimm(addr,ram_offset,HOST_TEMPREG); + addr=*addr_reg_override=HOST_TEMPREG; + } + } + + return jaddr; +} + +// return memhandler, or get directly accessable address and return 0 +static void *get_direct_memhandler(void *table, u_int addr, + enum stub_type type, uintptr_t *addr_host) +{ + uintptr_t l1, l2 = 0; + l1 = ((uintptr_t *)table)[addr>>12]; + if ((l1 & (1ul << (sizeof(l1)*8-1))) == 0) { + uintptr_t v = l1 << 1; + *addr_host = v + addr; + return NULL; + } + else { + l1 <<= 1; + if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB) + l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)]; + else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB) + l2=((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2]; + else + l2=((uintptr_t *)l1)[(addr&0xfff)/4]; + if ((l2 & (1<<31)) == 0) { + uintptr_t v = l2 << 1; + *addr_host = v + (addr&0xfff); + return NULL; + } + return (void *)(l2 << 1); + } +} + +static void load_assemble(int i,struct regstat *i_regs) +{ + int s,tl,addr; int offset; - int jaddr=0; + void *jaddr=0; int memtarget=0,c=0; - int fastload_reg_override=0; + int fastio_reg_override=-1; u_int hr,reglist=0; - th=get_reg(i_regs->regmap,rt1[i]|64); tl=get_reg(i_regs->regmap,rt1[i]); s=get_reg(i_regs->regmap,rs1[i]); offset=imm[i]; @@ -2877,14 +2543,12 @@ void load_assemble(int i,struct regstat *i_regs) c=(i_regs->wasconst>>s)&1; if (c) { memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; - if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1; } } //printf("load_assemble: c=%d\n",c); - //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset); + //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset); // FIXME: Even if the load is a NOP, we should check for pagefaults... -#ifdef PCSX - if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80) + if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)) ||rt1[i]==0) { // could be FIFO, must perform the read // ||dummy read @@ -2892,68 +2556,42 @@ void load_assemble(int i,struct regstat *i_regs) tl=get_reg(i_regs->regmap,-1); assert(tl>=0); } -#endif if(offset||s<0||c) addr=tl; else addr=s; //if(tl<0) tl=get_reg(i_regs->regmap,-1); if(tl>=0) { //printf("load_assemble: c=%d\n",c); - //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset); + //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset); assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O reglist&=~(1<=0) reglist&=~(1<regmap,ROREG); - if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG); - #endif -//#define R29_HACK 1 - #ifdef R29_HACK - // Strmnnrmn's speed hack - if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE) - #endif - { - jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override); - } + if(!c) { + #ifdef R29_HACK + // Strmnnrmn's speed hack + if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE) + #endif + { + jaddr=emit_fastpath_cmp_jump(i,addr,&fastio_reg_override); } - }else{ // using tlb - int x=0; - if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU - if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU - map=get_reg(i_regs->regmap,TLREG); - assert(map>=0); - reglist&=~(1<regmap,rt1[i])); // ignore loads to r0 and unneeded reg if (opcode[i]==0x20) { // LB if(!c||memtarget) { if(!dummy) { - #ifdef HOST_IMM_ADDR32 - if(c) - emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl); - else - #endif { - //emit_xorimm(addr,3,tl); - //gen_tlb_addr_r(tl,map); - //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl); int x=0,a=tl; -#ifdef BIG_ENDIAN_MIPS - if(!c) emit_xorimm(addr,3,tl); - else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset); -#else if(!c) a=addr; -#endif - if(fastload_reg_override) a=fastload_reg_override; + if(fastio_reg_override>=0) a=fastio_reg_override; - emit_movsbl_indexed_tlb(x,a,map,tl); + emit_movsbl_indexed(x,a,tl); } } if(jaddr) - add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); + add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); } else inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); @@ -2961,37 +2599,13 @@ void load_assemble(int i,struct regstat *i_regs) if (opcode[i]==0x21) { // LH if(!c||memtarget) { if(!dummy) { - #ifdef HOST_IMM_ADDR32 - if(c) - emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl); - else - #endif - { - int x=0,a=tl; -#ifdef BIG_ENDIAN_MIPS - if(!c) emit_xorimm(addr,2,tl); - else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset); -#else - if(!c) a=addr; -#endif - if(fastload_reg_override) a=fastload_reg_override; - //#ifdef - //emit_movswl_indexed_tlb(x,tl,map,tl); - //else - if(map>=0) { - gen_tlb_addr_r(a,map); - emit_movswl_indexed(x,a,tl); - }else{ - #ifdef RAM_OFFSET - emit_movswl_indexed(x,a,tl); - #else - emit_movswl_indexed((int)rdram-0x80000000+x,a,tl); - #endif - } - } + int x=0,a=tl; + if(!c) a=addr; + if(fastio_reg_override>=0) a=fastio_reg_override; + emit_movswl_indexed(x,a,tl); } if(jaddr) - add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); + add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); } else inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); @@ -3000,17 +2614,11 @@ void load_assemble(int i,struct regstat *i_regs) if(!c||memtarget) { if(!dummy) { int a=addr; - if(fastload_reg_override) a=fastload_reg_override; - //emit_readword_indexed((int)rdram-0x80000000,addr,tl); - #ifdef HOST_IMM_ADDR32 - if(c) - emit_readword_tlb(constmap[i][s]+offset,map,tl); - else - #endif - emit_readword_indexed_tlb(0,a,map,tl); + if(fastio_reg_override>=0) a=fastio_reg_override; + emit_readword_indexed(0,a,tl); } if(jaddr) - add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); + add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); } else inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); @@ -3018,29 +2626,14 @@ void load_assemble(int i,struct regstat *i_regs) if (opcode[i]==0x24) { // LBU if(!c||memtarget) { if(!dummy) { - #ifdef HOST_IMM_ADDR32 - if(c) - emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl); - else - #endif - { - //emit_xorimm(addr,3,tl); - //gen_tlb_addr_r(tl,map); - //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl); - int x=0,a=tl; -#ifdef BIG_ENDIAN_MIPS - if(!c) emit_xorimm(addr,3,tl); - else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset); -#else - if(!c) a=addr; -#endif - if(fastload_reg_override) a=fastload_reg_override; + int x=0,a=tl; + if(!c) a=addr; + if(fastio_reg_override>=0) a=fastio_reg_override; - emit_movzbl_indexed_tlb(x,a,map,tl); - } + emit_movzbl_indexed(x,a,tl); } if(jaddr) - add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); + add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); } else inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); @@ -3048,135 +2641,123 @@ void load_assemble(int i,struct regstat *i_regs) if (opcode[i]==0x25) { // LHU if(!c||memtarget) { if(!dummy) { - #ifdef HOST_IMM_ADDR32 - if(c) - emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl); - else - #endif - { - int x=0,a=tl; -#ifdef BIG_ENDIAN_MIPS - if(!c) emit_xorimm(addr,2,tl); - else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset); -#else - if(!c) a=addr; -#endif - if(fastload_reg_override) a=fastload_reg_override; - //#ifdef - //emit_movzwl_indexed_tlb(x,tl,map,tl); - //#else - if(map>=0) { - gen_tlb_addr_r(a,map); - emit_movzwl_indexed(x,a,tl); - }else{ - #ifdef RAM_OFFSET - emit_movzwl_indexed(x,a,tl); - #else - emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl); - #endif - } - } + int x=0,a=tl; + if(!c) a=addr; + if(fastio_reg_override>=0) a=fastio_reg_override; + emit_movzwl_indexed(x,a,tl); } if(jaddr) - add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); + add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); } else inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); } if (opcode[i]==0x27) { // LWU - assert(th>=0); - if(!c||memtarget) { - if(!dummy) { - int a=addr; - if(fastload_reg_override) a=fastload_reg_override; - //emit_readword_indexed((int)rdram-0x80000000,addr,tl); - #ifdef HOST_IMM_ADDR32 - if(c) - emit_readword_tlb(constmap[i][s]+offset,map,tl); - else - #endif - emit_readword_indexed_tlb(0,a,map,tl); - } - if(jaddr) - add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); - } - else { - inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); - } - emit_zeroreg(th); + assert(0); } if (opcode[i]==0x37) { // LD - if(!c||memtarget) { - if(!dummy) { - int a=addr; - if(fastload_reg_override) a=fastload_reg_override; - //gen_tlb_addr_r(tl,map); - //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th); - //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl); - #ifdef HOST_IMM_ADDR32 - if(c) - emit_readdword_tlb(constmap[i][s]+offset,map,th,tl); - else - #endif - emit_readdword_indexed_tlb(0,a,map,th,tl); - } - if(jaddr) - add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist); - } - else - inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist); + assert(0); } } - //emit_storereg(rt1[i],tl); // DEBUG - //if(opcode[i]==0x23) - //if(opcode[i]==0x24) - //if(opcode[i]==0x23||opcode[i]==0x24) - /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24) - { - //emit_pusha(); - save_regs(0x100f); - emit_readword((int)&last_count,ECX); - #ifdef __i386__ - if(get_reg(i_regs->regmap,CCREG)<0) - emit_loadreg(CCREG,HOST_CCREG); - emit_add(HOST_CCREG,ECX,HOST_CCREG); - emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); - emit_writeword(HOST_CCREG,(int)&Count); - #endif - #ifdef __arm__ - if(get_reg(i_regs->regmap,CCREG)<0) - emit_loadreg(CCREG,0); - else - emit_mov(HOST_CCREG,0); - emit_add(0,ECX,0); - emit_addimm(0,2*ccadj[i],0); - emit_writeword(0,(int)&Count); - #endif - emit_call((int)memdebug); - //emit_popa(); - restore_regs(0x100f); - }/**/ + if (fastio_reg_override == HOST_TEMPREG) + host_tempreg_release(); } #ifndef loadlr_assemble -void loadlr_assemble(int i,struct regstat *i_regs) +static void loadlr_assemble(int i,struct regstat *i_regs) { - printf("Need loadlr_assemble for this architecture.\n"); - exit(1); + int s,tl,temp,temp2,addr; + int offset; + void *jaddr=0; + int memtarget=0,c=0; + int fastio_reg_override=-1; + u_int hr,reglist=0; + tl=get_reg(i_regs->regmap,rt1[i]); + s=get_reg(i_regs->regmap,rs1[i]); + temp=get_reg(i_regs->regmap,-1); + temp2=get_reg(i_regs->regmap,FTEMP); + addr=get_reg(i_regs->regmap,AGEN1+(i&1)); + assert(addr<0); + offset=imm[i]; + for(hr=0;hrregmap[hr]>=0) reglist|=1<=0) { + c=(i_regs->wasconst>>s)&1; + if(c) { + memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; + } + } + if(!c) { + emit_shlimm(addr,3,temp); + if (opcode[i]==0x22||opcode[i]==0x26) { + emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR + }else{ + emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR + } + jaddr=emit_fastpath_cmp_jump(i,temp2,&fastio_reg_override); + } + else { + if(ram_offset&&memtarget) { + host_tempreg_acquire(); + emit_addimm(temp2,ram_offset,HOST_TEMPREG); + fastio_reg_override=HOST_TEMPREG; + } + if (opcode[i]==0x22||opcode[i]==0x26) { + emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR + }else{ + emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR + } + } + if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR + if(!c||memtarget) { + int a=temp2; + if(fastio_reg_override>=0) a=fastio_reg_override; + emit_readword_indexed(0,a,temp2); + if(fastio_reg_override==HOST_TEMPREG) host_tempreg_release(); + if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj[i],reglist); + } + else + inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist); + if(rt1[i]) { + assert(tl>=0); + emit_andimm(temp,24,temp); + if (opcode[i]==0x22) // LWL + emit_xorimm(temp,24,temp); + host_tempreg_acquire(); + emit_movimm(-1,HOST_TEMPREG); + if (opcode[i]==0x26) { + emit_shr(temp2,temp,temp2); + emit_bic_lsr(tl,HOST_TEMPREG,temp,tl); + }else{ + emit_shl(temp2,temp,temp2); + emit_bic_lsl(tl,HOST_TEMPREG,temp,tl); + } + host_tempreg_release(); + emit_or(temp2,tl,tl); + } + //emit_storereg(rt1[i],tl); // DEBUG + } + if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR + assert(0); + } } #endif void store_assemble(int i,struct regstat *i_regs) { - int s,th,tl,map=-1; + int s,tl; int addr,temp; int offset; - int jaddr=0,jaddr2,type; + void *jaddr=0; + enum stub_type type; int memtarget=0,c=0; int agr=AGEN1+(i&1); - int faststore_reg_override=0; + int fastio_reg_override=-1; u_int hr,reglist=0; - th=get_reg(i_regs->regmap,rs2[i]|64); tl=get_reg(i_regs->regmap,rs2[i]); s=get_reg(i_regs->regmap,rs1[i]); temp=get_reg(i_regs->regmap,agr); @@ -3186,7 +2767,6 @@ void store_assemble(int i,struct regstat *i_regs) c=(i_regs->wasconst>>s)&1; if(c) { memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; - if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1; } } assert(tl>=0); @@ -3197,119 +2777,54 @@ void store_assemble(int i,struct regstat *i_regs) if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<=0x80000000+RAM_SIZE) - #endif - emit_cmpimm(addr,RAM_SIZE); - #ifdef DESTRUCTIVE_SHIFT - if(s==addr) emit_mov(s,temp); - #endif - #ifdef R29_HACK - memtarget=1; - if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE) - #endif - { - jaddr=(int)out; - #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK - // Hint to branch predictor that the branch is unlikely to be taken - if(rs1[i]>=28) - emit_jno_unlikely(0); - else - #endif - emit_jno(0); - } - #else - jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override); - #endif - } - }else{ // using tlb - int x=0; - if (opcode[i]==0x28) x=3; // SB - if (opcode[i]==0x29) x=2; // SH - map=get_reg(i_regs->regmap,TLREG); - assert(map>=0); - reglist&=~(1<=0) a=fastio_reg_override; + emit_writebyte_indexed(tl,x,a); } type=STOREB_STUB; } if (opcode[i]==0x29) { // SH if(!c||memtarget) { int x=0,a=temp; -#ifdef BIG_ENDIAN_MIPS - if(!c) emit_xorimm(addr,2,temp); - else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset); -#else if(!c) a=addr; -#endif - if(faststore_reg_override) a=faststore_reg_override; - //#ifdef - //emit_writehword_indexed_tlb(tl,x,temp,map,temp); - //#else - if(map>=0) { - gen_tlb_addr_w(a,map); - emit_writehword_indexed(tl,x,a); - }else - emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a); + if(fastio_reg_override>=0) a=fastio_reg_override; + emit_writehword_indexed(tl,x,a); } type=STOREH_STUB; } if (opcode[i]==0x2B) { // SW if(!c||memtarget) { int a=addr; - if(faststore_reg_override) a=faststore_reg_override; - //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr); - emit_writeword_indexed_tlb(tl,0,a,map,temp); + if(fastio_reg_override>=0) a=fastio_reg_override; + emit_writeword_indexed(tl,0,a); } type=STOREW_STUB; } if (opcode[i]==0x3F) { // SD - if(!c||memtarget) { - int a=addr; - if(faststore_reg_override) a=faststore_reg_override; - if(rs2[i]) { - assert(th>=0); - //emit_writeword_indexed(th,(int)rdram-0x80000000,addr); - //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr); - emit_writedword_indexed_tlb(th,tl,0,a,map,temp); - }else{ - // Store zero - //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp); - //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp); - emit_writedword_indexed_tlb(tl,tl,0,a,map,temp); - } - } + assert(0); type=STORED_STUB; } -#ifdef PCSX + if(fastio_reg_override==HOST_TEMPREG) + host_tempreg_release(); if(jaddr) { // PCSX store handlers don't check invcode again reglist|=1<waswritten&(1<waswritten&(1<=0); emit_cmpmem_indexedsr12_reg(ir,addr,1); #else - emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1); + emit_cmpmem_indexedsr12_imm(invalid_code,addr,1); #endif #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) emit_callne(invalidate_addr_reg[addr]); #else - jaddr2=(int)out; + void *jaddr2 = out; emit_jne(0); - add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<regmap,rs2[i],ccadj[i],reglist); + inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist); + } + // basic current block modification detection.. + // not looking back as that should be in mips cache already + // (see Spyro2 title->attract mode) + if(c&&start+i*4regmap==regs[i].regmap); // not delay slot + if(i_regs->regmap==regs[i].regmap) { + load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i); + wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty); + emit_movimm(start+i*4+4,0); + emit_writeword(0,&pcaddr); + emit_addimm(HOST_CCREG,2,HOST_CCREG); + emit_call(get_addr_ht); + emit_jmpreg(0); + } } - //if(opcode[i]==0x2B || opcode[i]==0x3F) - //if(opcode[i]==0x2B || opcode[i]==0x28) - //if(opcode[i]==0x2B || opcode[i]==0x29) - //if(opcode[i]==0x2B) - /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F) - { - #ifdef __i386__ - emit_pusha(); - #endif - #ifdef __arm__ - save_regs(0x100f); - #endif - emit_readword((int)&last_count,ECX); - #ifdef __i386__ - if(get_reg(i_regs->regmap,CCREG)<0) - emit_loadreg(CCREG,HOST_CCREG); - emit_add(HOST_CCREG,ECX,HOST_CCREG); - emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); - emit_writeword(HOST_CCREG,(int)&Count); - #endif - #ifdef __arm__ - if(get_reg(i_regs->regmap,CCREG)<0) - emit_loadreg(CCREG,0); - else - emit_mov(HOST_CCREG,0); - emit_add(0,ECX,0); - emit_addimm(0,2*ccadj[i],0); - emit_writeword(0,(int)&Count); - #endif - emit_call((int)memdebug); - #ifdef __i386__ - emit_popa(); - #endif - #ifdef __arm__ - restore_regs(0x100f); - #endif - }/**/ } -void storelr_assemble(int i,struct regstat *i_regs) +static void storelr_assemble(int i,struct regstat *i_regs) { - int s,th,tl; + int s,tl; int temp; - int temp2; int offset; - int jaddr=0,jaddr2; - int case1,case2,case3; - int done0,done1,done2; + void *jaddr=0; + void *case1, *case2, *case3; + void *done0, *done1, *done2; int memtarget=0,c=0; int agr=AGEN1+(i&1); u_int hr,reglist=0; - th=get_reg(i_regs->regmap,rs2[i]|64); tl=get_reg(i_regs->regmap,rs2[i]); s=get_reg(i_regs->regmap,rs1[i]); temp=get_reg(i_regs->regmap,agr); @@ -3398,7 +2891,6 @@ void storelr_assemble(int i,struct regstat *i_regs) c=(i_regs->isconst>>s)&1; if(c) { memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; - if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1; } } assert(tl>=0); @@ -3406,75 +2898,46 @@ void storelr_assemble(int i,struct regstat *i_regs) if(i_regs->regmap[hr]>=0) reglist|=1<=0); - if(!using_tlb) { - if(!c) { - emit_cmpimm(s<0||offset?temp:s,RAM_SIZE); - if(!offset&&s!=temp) emit_mov(s,temp); - jaddr=(int)out; - emit_jno(0); - } - else - { - if(!memtarget||!rs1[i]) { - jaddr=(int)out; - emit_jmp(0); - } - } - #ifdef RAM_OFFSET - int map=get_reg(i_regs->regmap,ROREG); - if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG); - gen_tlb_addr_w(temp,map); - #else - if((u_int)rdram!=0x80000000) - emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp); - #endif - }else{ // using tlb - int map=get_reg(i_regs->regmap,TLREG); - assert(map>=0); - reglist&=~(1<=0) emit_mov(s,temp); - do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr); - if(!jaddr&&!memtarget) { - jaddr=(int)out; + if(!c) { + emit_cmpimm(s<0||offset?temp:s,RAM_SIZE); + if(!offset&&s!=temp) emit_mov(s,temp); + jaddr=out; + emit_jno(0); + } + else + { + if(!memtarget||!rs1[i]) { + jaddr=out; emit_jmp(0); } - gen_tlb_addr_w(temp,map); } + if(ram_offset) + emit_addimm_no_flags(ram_offset,temp); if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR - temp2=get_reg(i_regs->regmap,FTEMP); - if(!rs2[i]) temp2=th=tl; + assert(0); } -#ifndef BIG_ENDIAN_MIPS - emit_xorimm(temp,3,temp); -#endif + emit_xorimm(temp,3,temp); emit_testimm(temp,2); - case2=(int)out; + case2=out; emit_jne(0); emit_testimm(temp,1); - case1=(int)out; + case1=out; emit_jne(0); // 0 if (opcode[i]==0x2A) { // SWL emit_writeword_indexed(tl,0,temp); } - if (opcode[i]==0x2E) { // SWR - emit_writebyte_indexed(tl,3,temp); - } - if (opcode[i]==0x2C) { // SDL - emit_writeword_indexed(th,0,temp); - if(rs2[i]) emit_mov(tl,temp2); - } - if (opcode[i]==0x2D) { // SDR + else if (opcode[i]==0x2E) { // SWR emit_writebyte_indexed(tl,3,temp); - if(rs2[i]) emit_shldimm(th,tl,24,temp2); } - done0=(int)out; + else + assert(0); + done0=out; emit_jmp(0); // 1 - set_jump_target(case1,(int)out); + set_jump_target(case1, out); if (opcode[i]==0x2A) { // SWL // Write 3 msb into three least significant bytes if(rs2[i]) emit_rorimm(tl,8,tl); @@ -3483,30 +2946,16 @@ void storelr_assemble(int i,struct regstat *i_regs) emit_writebyte_indexed(tl,1,temp); if(rs2[i]) emit_rorimm(tl,8,tl); } - if (opcode[i]==0x2E) { // SWR - // Write two lsb into two most significant bytes - emit_writehword_indexed(tl,1,temp); - } - if (opcode[i]==0x2C) { // SDL - if(rs2[i]) emit_shrdimm(tl,th,8,temp2); - // Write 3 msb into three least significant bytes - if(rs2[i]) emit_rorimm(th,8,th); - emit_writehword_indexed(th,-1,temp); - if(rs2[i]) emit_rorimm(th,16,th); - emit_writebyte_indexed(th,1,temp); - if(rs2[i]) emit_rorimm(th,8,th); - } - if (opcode[i]==0x2D) { // SDR - if(rs2[i]) emit_shldimm(th,tl,16,temp2); + else if (opcode[i]==0x2E) { // SWR // Write two lsb into two most significant bytes emit_writehword_indexed(tl,1,temp); } - done1=(int)out; + done1=out; emit_jmp(0); // 2 - set_jump_target(case2,(int)out); + set_jump_target(case2, out); emit_testimm(temp,1); - case3=(int)out; + case3=out; emit_jne(0); if (opcode[i]==0x2A) { // SWL // Write two msb into two least significant bytes @@ -3514,309 +2963,278 @@ void storelr_assemble(int i,struct regstat *i_regs) emit_writehword_indexed(tl,-2,temp); if(rs2[i]) emit_rorimm(tl,16,tl); } - if (opcode[i]==0x2E) { // SWR + else if (opcode[i]==0x2E) { // SWR // Write 3 lsb into three most significant bytes emit_writebyte_indexed(tl,-1,temp); if(rs2[i]) emit_rorimm(tl,8,tl); emit_writehword_indexed(tl,0,temp); if(rs2[i]) emit_rorimm(tl,24,tl); } - if (opcode[i]==0x2C) { // SDL - if(rs2[i]) emit_shrdimm(tl,th,16,temp2); - // Write two msb into two least significant bytes - if(rs2[i]) emit_rorimm(th,16,th); - emit_writehword_indexed(th,-2,temp); - if(rs2[i]) emit_rorimm(th,16,th); - } - if (opcode[i]==0x2D) { // SDR - if(rs2[i]) emit_shldimm(th,tl,8,temp2); - // Write 3 lsb into three most significant bytes - emit_writebyte_indexed(tl,-1,temp); - if(rs2[i]) emit_rorimm(tl,8,tl); - emit_writehword_indexed(tl,0,temp); - if(rs2[i]) emit_rorimm(tl,24,tl); - } - done2=(int)out; + done2=out; emit_jmp(0); // 3 - set_jump_target(case3,(int)out); + set_jump_target(case3, out); if (opcode[i]==0x2A) { // SWL // Write msb into least significant byte if(rs2[i]) emit_rorimm(tl,24,tl); emit_writebyte_indexed(tl,-3,temp); if(rs2[i]) emit_rorimm(tl,8,tl); } - if (opcode[i]==0x2E) { // SWR - // Write entire word - emit_writeword_indexed(tl,-3,temp); - } - if (opcode[i]==0x2C) { // SDL - if(rs2[i]) emit_shrdimm(tl,th,24,temp2); - // Write msb into least significant byte - if(rs2[i]) emit_rorimm(th,24,th); - emit_writebyte_indexed(th,-3,temp); - if(rs2[i]) emit_rorimm(th,8,th); - } - if (opcode[i]==0x2D) { // SDR - if(rs2[i]) emit_mov(th,temp2); + else if (opcode[i]==0x2E) { // SWR // Write entire word emit_writeword_indexed(tl,-3,temp); } - set_jump_target(done0,(int)out); - set_jump_target(done1,(int)out); - set_jump_target(done2,(int)out); - if (opcode[i]==0x2C) { // SDL - emit_testimm(temp,4); - done0=(int)out; - emit_jne(0); - emit_andimm(temp,~3,temp); - emit_writeword_indexed(temp2,4,temp); - set_jump_target(done0,(int)out); - } - if (opcode[i]==0x2D) { // SDR - emit_testimm(temp,4); - done0=(int)out; - emit_jeq(0); - emit_andimm(temp,~3,temp); - emit_writeword_indexed(temp2,-4,temp); - set_jump_target(done0,(int)out); - } + set_jump_target(done0, out); + set_jump_target(done1, out); + set_jump_target(done2, out); if(!c||!memtarget) - add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist); - if(!using_tlb&&!(i_regs->waswritten&(1<regmap,ROREG); - if(map<0) map=HOST_TEMPREG; - gen_orig_addr_w(temp,map); - #else - emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp); - #endif + add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj[i],reglist); + if(!(i_regs->waswritten&(1<regmap,INVCP); assert(ir>=0); emit_cmpmem_indexedsr12_reg(ir,temp,1); #else - emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1); + emit_cmpmem_indexedsr12_imm(invalid_code,temp,1); #endif #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) emit_callne(invalidate_addr_reg[temp]); #else - jaddr2=(int)out; + void *jaddr2 = out; emit_jne(0); - add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<regmap,CCREG)<0) - emit_loadreg(CCREG,HOST_CCREG); - emit_add(HOST_CCREG,ECX,HOST_CCREG); - emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); - emit_writeword(HOST_CCREG,(int)&Count); - emit_call((int)memdebug); - emit_popa(); - //restore_regs(0x100f); - /**/ } -void c1ls_assemble(int i,struct regstat *i_regs) +static void cop0_assemble(int i,struct regstat *i_regs) { -#ifndef DISABLE_COP1 - int s,th,tl; - int temp,ar; - int map=-1; - int offset; - int c=0; - int jaddr,jaddr2=0,jaddr3,type; - int agr=AGEN1+(i&1); - u_int hr,reglist=0; - th=get_reg(i_regs->regmap,FTEMP|64); - tl=get_reg(i_regs->regmap,FTEMP); - s=get_reg(i_regs->regmap,rs1[i]); - temp=get_reg(i_regs->regmap,agr); - if(temp<0) temp=get_reg(i_regs->regmap,-1); - offset=imm[i]; - assert(tl>=0); - assert(rs1[i]>0); - assert(temp>=0); - for(hr=0;hrregmap[hr]>=0) reglist|=1<regmap[HOST_CCREG]==CCREG) reglist&=~(1<wasconst>>s)&1; - if(s>=0) c=(i_regs->wasconst>>s)&1; - // Check cop1 unusable - if(!cop1_usable) { - signed char rs=get_reg(i_regs->regmap,CSREG); - assert(rs>=0); - emit_testimm(rs,0x20000000); - jaddr=(int)out; - emit_jeq(0); - add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0); - cop1_usable=1; - } - if (opcode[i]==0x39) { // SWC1 (get float address) - emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl); - } - if (opcode[i]==0x3D) { // SDC1 (get double address) - emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl); - } - // Generate address + offset - if(!using_tlb) { - if(!c) - emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE); - } - else + if(opcode2[i]==0) // MFC0 { - map=get_reg(i_regs->regmap,TLREG); - assert(map>=0); - reglist&=~(1<regmap,rt1[i]); + u_int copr=(source[i]>>11)&0x1f; + //assert(t>=0); // Why does this happen? OOT is weird + if(t>=0&&rt1[i]!=0) { + emit_readword(®_cop0[copr],t); } } - if (opcode[i]==0x39) { // SWC1 (read float) - emit_readword_indexed(0,tl,tl); - } - if (opcode[i]==0x3D) { // SDC1 (read double) - emit_readword_indexed(4,tl,th); - emit_readword_indexed(0,tl,tl); - } - if (opcode[i]==0x31) { // LWC1 (get target address) - emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp); - } - if (opcode[i]==0x35) { // LDC1 (get target address) - emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp); - } - if(!using_tlb) { - if(!c) { - jaddr2=(int)out; - emit_jno(0); - } - else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) { - jaddr2=(int)out; - emit_jmp(0); // inline_readstub/inline_writestub? Very rare case - } - #ifdef DESTRUCTIVE_SHIFT - if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1 - if(!offset&&!c&&s>=0) emit_mov(s,ar); - } - #endif - }else{ - if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1 - do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2); + else if(opcode2[i]==4) // MTC0 + { + signed char s=get_reg(i_regs->regmap,rs1[i]); + char copr=(source[i]>>11)&0x1f; + assert(s>=0); + wb_register(rs1[i],i_regs->regmap,i_regs->dirty); + if(copr==9||copr==11||copr==12||copr==13) { + emit_readword(&last_count,HOST_TEMPREG); + emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc + emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG); + emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); + emit_writeword(HOST_CCREG,&Count); + } + // What a mess. The status register (12) can enable interrupts, + // so needs a special case to handle a pending interrupt. + // The interrupt must be taken immediately, because a subsequent + // instruction might disable interrupts again. + if(copr==12||copr==13) { + if (is_delayslot) { + // burn cycles to cause cc_interrupt, which will + // reschedule next_interupt. Relies on CCREG from above. + assem_debug("MTC0 DS %d\n", copr); + emit_writeword(HOST_CCREG,&last_count); + emit_movimm(0,HOST_CCREG); + emit_storereg(CCREG,HOST_CCREG); + emit_loadreg(rs1[i],1); + emit_movimm(copr,0); + emit_call(pcsx_mtc0_ds); + emit_loadreg(rs1[i],s); + return; + } + emit_movimm(start+i*4+4,HOST_TEMPREG); + emit_writeword(HOST_TEMPREG,&pcaddr); + emit_movimm(0,HOST_TEMPREG); + emit_writeword(HOST_TEMPREG,&pending_exception); + } + //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12); + //else + if(s==HOST_CCREG) + emit_loadreg(rs1[i],1); + else if(s!=1) + emit_mov(s,1); + emit_movimm(copr,0); + emit_call(pcsx_mtc0); + if(copr==9||copr==11||copr==12||copr==13) { + emit_readword(&Count,HOST_CCREG); + emit_readword(&next_interupt,HOST_TEMPREG); + emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG); + emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG); + emit_writeword(HOST_TEMPREG,&last_count); + emit_storereg(CCREG,HOST_CCREG); } - if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1 - do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2); + if(copr==12||copr==13) { + assert(!is_delayslot); + emit_readword(&pending_exception,14); + emit_test(14,14); + void *jaddr = out; + emit_jeq(0); + emit_readword(&pcaddr, 0); + emit_addimm(HOST_CCREG,2,HOST_CCREG); + emit_call(get_addr_ht); + emit_jmpreg(0); + set_jump_target(jaddr, out); } + emit_loadreg(rs1[i],s); } - if (opcode[i]==0x31) { // LWC1 - //if(s>=0&&!c&&!offset) emit_mov(s,tl); - //gen_tlb_addr_r(ar,map); - //emit_readword_indexed((int)rdram-0x80000000,tl,tl); - #ifdef HOST_IMM_ADDR32 - if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl); - else - #endif - emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl); - type=LOADW_STUB; - } - if (opcode[i]==0x35) { // LDC1 - assert(th>=0); - //if(s>=0&&!c&&!offset) emit_mov(s,tl); - //gen_tlb_addr_r(ar,map); - //emit_readword_indexed((int)rdram-0x80000000,tl,th); - //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl); - #ifdef HOST_IMM_ADDR32 - if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl); - else - #endif - emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl); - type=LOADD_STUB; - } - if (opcode[i]==0x39) { // SWC1 - //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp); - emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp); - type=STOREW_STUB; - } - if (opcode[i]==0x3D) { // SDC1 - assert(th>=0); - //emit_writeword_indexed(th,(int)rdram-0x80000000,temp); - //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp); - emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp); - type=STORED_STUB; - } - if(!using_tlb&&!(i_regs->waswritten&(1<regmap,INVCP); - assert(ir>=0); - emit_cmpmem_indexedsr12_reg(ir,temp,1); - #else - emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1); - #endif - #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) - emit_callne(invalidate_addr_reg[temp]); - #else - jaddr3=(int)out; - emit_jne(0); - add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<regmap_entry,i_regs->wasdirty); + if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); + emit_movimm(start+(i-ds)*4,EAX); // Get PC + emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle... + emit_jmp(ds?fp_exception_ds:fp_exception); +} + +static void cop2_get_dreg(u_int copr,signed char tl,signed char temp) +{ + switch (copr) { + case 1: + case 3: + case 5: + case 8: + case 9: + case 10: + case 11: + emit_readword(®_cop2d[copr],tl); + emit_signextend16(tl,tl); + emit_writeword(tl,®_cop2d[copr]); // hmh + break; + case 7: + case 16: + case 17: + case 18: + case 19: + emit_readword(®_cop2d[copr],tl); + emit_andimm(tl,0xffff,tl); + emit_writeword(tl,®_cop2d[copr]); + break; + case 15: + emit_readword(®_cop2d[14],tl); // SXY2 + emit_writeword(tl,®_cop2d[copr]); + break; + case 28: + case 29: + c2op_mfc2_29_assemble(tl,temp); + break; + default: + emit_readword(®_cop2d[copr],tl); + break; } - //if(opcode[i]==0x39) - /*if(opcode[i]==0x39||opcode[i]==0x31) - { - emit_pusha(); - emit_readword((int)&last_count,ECX); - if(get_reg(i_regs->regmap,CCREG)<0) - emit_loadreg(CCREG,HOST_CCREG); - emit_add(HOST_CCREG,ECX,HOST_CCREG); - emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG); - emit_writeword(HOST_CCREG,(int)&Count); - emit_call((int)memdebug); - emit_popa(); - }/**/ +} + +static void cop2_put_dreg(u_int copr,signed char sl,signed char temp) +{ + switch (copr) { + case 15: + emit_readword(®_cop2d[13],temp); // SXY1 + emit_writeword(sl,®_cop2d[copr]); + emit_writeword(temp,®_cop2d[12]); // SXY0 + emit_readword(®_cop2d[14],temp); // SXY2 + emit_writeword(sl,®_cop2d[14]); + emit_writeword(temp,®_cop2d[13]); // SXY1 + break; + case 28: + emit_andimm(sl,0x001f,temp); + emit_shlimm(temp,7,temp); + emit_writeword(temp,®_cop2d[9]); + emit_andimm(sl,0x03e0,temp); + emit_shlimm(temp,2,temp); + emit_writeword(temp,®_cop2d[10]); + emit_andimm(sl,0x7c00,temp); + emit_shrimm(temp,3,temp); + emit_writeword(temp,®_cop2d[11]); + emit_writeword(sl,®_cop2d[28]); + break; + case 30: + emit_xorsar_imm(sl,sl,31,temp); +#if defined(HAVE_ARMV5) || defined(__aarch64__) + emit_clz(temp,temp); #else - cop1_unusable(i, i_regs); + emit_movs(temp,HOST_TEMPREG); + emit_movimm(0,temp); + emit_jeq((int)out+4*4); + emit_addpl_imm(temp,1,temp); + emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG); + emit_jns((int)out-2*4); #endif + emit_writeword(sl,®_cop2d[30]); + emit_writeword(temp,®_cop2d[31]); + break; + case 31: + break; + default: + emit_writeword(sl,®_cop2d[copr]); + break; + } } -void c2ls_assemble(int i,struct regstat *i_regs) +static void c2ls_assemble(int i,struct regstat *i_regs) { int s,tl; int ar; int offset; int memtarget=0,c=0; - int jaddr2=0,jaddr3,type; + void *jaddr2=NULL; + enum stub_type type; int agr=AGEN1+(i&1); - int fastio_reg_override=0; + int fastio_reg_override=-1; u_int hr,reglist=0; u_int copr=(source[i]>>16)&0x1f; s=get_reg(i_regs->regmap,rs1[i]); @@ -3824,7 +3242,6 @@ void c2ls_assemble(int i,struct regstat *i_regs) offset=imm[i]; assert(rs1[i]>0); assert(tl>=0); - assert(!using_tlb); for(hr=0;hrregmap[hr]>=0) reglist|=1<=0); if (opcode[i]==0x3a) { // SWC2 - cop2_get_dreg(copr,tl,HOST_TEMPREG); + cop2_get_dreg(copr,tl,-1); type=STOREW_STUB; } else type=LOADW_STUB; if(c&&!memtarget) { - jaddr2=(int)out; + jaddr2=out; emit_jmp(0); // inline_readstub/inline_writestub? } else { if(!c) { jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override); } + else if(ram_offset&&memtarget) { + host_tempreg_acquire(); + emit_addimm(ar,ram_offset,HOST_TEMPREG); + fastio_reg_override=HOST_TEMPREG; + } if (opcode[i]==0x32) { // LWC2 - #ifdef HOST_IMM_ADDR32 - if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl); - else - #endif int a=ar; - if(fastio_reg_override) a=fastio_reg_override; + if(fastio_reg_override>=0) a=fastio_reg_override; emit_readword_indexed(0,a,tl); } if (opcode[i]==0x3a) { // SWC2 @@ -3874,12 +3292,14 @@ void c2ls_assemble(int i,struct regstat *i_regs) if(!offset&&!c&&s>=0) emit_mov(s,ar); #endif int a=ar; - if(fastio_reg_override) a=fastio_reg_override; + if(fastio_reg_override>=0) a=fastio_reg_override; emit_writeword_indexed(tl,0,a); } } + if(fastio_reg_override==HOST_TEMPREG) + host_tempreg_release(); if(jaddr2) - add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist); + add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj[i],reglist); if(opcode[i]==0x3a) // SWC2 if(!(i_regs->waswritten&(1<=0); emit_cmpmem_indexedsr12_reg(ir,ar,1); #else - emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1); + emit_cmpmem_indexedsr12_imm(invalid_code,ar,1); #endif #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) emit_callne(invalidate_addr_reg[ar]); #else - jaddr3=(int)out; + void *jaddr3 = out; emit_jne(0); - add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<>11)&0x1f; + signed char temp=get_reg(i_regs->regmap,-1); + if (opcode2[i]==0) { // MFC2 + signed char tl=get_reg(i_regs->regmap,rt1[i]); + if(tl>=0&&rt1[i]!=0) + cop2_get_dreg(copr,tl,temp); + } + else if (opcode2[i]==4) { // MTC2 + signed char sl=get_reg(i_regs->regmap,rs1[i]); + cop2_put_dreg(copr,sl,temp); + } + else if (opcode2[i]==2) // CFC2 + { + signed char tl=get_reg(i_regs->regmap,rt1[i]); + if(tl>=0&&rt1[i]!=0) + emit_readword(®_cop2c[copr],tl); + } + else if (opcode2[i]==6) // CTC2 + { + signed char sl=get_reg(i_regs->regmap,rs1[i]); + switch(copr) { + case 4: + case 12: + case 20: + case 26: + case 27: + case 29: + case 30: + emit_signextend16(sl,temp); + break; + case 31: + c2op_ctc2_31_assemble(sl,temp); + break; + default: + temp=sl; + break; + } + emit_writeword(temp,®_cop2c[copr]); + assert(sl>=0); } } +static void do_unalignedwritestub(int n) +{ + assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4); + literal_pool(256); + set_jump_target(stubs[n].addr, out); + + int i=stubs[n].a; + struct regstat *i_regs=(struct regstat *)stubs[n].c; + int addr=stubs[n].b; + u_int reglist=stubs[n].e; + signed char *i_regmap=i_regs->regmap; + int temp2=get_reg(i_regmap,FTEMP); + int rt; + rt=get_reg(i_regmap,rs2[i]); + assert(rt>=0); + assert(addr>=0); + assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented + reglist|=(1<regmap,rt1[i]|64); + signed char sl,tl; tl=get_reg(i_regs->regmap,rt1[i]); //assert(tl>=0); if(tl>=0) { - sh=get_reg(i_regs->regmap,rs1[i]|64); sl=get_reg(i_regs->regmap,rs1[i]); if(sl>=0) emit_mov(sl,tl); else emit_loadreg(rs1[i],tl); - if(th>=0) { - if(sh>=0) emit_mov(sh,th); - else emit_loadreg(rs1[i]|64,th); - } } } } -#ifndef fconv_assemble -void fconv_assemble(int i,struct regstat *i_regs) +// call interpreter, exception handler, things that change pc/regs/cycles ... +static void call_c_cpu_handler(int i, const struct regstat *i_regs, u_int pc, void *func) { - printf("Need fconv_assemble for this architecture.\n"); - exit(1); + signed char ccreg=get_reg(i_regs->regmap,CCREG); + assert(ccreg==HOST_CCREG); + assert(!is_delayslot); + (void)ccreg; + + emit_movimm(pc,3); // Get PC + emit_readword(&last_count,2); + emit_writeword(3,&psxRegs.pc); + emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX + emit_add(2,HOST_CCREG,2); + emit_writeword(2,&psxRegs.cycle); + emit_call(func); + emit_jmp(jump_to_new_pc); } -#endif -#if 0 -void float_assemble(int i,struct regstat *i_regs) +static void syscall_assemble(int i,struct regstat *i_regs) { - printf("Need float_assemble for this architecture.\n"); - exit(1); + emit_movimm(0x20,0); // cause code + emit_movimm(0,1); // not in delay slot + call_c_cpu_handler(i,i_regs,start+i*4,psxException); } -#endif -void syscall_assemble(int i,struct regstat *i_regs) +static void hlecall_assemble(int i,struct regstat *i_regs) { - signed char ccreg=get_reg(i_regs->regmap,CCREG); - assert(ccreg==HOST_CCREG); - assert(!is_delayslot); - emit_movimm(start+i*4,EAX); // Get PC - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle... - emit_jmp((int)jump_syscall_hle); // XXX + void *hlefunc = psxNULL; + uint32_t hleCode = source[i] & 0x03ffffff; + if (hleCode < ARRAY_SIZE(psxHLEt)) + hlefunc = psxHLEt[hleCode]; + + call_c_cpu_handler(i,i_regs,start+i*4+4,hlefunc); } -void hlecall_assemble(int i,struct regstat *i_regs) +static void intcall_assemble(int i,struct regstat *i_regs) { - signed char ccreg=get_reg(i_regs->regmap,CCREG); - assert(ccreg==HOST_CCREG); - assert(!is_delayslot); - emit_movimm(start+i*4+4,0); // Get PC - emit_movimm((int)psxHLEt[source[i]&7],1); - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX - emit_jmp((int)jump_hlecall); + call_c_cpu_handler(i,i_regs,start+i*4,execI); } -void intcall_assemble(int i,struct regstat *i_regs) +static void speculate_mov(int rs,int rt) { - signed char ccreg=get_reg(i_regs->regmap,CCREG); - assert(ccreg==HOST_CCREG); - assert(!is_delayslot); - emit_movimm(start+i*4,0); // Get PC - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); - emit_jmp((int)jump_intcall); + if(rt!=0) { + smrv_strong_next|=1<>rs1[i])&1) speculate_mov(rs1[i],rt1[i]); + else if((smrv_strong>>rs2[i])&1) speculate_mov(rs2[i],rt1[i]); + else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]); + else if((smrv_weak>>rs2[i])&1) speculate_mov_weak(rs2[i],rt1[i]); + else { + smrv_strong_next&=~(1<=0) { + if(get_final_value(hr,i,&value)) + smrv[rt1[i]]=value; + else smrv[rt1[i]]=constmap[i][hr]; + smrv_strong_next|=1<>rs1[i])&1) speculate_mov(rs1[i],rt1[i]); + else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]); + } + break; + case LOAD: + if(start<0x2000&&(rt1[i]==26||(smrv[rt1[i]]>>24)==0xa0)) { + // special case for BIOS + smrv[rt1[i]]=0xa0000000; + smrv_strong_next|=1<>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst); +#endif } -void ds_assemble(int i,struct regstat *i_regs) +static void ds_assemble(int i,struct regstat *i_regs) { speculate_register_values(i); is_delayslot=1; @@ -4012,12 +3641,6 @@ void ds_assemble(int i,struct regstat *i_regs) c2ls_assemble(i,i_regs);break; case C2OP: c2op_assemble(i,i_regs);break; - case FCONV: - fconv_assemble(i,i_regs);break; - case FLOAT: - float_assemble(i,i_regs);break; - case FCOMP: - fcomp_assemble(i,i_regs);break; case MULTDIV: multdiv_assemble(i,i_regs);break; case MOV: @@ -4030,40 +3653,23 @@ void ds_assemble(int i,struct regstat *i_regs) case RJUMP: case CJUMP: case SJUMP: - case FJUMP: - printf("Jump in the delay slot. This is probably a bug.\n"); + SysPrintf("Jump in the delay slot. This is probably a bug.\n"); } is_delayslot=0; } // Is the branch target a valid internal jump? -int internal_branch(uint64_t i_is32,int addr) +static int internal_branch(int addr) { if(addr&1) return 0; // Indirect (register) jump if(addr>=start && addr>2; - // Delay slots are not valid branch targets - //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0; - // 64 -> 32 bit transition requires a recompile - /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32) - { - if(requires_32bit[t]&~i_is32) printf("optimizable: no\n"); - else printf("optimizable: yes\n"); - }*/ - //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0; -#ifndef FORCE32 - if(requires_32bit[t]&~i_is32) return 0; - else -#endif - return 1; + return 1; } return 0; } -#ifndef wb_invalidate -void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32, - uint64_t u,uint64_t uu) +static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u) { int hr; for(hr=0;hr=0) { if((dirty>>hr)&1) { if(get_reg(entry,pre[hr])<0) { - if(pre[hr]<64) { - if(!((u>>pre[hr])&1)) { - emit_storereg(pre[hr],hr); - if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) { - emit_sarimm(hr,31,hr); - emit_storereg(pre[hr]|64,hr); - } - } - }else{ - if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) { - emit_storereg(pre[hr],hr); - } - } + assert(pre[hr]<64); + if(!((u>>pre[hr])&1)) + emit_storereg(pre[hr],hr); } } } @@ -4105,12 +3701,11 @@ void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t } } } -#endif // Load the specified registers // This only loads the registers given as arguments because // we don't want to load things that will be overwritten -void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2) +static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2) { int hr; // Load 32-bit regs @@ -4130,28 +3725,6 @@ void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2 } } } - //Load 64-bit regs - for(hr=0;hr=0) { - if(entry[hr]!=regmap[hr]) { - if(regmap[hr]-64==rs1||regmap[hr]-64==rs2) - { - assert(regmap[hr]!=64); - if((is32>>(regmap[hr]&63))&1) { - int lr=get_reg(regmap,regmap[hr]-64); - if(lr>=0) - emit_sarimm(lr,31,hr); - else - emit_loadreg(regmap[hr],hr); - } - else - { - emit_loadreg(regmap[hr],hr); - } - } - } - } - } } // Load registers prior to the start of a loop @@ -4191,10 +3764,9 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[]) if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) { int ra=-1; int agr=AGEN1+(i&1); - int mgr=MGEN1+(i&1); if(itype[i]==LOAD) { ra=get_reg(i_regs->regmap,rt1[i]); - if(ra<0) ra=get_reg(i_regs->regmap,-1); + if(ra<0) ra=get_reg(i_regs->regmap,-1); assert(ra>=0); } if(itype[i]==LOADLR) { @@ -4213,17 +3785,11 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[]) } } int rs=get_reg(i_regs->regmap,rs1[i]); - int rm=get_reg(i_regs->regmap,TLREG); if(ra>=0) { int offset=imm[i]; int c=(i_regs->wasconst>>rs)&1; if(rs1[i]==0) { // Using r0 as a base address - /*if(rm>=0) { - if(!entry||entry[rm]!=mgr) { - generate_map_const(offset,rm); - } // else did it in the previous cycle - }*/ if(!entry||entry[ra]!=agr) { if (opcode[i]==0x22||opcode[i]==0x26) { emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR @@ -4241,22 +3807,6 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[]) // printf("poor load scheduling!\n"); } else if(c) { -#ifndef DISABLE_TLB - if(rm>=0) { - if(!entry||entry[rm]!=mgr) { - if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) { - // Stores to memory go thru the mapper to detect self-modifying - // code, loads don't. - if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 || - (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE ) - generate_map_const(constmap[i][rs]+offset,rm); - }else{ - if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000) - generate_map_const(constmap[i][rs]+offset,rm); - } - } - } -#endif if(rs1[i]!=rt1[i]||itype[i]!=LOAD) { if(!entry||entry[ra]!=agr) { if (opcode[i]==0x22||opcode[i]==0x26) { @@ -4264,10 +3814,6 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[]) }else if (opcode[i]==0x1a||opcode[i]==0x1b) { emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR }else{ - #ifdef HOST_IMM_ADDR32 - if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2 - (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000)) - #endif emit_movimm(constmap[i][rs]+offset,ra); regs[i].loadedconst|=1<regmap,agr); - if(ra>=0) { - int rs=get_reg(regs[i+1].regmap,rs1[i+1]); - int offset=imm[i+1]; - int c=(regs[i+1].wasconst>>rs)&1; - if(c) { - if(itype[i+1]==STORE||itype[i+1]==STORELR - ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2 - // Stores to memory go thru the mapper to detect self-modifying - // code, loads don't. - if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 || - (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE ) - generate_map_const(constmap[i+1][rs]+offset,ra); - }else{ - if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000) - generate_map_const(constmap[i+1][rs]+offset,ra); - } - } - /*else if(rs1[i]==0) { - generate_map_const(offset,ra); - }*/ - } - #endif // Actual address agr=AGEN1+((i+1)&1); ra=get_reg(i_regs->regmap,agr); @@ -4325,10 +3845,6 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[]) }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) { emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR }else{ - #ifdef HOST_IMM_ADDR32 - if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2 - (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000)) - #endif emit_movimm(constmap[i+1][rs]+offset,ra); regs[i+1].loadedconst|=1<>hr)&1)) { - #ifdef HOST_IMM_ADDR32 - if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0; - #endif // Precompute load address *value=constmap[i][hr]+imm[i+2]; return 1; @@ -4376,28 +3889,22 @@ int get_final_value(int hr, int i, int *value) } if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg) { - #ifdef HOST_IMM_ADDR32 - if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0; - #endif // Precompute load address *value=constmap[i][hr]+imm[i+1]; - //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]); + //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]); return 1; } } } *value=constmap[i][hr]; - //printf("c=%x\n",(int)constmap[i][hr]); + //printf("c=%lx\n",(long)constmap[i][hr]); if(i==slen-1) return 1; - if(reg<64) { - return !((unneeded_reg[i+1]>>reg)&1); - }else{ - return !((unneeded_reg_upper[i+1]>>reg)&1); - } + assert(reg < 64); + return !((unneeded_reg[i+1]>>reg)&1); } // Load registers with known constants -void load_consts(signed char pre[],signed char regmap[],int is32,int i) +static void load_consts(signed char pre[],signed char regmap[],int i) { int hr,hr2; // propagate loaded constant flags @@ -4417,7 +3924,8 @@ void load_consts(signed char pre[],signed char regmap[],int is32,int i) if(hr!=EXCLUDE_REG&®map[hr]>=0) { //if(entry[hr]!=regmap[hr]) { if(!((regs[i].loadedconst>>hr)&1)) { - if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) { + assert(regmap[hr]<64); + if(((regs[i].isconst>>hr)&1)&®map[hr]>0) { int value,similar=0; if(get_final_value(hr,i,&value)) { // see if some other register has similar value @@ -4448,41 +3956,16 @@ void load_consts(signed char pre[],signed char regmap[],int is32,int i) } } } - // Load 64-bit regs - for(hr=0;hr=0) { - //if(entry[hr]!=regmap[hr]) { - if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) { - if(((regs[i].isconst>>hr)&1)&®map[hr]>64) { - if((is32>>(regmap[hr]&63))&1) { - int lr=get_reg(regmap,regmap[hr]-64); - assert(lr>=0); - emit_sarimm(lr,31,hr); - } - else - { - int value; - if(get_final_value(hr,i,&value)) { - if(value==0) { - emit_zeroreg(hr); - } - else { - emit_movimm(value,hr); - } - } - } - } - } - } - } } -void load_all_consts(signed char regmap[],int is32,u_int dirty,int i) + +void load_all_consts(signed char regmap[], u_int dirty, int i) { int hr; // Load 32-bit regs for(hr=0;hr=0&&((dirty>>hr)&1)) { - if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) { + assert(regmap[hr] < 64); + if(((regs[i].isconst>>hr)&1)&®map[hr]>0) { int value=constmap[i][hr]; if(value==0) { emit_zeroreg(hr); @@ -4493,32 +3976,10 @@ void load_all_consts(signed char regmap[],int is32,u_int dirty,int i) } } } - // Load 64-bit regs - for(hr=0;hr=0&&((dirty>>hr)&1)) { - if(((regs[i].isconst>>hr)&1)&®map[hr]>64) { - if((is32>>(regmap[hr]&63))&1) { - int lr=get_reg(regmap,regmap[hr]-64); - assert(lr>=0); - emit_sarimm(lr,31,hr); - } - else - { - int value=constmap[i][hr]; - if(value==0) { - emit_zeroreg(hr); - } - else { - emit_movimm(value,hr); - } - } - } - } - } } // Write out all dirty registers (except cycle count) -void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty) +static void wb_dirtys(signed char i_regmap[],uint64_t i_dirty) { int hr; for(hr=0;hr0) { if(i_regmap[hr]!=CCREG) { if((i_dirty>>hr)&1) { - if(i_regmap[hr]<64) { - emit_storereg(i_regmap[hr],hr); -#ifndef FORCE32 - if( ((i_is32>>i_regmap[hr])&1) ) { - #ifdef DESTRUCTIVE_WRITEBACK - emit_sarimm(hr,31,hr); - emit_storereg(i_regmap[hr]|64,hr); - #else - emit_sarimm(hr,31,HOST_TEMPREG); - emit_storereg(i_regmap[hr]|64,HOST_TEMPREG); - #endif - } -#endif - }else{ - if( !((i_is32>>(i_regmap[hr]&63))&1) ) { - emit_storereg(i_regmap[hr],hr); - } - } + assert(i_regmap[hr]<64); + emit_storereg(i_regmap[hr],hr); } } } } } } + // Write out dirty registers that we need to reload (pair with load_needed_regs) // This writes the registers not written by store_regs_bt -void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr) +void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr) { int hr; int t=(addr-start)>>2; @@ -4560,26 +4006,10 @@ void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,in if(hr!=EXCLUDE_REG) { if(i_regmap[hr]>0) { if(i_regmap[hr]!=CCREG) { - if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) { + if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) { if((i_dirty>>hr)&1) { - if(i_regmap[hr]<64) { - emit_storereg(i_regmap[hr],hr); -#ifndef FORCE32 - if( ((i_is32>>i_regmap[hr])&1) ) { - #ifdef DESTRUCTIVE_WRITEBACK - emit_sarimm(hr,31,hr); - emit_storereg(i_regmap[hr]|64,hr); - #else - emit_sarimm(hr,31,HOST_TEMPREG); - emit_storereg(i_regmap[hr]|64,HOST_TEMPREG); - #endif - } -#endif - }else{ - if( !((i_is32>>(i_regmap[hr]&63))&1) ) { - emit_storereg(i_regmap[hr],hr); - } - } + assert(i_regmap[hr]<64); + emit_storereg(i_regmap[hr],hr); } } } @@ -4647,58 +4077,23 @@ void load_regs_entry(int t) } } } - // Load 64-bit regs - for(hr=0;hr=64&®s[t].regmap_entry[hr]>(regs[t].regmap_entry[hr]&63))&1) { - int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64); - if(lr<0) { - emit_loadreg(regs[t].regmap_entry[hr],hr); - } - else - { - emit_sarimm(lr,31,hr); - } - } - else - { - emit_loadreg(regs[t].regmap_entry[hr],hr); - } - } - } } // Store dirty registers prior to branch -void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr) +void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr) { - if(internal_branch(i_is32,addr)) + if(internal_branch(addr)) { int t=(addr-start)>>2; int hr; for(hr=0;hr0 && i_regmap[hr]!=CCREG) { - if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) { + if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) { if((i_dirty>>hr)&1) { - if(i_regmap[hr]<64) { - if(!((unneeded_reg[t]>>i_regmap[hr])&1)) { - emit_storereg(i_regmap[hr],hr); - if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) { - #ifdef DESTRUCTIVE_WRITEBACK - emit_sarimm(hr,31,hr); - emit_storereg(i_regmap[hr]|64,hr); - #else - emit_sarimm(hr,31,HOST_TEMPREG); - emit_storereg(i_regmap[hr]|64,HOST_TEMPREG); - #endif - } - } - }else{ - if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) { - emit_storereg(i_regmap[hr],hr); - } - } + assert(i_regmap[hr]<64); + if(!((unneeded_reg[t]>>i_regmap[hr])&1)) + emit_storereg(i_regmap[hr],hr); } } } @@ -4708,15 +4103,15 @@ void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int a else { // Branch out of this block, write out all dirty regs - wb_dirtys(i_regmap,i_is32,i_dirty); + wb_dirtys(i_regmap,i_dirty); } } // Load all needed registers for branch target -void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr) +static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr) { //if(addr>=start && addr<(start+slen*4)) - if(internal_branch(i_is32,addr)) + if(internal_branch(addr)) { int t=(addr-start)>>2; int hr; @@ -4730,11 +4125,7 @@ void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int ad // Load 32-bit regs for(hr=0;hr=0&®s[t].regmap_entry[hr]>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) { - #else - if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) { - #endif + if(i_regmap[hr]!=regs[t].regmap_entry[hr]) { if(regs[t].regmap_entry[hr]==0) { emit_zeroreg(hr); } @@ -4745,37 +4136,10 @@ void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int ad } } } - //Load 64-bit regs - for(hr=0;hr=64&®s[t].regmap_entry[hr]>(regs[t].regmap_entry[hr]&63))&1) { - int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64); - if(lr<0) { - emit_loadreg(regs[t].regmap_entry[hr],hr); - } - else - { - emit_sarimm(lr,31,hr); - } - } - else - { - emit_loadreg(regs[t].regmap_entry[hr],hr); - } - } - else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) { - int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64); - assert(lr>=0); - emit_sarimm(lr,31,hr); - } - } - } } } -int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr) +static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr) { if(addr>=start && addr>hr)&1) { if(i_regmap[hr]=64&&i_regmap[hr]>(i_regmap[hr]&63))&1)) - return 0; + assert(0); } } } @@ -4821,20 +4184,11 @@ int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr) } } } - if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1) - { - //printf("%x: is32 no match\n",addr); - return 0; - } } } } - //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0; -#ifndef FORCE32 - if(requires_32bit[t]&~i_is32) return 0; -#endif // Delay slots are not valid branch targets - //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0; + //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP)) return 0; // Delay slots require additional processing, so do not match if(is_ds[t]) return 0; } @@ -4861,20 +4215,44 @@ int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr) return 1; } +#ifdef DRC_DBG +static void drc_dbg_emit_do_cmp(int i) +{ + extern void do_insn_cmp(); + //extern int cycle; + u_int hr,reglist=0; + + for(hr=0;hr=0) reglist|=1<>2; - if(!instr_addr[t]) instr_addr[t]=(u_int)out; + if (!instr_addr[t]) + instr_addr[t] = out; assem_debug("Assemble delay slot at %x\n",ba[i]); assem_debug("<->\n"); + drc_dbg_emit_do_cmp(t); if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG) - wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32); - load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]); + wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty); + load_regs(regs[t].regmap_entry,regs[t].regmap,rs1[t],rs2[t]); address_generation(t,®s[t],regs[t].regmap_entry); if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a) - load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP); - cop1_usable=0; + load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP); is_delayslot=0; switch(itype[t]) { case ALU: @@ -4905,12 +4283,6 @@ void ds_assemble_entry(int i) c2ls_assemble(t,®s[t]);break; case C2OP: c2op_assemble(t,®s[t]);break; - case FCONV: - fconv_assemble(t,®s[t]);break; - case FLOAT: - float_assemble(t,®s[t]);break; - case FCOMP: - fcomp_assemble(t,®s[t]);break; case MULTDIV: multdiv_assemble(t,®s[t]);break; case MOV: @@ -4923,33 +4295,50 @@ void ds_assemble_entry(int i) case RJUMP: case CJUMP: case SJUMP: - case FJUMP: - printf("Jump in the delay slot. This is probably a bug.\n"); + SysPrintf("Jump in the delay slot. This is probably a bug.\n"); } - store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4); - load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4); - if(internal_branch(regs[t].is32,ba[i]+4)) + store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4); + load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4); + if(internal_branch(ba[i]+4)) assem_debug("branch: internal\n"); else assem_debug("branch: external\n"); - assert(internal_branch(regs[t].is32,ba[i]+4)); - add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4)); + assert(internal_branch(ba[i]+4)); + add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4)); emit_jmp(0); } +static void emit_extjump(void *addr, u_int target) +{ + emit_extjump2(addr, target, dyna_linker); +} + +static void emit_extjump_ds(void *addr, u_int target) +{ + emit_extjump2(addr, target, dyna_linker_ds); +} + +// Load 2 immediates optimizing for small code size +static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2) +{ + emit_movimm(imm1,rt1); + emit_movimm_from(imm1,rt1,imm2,rt2); +} + void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert) { int count; - int jaddr; - int idle=0; + void *jaddr; + void *idle=NULL; + int t=0; if(itype[i]==RJUMP) { *adj=0; } //if(ba[i]>=start && ba[i]<(start+slen*4)) - if(internal_branch(branch_regs[i].is32,ba[i])) + if(internal_branch(ba[i])) { - int t=(ba[i]-start)>>2; + t=(ba[i]-start)>>2; if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle else *adj=ccadj[t]; } @@ -4961,82 +4350,84 @@ void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert) if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) { // Idle loop if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG); - idle=(int)out; + idle=out; //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles emit_andimm(HOST_CCREG,3,HOST_CCREG); - jaddr=(int)out; + jaddr=out; emit_jmp(0); } else if(*adj==0||invert) { - emit_addimm_and_set_flags(CLOCK_ADJUST(count+2),HOST_CCREG); - jaddr=(int)out; + int cycles=CLOCK_ADJUST(count+2); + // faster loop HACK + if (t&&*adj) { + int rel=t-i; + if(-NO_CYCLE_PENALTY_THR>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) { - s1h=s2h=-1; + s2l=-1; } assert(s1l>=0); #ifdef DESTRUCTIVE_WRITEBACK if(rs1[i]) { - if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1) + if((branch_regs[i].dirty>>s1l)&&1) emit_loadreg(rs1[i],s1l); - } + } else { - if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1) + if((branch_regs[i].dirty>>s1l)&1) emit_loadreg(rs2[i],s1l); } if(s2l>=0) - if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1) + if((branch_regs[i].dirty>>s2l)&1) emit_loadreg(rs2[i],s2l); #endif int hr=0; @@ -5078,46 +4469,28 @@ void do_ccstub(int n) if((opcode[i]&0x2f)==4) // BEQ { #ifdef HAVE_CMOV_IMM - if(s1h<0) { - if(s2l>=0) emit_cmp(s1l,s2l); - else emit_test(s1l,s1l); - emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr); - } - else + if(s2l>=0) emit_cmp(s1l,s2l); + else emit_test(s1l,s1l); + emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr); + #else + emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); + if(s2l>=0) emit_cmp(s1l,s2l); + else emit_test(s1l,s1l); + emit_cmovne_reg(alt,addr); #endif - { - emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); - if(s1h>=0) { - if(s2h>=0) emit_cmp(s1h,s2h); - else emit_test(s1h,s1h); - emit_cmovne_reg(alt,addr); - } - if(s2l>=0) emit_cmp(s1l,s2l); - else emit_test(s1l,s1l); - emit_cmovne_reg(alt,addr); - } } if((opcode[i]&0x2f)==5) // BNE { #ifdef HAVE_CMOV_IMM - if(s1h<0) { - if(s2l>=0) emit_cmp(s1l,s2l); - else emit_test(s1l,s1l); - emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr); - } - else + if(s2l>=0) emit_cmp(s1l,s2l); + else emit_test(s1l,s1l); + emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr); + #else + emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt); + if(s2l>=0) emit_cmp(s1l,s2l); + else emit_test(s1l,s1l); + emit_cmovne_reg(alt,addr); #endif - { - emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt); - if(s1h>=0) { - if(s2h>=0) emit_cmp(s1h,s2h); - else emit_test(s1h,s1h); - emit_cmovne_reg(alt,addr); - } - if(s2l>=0) emit_cmp(s1l,s2l); - else emit_test(s1l,s1l); - emit_cmovne_reg(alt,addr); - } } if((opcode[i]&0x2f)==6) // BLEZ { @@ -5125,13 +4498,7 @@ void do_ccstub(int n) //emit_movimm(start+i*4+8,addr); emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); emit_cmpimm(s1l,1); - if(s1h>=0) emit_mov(addr,ntaddr); emit_cmovl_reg(alt,addr); - if(s1h>=0) { - emit_test(s1h,s1h); - emit_cmovne_reg(ntaddr,addr); - emit_cmovs_reg(alt,addr); - } } if((opcode[i]&0x2f)==7) // BGTZ { @@ -5139,21 +4506,14 @@ void do_ccstub(int n) //emit_movimm(start+i*4+8,ntaddr); emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr); emit_cmpimm(s1l,1); - if(s1h>=0) emit_mov(addr,alt); emit_cmovl_reg(ntaddr,addr); - if(s1h>=0) { - emit_test(s1h,s1h); - emit_cmovne_reg(alt,addr); - emit_cmovs_reg(ntaddr,addr); - } } if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ { //emit_movimm(ba[i],alt); //emit_movimm(start+i*4+8,addr); emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); - if(s1h>=0) emit_test(s1h,s1h); - else emit_test(s1l,s1l); + emit_test(s1l,s1l); emit_cmovs_reg(alt,addr); } if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ @@ -5161,8 +4521,7 @@ void do_ccstub(int n) //emit_movimm(ba[i],addr); //emit_movimm(start+i*4+8,alt); emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); - if(s1h>=0) emit_test(s1h,s1h); - else emit_test(s1l,s1l); + emit_test(s1l,s1l); emit_cmovs_reg(alt,addr); } if(opcode[i]==0x11 && opcode2[i]==0x08 ) { @@ -5183,7 +4542,7 @@ void do_ccstub(int n) emit_cmovne_reg(alt,addr); } } - emit_writeword(addr,(int)&pcaddr); + emit_writeword(addr,&pcaddr); } else if(itype[i]==RJUMP) @@ -5192,70 +4551,46 @@ void do_ccstub(int n) if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) { r=get_reg(branch_regs[i].regmap,RTEMP); } - emit_writeword(r,(int)&pcaddr); + emit_writeword(r,&pcaddr); } - else {printf("Unknown branch type in do_ccstub\n");exit(1);} + else {SysPrintf("Unknown branch type in do_ccstub\n");abort();} } // Update cycle count assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1); - if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG); - emit_call((int)cc_interrupt); - if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG); - if(stubs[n][6]==TAKEN) { - if(internal_branch(branch_regs[i].is32,ba[i])) + if(stubs[n].a) emit_addimm(HOST_CCREG,CLOCK_ADJUST((signed int)stubs[n].a),HOST_CCREG); + emit_call(cc_interrupt); + if(stubs[n].a) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((signed int)stubs[n].a),HOST_CCREG); + if(stubs[n].d==TAKEN) { + if(internal_branch(ba[i])) load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry); else if(itype[i]==RJUMP) { if(get_reg(branch_regs[i].regmap,RTEMP)>=0) - emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP)); + emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP)); else emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i])); } - }else if(stubs[n][6]==NOTTAKEN) { + }else if(stubs[n].d==NOTTAKEN) { if(i=0) { #ifdef USE_MINI_HT - if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) { + if(internal_branch(return_address)&&rt1[i+1]!=31) { int temp=-1; // note: must be ds-safe #ifdef HOST_TEMPREG temp=HOST_TEMPREG; @@ -5281,32 +4616,32 @@ static void ujump_assemble_write_ra(int i) #endif { #ifdef REG_PREFETCH - if(temp>=0) + if(temp>=0) { - if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp); + if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); } #endif emit_movimm(return_address,rt); // PC into link register #ifdef IMM_PREFETCH - emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]); + emit_prefetch(hash_table_get(return_address)); #endif } } } -void ujump_assemble(int i,struct regstat *i_regs) +static void ujump_assemble(int i,struct regstat *i_regs) { - signed char *i_regmap=i_regs->regmap; int ra_done=0; if(i==(ba[i]-start)>>2) assem_debug("idle loop\n"); address_generation(i+1,i_regs,regs[i].regmap_entry); #ifdef REG_PREFETCH int temp=get_reg(branch_regs[i].regmap,PTEMP); - if(rt1[i]==31&&temp>=0) + if(rt1[i]==31&&temp>=0) { + signed char *i_regmap=i_regs->regmap; int return_address=start+i*4+8; - if(get_reg(branch_regs[i].regmap,31)>0) - if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp); + if(get_reg(branch_regs[i].regmap,31)>0) + if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); } #endif if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) { @@ -5315,33 +4650,30 @@ void ujump_assemble(int i,struct regstat *i_regs) } ds_assemble(i+1,i_regs); uint64_t bc_unneeded=branch_regs[i].u; - uint64_t bc_unneeded_upper=branch_regs[i].uu; bc_unneeded|=1|(1LL<=0) emit_prefetchreg(temp); #endif do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); - load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); - if(internal_branch(branch_regs[i].is32,ba[i])) + load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); + if(internal_branch(ba[i])) assem_debug("branch: internal\n"); else assem_debug("branch: external\n"); - if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) { + if(internal_branch(ba[i])&&is_ds[(ba[i]-start)>>2]) { ds_assemble_entry(i); } else { - add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i])); + add_to_linker(out,ba[i],internal_branch(ba[i])); emit_jmp(0); } } @@ -5356,22 +4688,21 @@ static void rjump_assemble_write_ra(int i) assert(rt>=0); return_address=start+i*4+8; #ifdef REG_PREFETCH - if(temp>=0) + if(temp>=0) { - if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp); + if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); } #endif emit_movimm(return_address,rt); // PC into link register #ifdef IMM_PREFETCH - emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]); + emit_prefetch(hash_table_get(return_address)); #endif } -void rjump_assemble(int i,struct regstat *i_regs) +static void rjump_assemble(int i,struct regstat *i_regs) { - signed char *i_regmap=i_regs->regmap; int temp; - int rs,cc,adj; + int rs,cc; int ra_done=0; rs=get_reg(branch_regs[i].regmap,rs1[i]); assert(rs>=0); @@ -5385,11 +4716,12 @@ void rjump_assemble(int i,struct regstat *i_regs) } address_generation(i+1,i_regs,regs[i].regmap_entry); #ifdef REG_PREFETCH - if(rt1[i]==31) + if(rt1[i]==31) { if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) { + signed char *i_regmap=i_regs->regmap; int return_address=start+i*4+8; - if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp); + if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); } } #endif @@ -5405,17 +4737,15 @@ void rjump_assemble(int i,struct regstat *i_regs) } ds_assemble(i+1,i_regs); uint64_t bc_unneeded=branch_regs[i].u; - uint64_t bc_unneeded_upper=branch_regs[i].uu; bc_unneeded|=1|(1LL<>rs)&(branch_regs[i].is32>>rs1[i])&1) { + if((branch_regs[i].dirty>>rs)&1) { if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) { emit_loadreg(rs1[i],rs); } @@ -5445,15 +4775,13 @@ void rjump_assemble(int i,struct regstat *i_regs) //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen //assert(adj==0); emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); - add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0); -#ifdef PCSX + add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs); if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10) // special case for RFE emit_jmp(0); else -#endif - emit_jns(0); - //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1); + emit_jns(0); + //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1); #ifdef USE_MINI_HT if(rs1[i]==31) { do_miniht_jump(rs,rh,ht); @@ -5461,76 +4789,40 @@ void rjump_assemble(int i,struct regstat *i_regs) else #endif { - //if(rs!=EAX) emit_mov(rs,EAX); - //emit_jmp((int)jump_vaddr_eax); - emit_jmp(jump_vaddr_reg[rs]); - } - /* Check hash table - temp=!rs; - emit_mov(rs,temp); - emit_shrimm(rs,16,rs); - emit_xor(temp,rs,rs); - emit_movzwl_reg(rs,rs); - emit_shlimm(rs,4,rs); - emit_cmpmem_indexed((int)hash_table,rs,temp); - emit_jne((int)out+14); - emit_readword_indexed((int)hash_table+4,rs,rs); - emit_jmpreg(rs); - emit_cmpmem_indexed((int)hash_table+8,rs,temp); - emit_addimm_no_flags(8,rs); - emit_jeq((int)out-17); - // No hit on hash table, call compiler - emit_pushreg(temp); -//DEBUG > -#ifdef DEBUG_CYCLE_COUNT - emit_readword((int)&last_count,ECX); - emit_add(HOST_CCREG,ECX,HOST_CCREG); - emit_readword((int)&next_interupt,ECX); - emit_writeword(HOST_CCREG,(int)&Count); - emit_sub(HOST_CCREG,ECX,HOST_CCREG); - emit_writeword(ECX,(int)&last_count); -#endif -//DEBUG < - emit_storereg(CCREG,HOST_CCREG); - emit_call((int)get_addr); - emit_loadreg(CCREG,HOST_CCREG); - emit_addimm(ESP,4,ESP); - emit_jmpreg(EAX);*/ + do_jump_vaddr(rs); + } #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK if(rt1[i]!=31&&iregmap; int cc; int match; - match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); + match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); assem_debug("match=%d\n",match); - int s1h,s1l,s2h,s2l; - int prev_cop1_usable=cop1_usable; + int s1l,s2l; int unconditional=0,nop=0; - int only32=0; int invert=0; - int internal=internal_branch(branch_regs[i].is32,ba[i]); + int internal=internal_branch(ba[i]); if(i==(ba[i]-start)>>2) assem_debug("idle loop\n"); if(!match) invert=1; #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK if(i>(ba[i]-start)>>2) invert=1; #endif - + #ifdef __aarch64__ + invert=1; // because of near cond. branches + #endif + if(ooo[i]) { s1l=get_reg(branch_regs[i].regmap,rs1[i]); - s1h=get_reg(branch_regs[i].regmap,rs1[i]|64); s2l=get_reg(branch_regs[i].regmap,rs2[i]); - s2h=get_reg(branch_regs[i].regmap,rs2[i]|64); } else { s1l=get_reg(i_regmap,rs1[i]); - s1h=get_reg(i_regmap,rs1[i]|64); s2l=get_reg(i_regmap,rs2[i]); - s2h=get_reg(i_regmap,rs2[i]|64); } if(rs1[i]==0&&rs2[i]==0) { @@ -5543,17 +4835,12 @@ void cjump_assemble(int i,struct regstat *i_regs) } else if(rs1[i]==0) { - s1l=s2l;s1h=s2h; - s2l=s2h=-1; - only32=(regs[i].was32>>rs2[i])&1; + s1l=s2l; + s2l=-1; } else if(rs2[i]==0) { - s2l=s2h=-1; - only32=(regs[i].was32>>rs1[i])&1; - } - else { - only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1; + s2l=-1; } if(ooo[i]) { @@ -5563,26 +4850,22 @@ void cjump_assemble(int i,struct regstat *i_regs) ds_assemble(i+1,i_regs); int adj; uint64_t bc_unneeded=branch_regs[i].u; - uint64_t bc_unneeded_upper=branch_regs[i].uu; bc_unneeded&=~((1LL<>2 || source[i+1]!=0) { if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); - load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); + load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) assem_debug("branch: internal\n"); else @@ -5591,7 +4874,7 @@ void cjump_assemble(int i,struct regstat *i_regs) ds_assemble_entry(i); } else { - add_to_linker((int)out,ba[i],internal); + add_to_linker(out,ba[i],internal); emit_jmp(0); } #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK @@ -5601,52 +4884,15 @@ void cjump_assemble(int i,struct regstat *i_regs) } else if(nop) { emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); - int jaddr=(int)out; + void *jaddr=out; emit_jns(0); - add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0); + add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); } else { - int taken=0,nottaken=0,nottaken1=0; + void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL; do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); - if(!only32) - { - assert(s1h>=0); - if(opcode[i]==4) // BEQ - { - if(s2h>=0) emit_cmp(s1h,s2h); - else emit_test(s1h,s1h); - nottaken1=(int)out; - emit_jne(1); - } - if(opcode[i]==5) // BNE - { - if(s2h>=0) emit_cmp(s1h,s2h); - else emit_test(s1h,s1h); - if(invert) taken=(int)out; - else add_to_linker((int)out,ba[i],internal); - emit_jne(0); - } - if(opcode[i]==6) // BLEZ - { - emit_test(s1h,s1h); - if(invert) taken=(int)out; - else add_to_linker((int)out,ba[i],internal); - emit_js(0); - nottaken1=(int)out; - emit_jne(1); - } - if(opcode[i]==7) // BGTZ - { - emit_test(s1h,s1h); - nottaken1=(int)out; - emit_js(1); - if(invert) taken=(int)out; - else add_to_linker((int)out,ba[i],internal); - emit_jne(0); - } - } // if(!only32) - + //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); assert(s1l>=0); if(opcode[i]==4) // BEQ @@ -5654,10 +4900,10 @@ void cjump_assemble(int i,struct regstat *i_regs) if(s2l>=0) emit_cmp(s1l,s2l); else emit_test(s1l,s1l); if(invert){ - nottaken=(int)out; - emit_jne(1); + nottaken=out; + emit_jne(DJT_1); }else{ - add_to_linker((int)out,ba[i],internal); + add_to_linker(out,ba[i],internal); emit_jeq(0); } } @@ -5666,10 +4912,10 @@ void cjump_assemble(int i,struct regstat *i_regs) if(s2l>=0) emit_cmp(s1l,s2l); else emit_test(s1l,s1l); if(invert){ - nottaken=(int)out; - emit_jeq(1); + nottaken=out; + emit_jeq(DJT_1); }else{ - add_to_linker((int)out,ba[i],internal); + add_to_linker(out,ba[i],internal); emit_jne(0); } } @@ -5677,10 +4923,10 @@ void cjump_assemble(int i,struct regstat *i_regs) { emit_cmpimm(s1l,1); if(invert){ - nottaken=(int)out; - emit_jge(1); + nottaken=out; + emit_jge(DJT_1); }else{ - add_to_linker((int)out,ba[i],internal); + add_to_linker(out,ba[i],internal); emit_jl(0); } } @@ -5688,31 +4934,31 @@ void cjump_assemble(int i,struct regstat *i_regs) { emit_cmpimm(s1l,1); if(invert){ - nottaken=(int)out; - emit_jl(1); + nottaken=out; + emit_jl(DJT_1); }else{ - add_to_linker((int)out,ba[i],internal); + add_to_linker(out,ba[i],internal); emit_jge(0); } } if(invert) { - if(taken) set_jump_target(taken,(int)out); + if(taken) set_jump_target(taken, out); #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) { if(adj) { emit_addimm(cc,-CLOCK_ADJUST(adj),cc); - add_to_linker((int)out,ba[i],internal); + add_to_linker(out,ba[i],internal); }else{ emit_addnop(13); - add_to_linker((int)out,ba[i],internal*2); + add_to_linker(out,ba[i],internal*2); } emit_jmp(0); }else #endif { if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc); - store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); - load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); + store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); + load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) assem_debug("branch: internal\n"); else @@ -5721,14 +4967,14 @@ void cjump_assemble(int i,struct regstat *i_regs) ds_assemble_entry(i); } else { - add_to_linker((int)out,ba[i],internal); + add_to_linker(out,ba[i],internal); emit_jmp(0); } } - set_jump_target(nottaken,(int)out); + set_jump_target(nottaken, out); } - if(nottaken1) set_jump_target(nottaken1,(int)out); + if(nottaken1) set_jump_target(nottaken1, out); if(adj) { if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc); } @@ -5740,90 +4986,50 @@ void cjump_assemble(int i,struct regstat *i_regs) //if(likely[i]) printf("IOL\n"); //else //printf("IOE\n"); - int taken=0,nottaken=0,nottaken1=0; + void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL; if(!unconditional&&!nop) { - if(!only32) - { - assert(s1h>=0); - if((opcode[i]&0x2f)==4) // BEQ - { - if(s2h>=0) emit_cmp(s1h,s2h); - else emit_test(s1h,s1h); - nottaken1=(int)out; - emit_jne(2); - } - if((opcode[i]&0x2f)==5) // BNE - { - if(s2h>=0) emit_cmp(s1h,s2h); - else emit_test(s1h,s1h); - taken=(int)out; - emit_jne(1); - } - if((opcode[i]&0x2f)==6) // BLEZ - { - emit_test(s1h,s1h); - taken=(int)out; - emit_js(1); - nottaken1=(int)out; - emit_jne(2); - } - if((opcode[i]&0x2f)==7) // BGTZ - { - emit_test(s1h,s1h); - nottaken1=(int)out; - emit_js(2); - taken=(int)out; - emit_jne(1); - } - } // if(!only32) - //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); assert(s1l>=0); if((opcode[i]&0x2f)==4) // BEQ { if(s2l>=0) emit_cmp(s1l,s2l); else emit_test(s1l,s1l); - nottaken=(int)out; - emit_jne(2); + nottaken=out; + emit_jne(DJT_2); } if((opcode[i]&0x2f)==5) // BNE { if(s2l>=0) emit_cmp(s1l,s2l); else emit_test(s1l,s1l); - nottaken=(int)out; - emit_jeq(2); + nottaken=out; + emit_jeq(DJT_2); } if((opcode[i]&0x2f)==6) // BLEZ { emit_cmpimm(s1l,1); - nottaken=(int)out; - emit_jge(2); + nottaken=out; + emit_jge(DJT_2); } if((opcode[i]&0x2f)==7) // BGTZ { emit_cmpimm(s1l,1); - nottaken=(int)out; - emit_jl(2); + nottaken=out; + emit_jl(DJT_2); } } // if(!unconditional) int adj; uint64_t ds_unneeded=branch_regs[i].u; - uint64_t ds_unneeded_upper=branch_regs[i].uu; ds_unneeded&=~((1LL<>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<regmap; int cc; int match; - match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); + match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); assem_debug("smatch=%d\n",match); - int s1h,s1l; - int prev_cop1_usable=cop1_usable; + int s1l; int unconditional=0,nevertaken=0; - int only32=0; int invert=0; - int internal=internal_branch(branch_regs[i].is32,ba[i]); + int internal=internal_branch(ba[i]); if(i==(ba[i]-start)>>2) assem_debug("idle loop\n"); if(!match) invert=1; #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK if(i>(ba[i]-start)>>2) invert=1; #endif + #ifdef __aarch64__ + invert=1; // because of near cond. branches + #endif //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL) //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL) if(ooo[i]) { s1l=get_reg(branch_regs[i].regmap,rs1[i]); - s1h=get_reg(branch_regs[i].regmap,rs1[i]|64); } else { s1l=get_reg(i_regmap,rs1[i]); - s1h=get_reg(i_regmap,rs1[i]|64); } if(rs1[i]==0) { @@ -5924,9 +5127,6 @@ void sjump_assemble(int i,struct regstat *i_regs) //assert(opcode2[i]!=0x10); //assert(opcode2[i]!=0x12); } - else { - only32=(regs[i].was32>>rs1[i])&1; - } if(ooo[i]) { // Out of order execution (delay slot first) @@ -5935,15 +5135,11 @@ void sjump_assemble(int i,struct regstat *i_regs) ds_assemble(i+1,i_regs); int adj; uint64_t bc_unneeded=branch_regs[i].u; - uint64_t bc_unneeded_upper=branch_regs[i].uu; bc_unneeded&=~((1LL<>16)^return_address)&0xFFFF]); + if(!nevertaken) emit_prefetch(hash_table_get(return_address)); #endif } } cc=get_reg(branch_regs[i].regmap,CCREG); assert(cc==HOST_CCREG); - if(unconditional) - store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); + if(unconditional) + store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional); assem_debug("cycle count (adj)\n"); if(unconditional) { do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); if(i!=(ba[i]-start)>>2 || source[i+1]!=0) { if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); - load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); + load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) assem_debug("branch: internal\n"); else @@ -5976,7 +5172,7 @@ void sjump_assemble(int i,struct regstat *i_regs) ds_assemble_entry(i); } else { - add_to_linker((int)out,ba[i],internal); + add_to_linker(out,ba[i],internal); emit_jmp(0); } #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK @@ -5986,51 +5182,24 @@ void sjump_assemble(int i,struct regstat *i_regs) } else if(nevertaken) { emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); - int jaddr=(int)out; + void *jaddr=out; emit_jns(0); - add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0); + add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); } else { - int nottaken=0; + void *nottaken = NULL; do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); - if(!only32) - { - assert(s1h>=0); - if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL - { - emit_test(s1h,s1h); - if(invert){ - nottaken=(int)out; - emit_jns(1); - }else{ - add_to_linker((int)out,ba[i],internal); - emit_js(0); - } - } - if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL - { - emit_test(s1h,s1h); - if(invert){ - nottaken=(int)out; - emit_js(1); - }else{ - add_to_linker((int)out,ba[i],internal); - emit_jns(0); - } - } - } // if(!only32) - else { assert(s1l>=0); if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL { emit_test(s1l,s1l); if(invert){ - nottaken=(int)out; - emit_jns(1); + nottaken=out; + emit_jns(DJT_1); }else{ - add_to_linker((int)out,ba[i],internal); + add_to_linker(out,ba[i],internal); emit_js(0); } } @@ -6038,32 +5207,32 @@ void sjump_assemble(int i,struct regstat *i_regs) { emit_test(s1l,s1l); if(invert){ - nottaken=(int)out; - emit_js(1); + nottaken=out; + emit_js(DJT_1); }else{ - add_to_linker((int)out,ba[i],internal); + add_to_linker(out,ba[i],internal); emit_jns(0); } } - } // if(!only32) - + } + if(invert) { #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) { if(adj) { emit_addimm(cc,-CLOCK_ADJUST(adj),cc); - add_to_linker((int)out,ba[i],internal); + add_to_linker(out,ba[i],internal); }else{ emit_addnop(13); - add_to_linker((int)out,ba[i],internal*2); + add_to_linker(out,ba[i],internal*2); } emit_jmp(0); }else #endif { if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc); - store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); - load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); + store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); + load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) assem_debug("branch: internal\n"); else @@ -6072,11 +5241,11 @@ void sjump_assemble(int i,struct regstat *i_regs) ds_assemble_entry(i); } else { - add_to_linker((int)out,ba[i],internal); + add_to_linker(out,ba[i],internal); emit_jmp(0); } } - set_jump_target(nottaken,(int)out); + set_jump_target(nottaken, out); } if(adj) { @@ -6088,7 +5257,7 @@ void sjump_assemble(int i,struct regstat *i_regs) { // In-order execution (branch first) //printf("IOE\n"); - int nottaken=0; + void *nottaken = NULL; if(rt1[i]==31) { int rt,return_address; rt=get_reg(branch_regs[i].regmap,31); @@ -6097,62 +5266,38 @@ void sjump_assemble(int i,struct regstat *i_regs) return_address=start+i*4+8; emit_movimm(return_address,rt); // PC into link register #ifdef IMM_PREFETCH - emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]); + emit_prefetch(hash_table_get(return_address)); #endif } } if(!unconditional) { //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); - if(!only32) - { - assert(s1h>=0); - if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL - { - emit_test(s1h,s1h); - nottaken=(int)out; - emit_jns(1); - } - if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL - { - emit_test(s1h,s1h); - nottaken=(int)out; - emit_js(1); - } - } // if(!only32) - else - { assert(s1l>=0); if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL { emit_test(s1l,s1l); - nottaken=(int)out; - emit_jns(1); + nottaken=out; + emit_jns(DJT_1); } if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL { emit_test(s1l,s1l); - nottaken=(int)out; - emit_js(1); + nottaken=out; + emit_js(DJT_1); } - } } // if(!unconditional) int adj; uint64_t ds_unneeded=branch_regs[i].u; - uint64_t ds_unneeded_upper=branch_regs[i].uu; ds_unneeded&=~((1LL<>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<regmap; - int cc; - int match; - match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); - assem_debug("fmatch=%d\n",match); - int fs,cs; - int eaddr; - int invert=0; - int internal=internal_branch(branch_regs[i].is32,ba[i]); - if(i==(ba[i]-start)>>2) assem_debug("idle loop\n"); - if(!match) invert=1; - #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK - if(i>(ba[i]-start)>>2) invert=1; - #endif - - if(ooo[i]) { - fs=get_reg(branch_regs[i].regmap,FSREG); - address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay? - } - else { - fs=get_reg(i_regmap,FSREG); - } - - // Check cop1 unusable - if(!cop1_usable) { - cs=get_reg(i_regmap,CSREG); - assert(cs>=0); - emit_testimm(cs,0x20000000); - eaddr=(int)out; - emit_jeq(0); - add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0); - cop1_usable=1; - } - - if(ooo[i]) { - // Out of order execution (delay slot first) - //printf("OOOE\n"); - ds_assemble(i+1,i_regs); - int adj; - uint64_t bc_unneeded=branch_regs[i].u; - uint64_t bc_unneeded_upper=branch_regs[i].uu; - bc_unneeded&=~((1LL<=0); - emit_testimm(fs,0x800000); - if(source[i]&0x10000) // BC1T - { - if(invert){ - nottaken=(int)out; - emit_jeq(1); - }else{ - add_to_linker((int)out,ba[i],internal); - emit_jne(0); - } - } - else // BC1F - if(invert){ - nottaken=(int)out; - emit_jne(1); - }else{ - add_to_linker((int)out,ba[i],internal); - emit_jeq(0); - } - { - } - } // if(!only32) - - if(invert) { - if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc); - #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK - else if(match) emit_addnop(13); - #endif - store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); - load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); - if(internal) - assem_debug("branch: internal\n"); - else - assem_debug("branch: external\n"); - if(internal&&is_ds[(ba[i]-start)>>2]) { - ds_assemble_entry(i); - } - else { - add_to_linker((int)out,ba[i],internal); - emit_jmp(0); - } - set_jump_target(nottaken,(int)out); - } - - if(adj) { - if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc); - } - } // (!unconditional) - } // if(ooo) - else - { - // In-order execution (branch first) - //printf("IOE\n"); - int nottaken=0; - if(1) { - //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); - if(1) { - assert(fs>=0); - emit_testimm(fs,0x800000); - if(source[i]&0x10000) // BC1T - { - nottaken=(int)out; - emit_jeq(1); - } - else // BC1F - { - nottaken=(int)out; - emit_jne(1); - } - } - } // if(!unconditional) - int adj; - uint64_t ds_unneeded=branch_regs[i].u; - uint64_t ds_unneeded_upper=branch_regs[i].uu; - ds_unneeded&=~((1LL<>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<>2]) { - ds_assemble_entry(i); - } - else { - add_to_linker((int)out,ba[i],internal); - emit_jmp(0); - } - - // branch not taken - if(1) { // <- FIXME (don't need this) - set_jump_target(nottaken,(int)out); + set_jump_target(nottaken, out); assem_debug("1:\n"); if(!likely[i]) { - wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32, - ds_unneeded,ds_unneeded_upper); - load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]); + wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); + load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i+1],rs2[i+1]); address_generation(i+1,&branch_regs[i],0); - load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG); + load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG); ds_assemble(i+1,&branch_regs[i]); } cc=get_reg(branch_regs[i].regmap,CCREG); @@ -6400,18 +5338,18 @@ void fjump_assemble(int i,struct regstat *i_regs) // Cycle count isn't in a register, temporarily load it then write it out emit_loadreg(CCREG,HOST_CCREG); emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); - int jaddr=(int)out; + void *jaddr=out; emit_jns(0); - add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0); + add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); emit_storereg(CCREG,HOST_CCREG); } else{ cc=get_reg(i_regmap,CCREG); assert(cc==HOST_CCREG); emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); - int jaddr=(int)out; + void *jaddr=out; emit_jns(0); - add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0); + add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0); } } } @@ -6420,27 +5358,21 @@ void fjump_assemble(int i,struct regstat *i_regs) static void pagespan_assemble(int i,struct regstat *i_regs) { int s1l=get_reg(i_regs->regmap,rs1[i]); - int s1h=get_reg(i_regs->regmap,rs1[i]|64); int s2l=get_reg(i_regs->regmap,rs2[i]); - int s2h=get_reg(i_regs->regmap,rs2[i]|64); - void *nt_branch=NULL; - int taken=0; - int nottaken=0; + void *taken = NULL; + void *nottaken = NULL; int unconditional=0; if(rs1[i]==0) { - s1l=s2l;s1h=s2h; - s2l=s2h=-1; + s1l=s2l; + s2l=-1; } else if(rs2[i]==0) { - s2l=s2h=-1; - } - if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) { - s1h=s2h=-1; + s2l=-1; } int hr=0; - int addr,alt,ntaddr; + int addr=-1,alt=-1,ntaddr=-1; if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;} else { while(hr=0) emit_cmp(s1l,s2l); else emit_test(s1l,s1l); emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr); @@ -6520,11 +5452,6 @@ static void pagespan_assemble(int i,struct regstat *i_regs) { assert(s1l>=0); emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); - if(s1h>=0) { - if(s2h>=0) emit_cmp(s1h,s2h); - else emit_test(s1h,s1h); - emit_cmovne_reg(alt,addr); - } if(s2l>=0) emit_cmp(s1l,s2l); else emit_test(s1l,s1l); emit_cmovne_reg(alt,addr); @@ -6533,77 +5460,44 @@ static void pagespan_assemble(int i,struct regstat *i_regs) if((opcode[i]&0x3f)==5) // BNE { #ifdef HAVE_CMOV_IMM - if(s1h<0) { - if(s2l>=0) emit_cmp(s1l,s2l); - else emit_test(s1l,s1l); - emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr); - } - else + if(s2l>=0) emit_cmp(s1l,s2l); + else emit_test(s1l,s1l); + emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr); + #else + assert(s1l>=0); + emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt); + if(s2l>=0) emit_cmp(s1l,s2l); + else emit_test(s1l,s1l); + emit_cmovne_reg(alt,addr); #endif - { - assert(s1l>=0); - emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt); - if(s1h>=0) { - if(s2h>=0) emit_cmp(s1h,s2h); - else emit_test(s1h,s1h); - emit_cmovne_reg(alt,addr); - } - if(s2l>=0) emit_cmp(s1l,s2l); - else emit_test(s1l,s1l); - emit_cmovne_reg(alt,addr); - } } if((opcode[i]&0x3f)==0x14) // BEQL { - if(s1h>=0) { - if(s2h>=0) emit_cmp(s1h,s2h); - else emit_test(s1h,s1h); - nottaken=(int)out; - emit_jne(0); - } if(s2l>=0) emit_cmp(s1l,s2l); else emit_test(s1l,s1l); - if(nottaken) set_jump_target(nottaken,(int)out); - nottaken=(int)out; + if(nottaken) set_jump_target(nottaken, out); + nottaken=out; emit_jne(0); } if((opcode[i]&0x3f)==0x15) // BNEL { - if(s1h>=0) { - if(s2h>=0) emit_cmp(s1h,s2h); - else emit_test(s1h,s1h); - taken=(int)out; - emit_jne(0); - } if(s2l>=0) emit_cmp(s1l,s2l); else emit_test(s1l,s1l); - nottaken=(int)out; + nottaken=out; emit_jeq(0); - if(taken) set_jump_target(taken,(int)out); + if(taken) set_jump_target(taken, out); } if((opcode[i]&0x3f)==6) // BLEZ { emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); emit_cmpimm(s1l,1); - if(s1h>=0) emit_mov(addr,ntaddr); emit_cmovl_reg(alt,addr); - if(s1h>=0) { - emit_test(s1h,s1h); - emit_cmovne_reg(ntaddr,addr); - emit_cmovs_reg(alt,addr); - } } if((opcode[i]&0x3f)==7) // BGTZ { emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr); emit_cmpimm(s1l,1); - if(s1h>=0) emit_mov(addr,alt); emit_cmovl_reg(ntaddr,addr); - if(s1h>=0) { - emit_test(s1h,s1h); - emit_cmovne_reg(alt,addr); - emit_cmovs_reg(ntaddr,addr); - } } if((opcode[i]&0x3f)==0x16) // BLEZL { @@ -6632,19 +5526,19 @@ static void pagespan_assemble(int i,struct regstat *i_regs) if((source[i]&0x30000)==0x20000) // BC1FL { emit_testimm(s1l,0x800000); - nottaken=(int)out; + nottaken=out; emit_jne(0); } if((source[i]&0x30000)==0x30000) // BC1TL { emit_testimm(s1l,0x800000); - nottaken=(int)out; + nottaken=out; emit_jeq(0); } } assert(i_regs->regmap[HOST_CCREG]==CCREG); - wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty); + wb_dirtys(regs[i].regmap,regs[i].dirty); if(likely[i]||unconditional) { emit_movimm(ba[i],HOST_BTREG); @@ -6658,27 +5552,27 @@ static void pagespan_assemble(int i,struct regstat *i_regs) int target_addr=start+i*4+5; void *stub=out; void *compiled_target_addr=check_addr(target_addr); - emit_extjump_ds((int)branch_addr,target_addr); + emit_extjump_ds(branch_addr, target_addr); if(compiled_target_addr) { - set_jump_target((int)branch_addr,(int)compiled_target_addr); + set_jump_target(branch_addr, compiled_target_addr); add_link(target_addr,stub); } - else set_jump_target((int)branch_addr,(int)stub); + else set_jump_target(branch_addr, stub); if(likely[i]) { // Not-taken path - set_jump_target((int)nottaken,(int)out); - wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty); + set_jump_target(nottaken, out); + wb_dirtys(regs[i].regmap,regs[i].dirty); void *branch_addr=out; emit_jmp(0); int target_addr=start+i*4+8; void *stub=out; void *compiled_target_addr=check_addr(target_addr); - emit_extjump_ds((int)branch_addr,target_addr); + emit_extjump_ds(branch_addr, target_addr); if(compiled_target_addr) { - set_jump_target((int)branch_addr,(int)compiled_target_addr); + set_jump_target(branch_addr, compiled_target_addr); add_link(target_addr,stub); } - else set_jump_target((int)branch_addr,(int)stub); + else set_jump_target(branch_addr, stub); } } @@ -6694,14 +5588,13 @@ static void pagespan_ds() ll_add(jump_in+page,vaddr,(void *)out); assert(regs[0].regmap_entry[HOST_CCREG]==CCREG); if(regs[0].regmap[HOST_CCREG]!=CCREG) - wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32); + wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty); if(regs[0].regmap[HOST_BTREG]!=BTREG) - emit_writeword(HOST_BTREG,(int)&branch_target); - load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]); + emit_writeword(HOST_BTREG,&branch_target); + load_regs(regs[0].regmap_entry,regs[0].regmap,rs1[0],rs2[0]); address_generation(0,®s[0],regs[0].regmap_entry); if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a) - load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP); - cop1_usable=0; + load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP); is_delayslot=0; switch(itype[0]) { case ALU: @@ -6732,12 +5625,6 @@ static void pagespan_ds() c2ls_assemble(0,®s[0]);break; case C2OP: c2op_assemble(0,®s[0]);break; - case FCONV: - fconv_assemble(0,®s[0]);break; - case FLOAT: - float_assemble(0,®s[0]);break; - case FCOMP: - fcomp_assemble(0,®s[0]);break; case MULTDIV: multdiv_assemble(0,®s[0]);break; case MOV: @@ -6750,96 +5637,68 @@ static void pagespan_ds() case RJUMP: case CJUMP: case SJUMP: - case FJUMP: - printf("Jump in the delay slot. This is probably a bug.\n"); + SysPrintf("Jump in the delay slot. This is probably a bug.\n"); } int btaddr=get_reg(regs[0].regmap,BTREG); if(btaddr<0) { btaddr=get_reg(regs[0].regmap,-1); - emit_readword((int)&branch_target,btaddr); + emit_readword(&branch_target,btaddr); } assert(btaddr!=HOST_CCREG); if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); #ifdef HOST_IMM8 + host_tempreg_acquire(); emit_movimm(start+4,HOST_TEMPREG); emit_cmp(btaddr,HOST_TEMPREG); + host_tempreg_release(); #else emit_cmpimm(btaddr,start+4); #endif - int branch=(int)out; + void *branch = out; emit_jeq(0); - store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1); - emit_jmp(jump_vaddr_reg[btaddr]); - set_jump_target(branch,(int)out); - store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4); - load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4); + store_regs_bt(regs[0].regmap,regs[0].dirty,-1); + do_jump_vaddr(btaddr); + set_jump_target(branch, out); + store_regs_bt(regs[0].regmap,regs[0].dirty,start+4); + load_regs_bt(regs[0].regmap,regs[0].dirty,start+4); } // Basic liveness analysis for MIPS registers void unneeded_registers(int istart,int iend,int r) { int i; - uint64_t u,uu,gte_u,b,bu,gte_bu; - uint64_t temp_u,temp_uu,temp_gte_u=0; - uint64_t tdep; + uint64_t u,gte_u,b,gte_b; + uint64_t temp_u,temp_gte_u=0; uint64_t gte_u_unknown=0; if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED) gte_u_unknown=~0ll; if(iend==slen-1) { - u=1;uu=1; + u=1; gte_u=gte_u_unknown; }else{ - u=unneeded_reg[iend+1]; - uu=unneeded_reg_upper[iend+1]; - u=1;uu=1; + //u=unneeded_reg[iend+1]; + u=1; gte_u=gte_unneeded[iend+1]; } for (i=iend;i>=istart;i--) { //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r); - if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) + if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP) { // If subroutine call, flag return address as a possible branch target if(rt1[i]==31 && i=(start+slen*4)) { // Branch out of this block, flush all regs u=1; - uu=1; - gte_u=gte_u_unknown; - /* Hexagon hack - if(itype[i]==UJUMP&&rt1[i]==31) - { - uu=u=0x300C00F; // Discard at, v0-v1, t6-t9 - } - if(itype[i]==RJUMP&&rs1[i]==31) - { - uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9 - } - if(start>0x80000400&&start<0x80000000+RAM_SIZE) { - if(itype[i]==UJUMP&&rt1[i]==31) - { - //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi - uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9 - } - if(itype[i]==RJUMP&&rs1[i]==31) - { - //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi - uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9 - } - }*/ + gte_u=gte_u_unknown; branch_unneeded_reg[i]=u; - branch_unneeded_reg_upper[i]=uu; // Merge in delay slot - tdep=(~uu>>rt1[i+1])&1; u|=(1LL<>16)==0x1000) { // Unconditional branch - temp_u=1;temp_uu=1; + temp_u=1; temp_gte_u=0; } else { // Conditional branch (not taken case) temp_u=unneeded_reg[i+2]; - temp_uu=unneeded_reg_upper[i+2]; temp_gte_u&=gte_unneeded[i+2]; } // Merge in delay slot - tdep=(~temp_uu>>rt1[i+1])&1; temp_u|=(1LL<>rt1[i])&1; temp_u|=(1LL<>2,i-1,r+1); }else{ unneeded_reg[(ba[i]-start)>>2]=1; - unneeded_reg_upper[(ba[i]-start)>>2]=1; gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown; } } /*else*/ if(1) { @@ -6926,73 +5770,42 @@ void unneeded_registers(int istart,int iend,int r) { // Unconditional branch u=unneeded_reg[(ba[i]-start)>>2]; - uu=unneeded_reg_upper[(ba[i]-start)>>2]; gte_u=gte_unneeded[(ba[i]-start)>>2]; branch_unneeded_reg[i]=u; - branch_unneeded_reg_upper[i]=uu; - //u=1; - //uu=1; - //branch_unneeded_reg[i]=u; - //branch_unneeded_reg_upper[i]=uu; // Merge in delay slot - tdep=(~uu>>rt1[i+1])&1; u|=(1LL<>2]; - bu=unneeded_reg_upper[(ba[i]-start)>>2]; - gte_bu=gte_unneeded[(ba[i]-start)>>2]; + gte_b=gte_unneeded[(ba[i]-start)>>2]; branch_unneeded_reg[i]=b; - branch_unneeded_reg_upper[i]=bu; - //b=1; - //bu=1; - //branch_unneeded_reg[i]=b; - //branch_unneeded_reg_upper[i]=bu; // Branch delay slot - tdep=(~uu>>rt1[i+1])&1; b|=(1LL<>rt1[i])&1; + //u=1; // DEBUG // Written registers are unneeded u|=1LL<>r)&1) { - if(r==HIREG) printf(" HI"); - else if(r==LOREG) printf(" LO"); - else printf(" r%d",r); - } - } - printf("\n");*/ - } -#ifdef FORCE32 - for (i=iend;i>=istart;i--) - { - unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL; - } -#endif -} - -// Identify registers which are likely to contain 32-bit values -// This is used to predict whether any branches will jump to a -// location with 64-bit values in registers. -static void provisional_32bit() -{ - int i,j; - uint64_t is32=1; - uint64_t lastbranch=1; - - for(i=0;i0) { - if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) { - if(i>1) is32=lastbranch; - else is32=1; - } - } - if(i>1) - { - if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) { - if(likely[i-2]) { - if(i>2) is32=lastbranch; - else is32=1; - } - } - if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL - { - if(rs1[i-2]==0||rs2[i-2]==0) - { - if(rs1[i-2]) { - is32|=1LL<=0;j--) - { - if(ba[j]==start+i*4) - //temp_is32&=branch_regs[j].is32; - temp_is32&=p32[j]; - } - for(j=i;j>s1)&1LL)<>s1)&1LL); - is32&=~(1LL<=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU - is32|=1LL<=0x24&&op2<=0x27) { // AND/OR/XOR/NOR - uint64_t sr=((is32>>s1)&(is32>>s2)&1LL); - is32&=~(1LL<=0x2c&&op2<=0x2d) { // DADD/DADDU - if(s1==0&&s2==0) { - is32|=1LL<>s1)&1LL); - is32&=~(1LL<>s2)&1LL); - is32&=~(1LL<=0x2e&&op2<=0x2f) { // DSUB/DSUBU - if(s1==0&&s2==0) { - is32|=1LL<>s1)&1LL); - is32&=~(1LL<=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU - is32&=~((1LL<>s1)&1LL); - is32&=~(1LL<=0x14&&op2<=0x17) is32&=~(1LL<=0x38&&op2<0x3f) is32&=~(1LL<0) - { - if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000) - { - if(rt1[i-1]==31) // JAL/JALR - { - // Subroutine call will return here, don't alloc any registers - is32=1; - } - else if(i+1=0;i--) - { - int hr; - if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) - { - if(ba[i]=(start+slen*4)) - { - // Branch out of this block, don't need anything - r32=0; - } - else - { - // Internal branch - // Need whatever matches the target - // (and doesn't get overwritten by the delay slot instruction) - r32=0; - int t=(ba[i]-start)>>2; - if(ba[i]>start+i*4) { - // Forward branch - //if(!(requires_32bit[t]&~regs[i].was32)) - // r32|=requires_32bit[t]&(~(1LL<>16)!=0x1000) - { - if(i0) - { - if((regs[i].was32>>us1[i+1])&1) r32|=1LL<0) - { - if((regs[i].was32>>us2[i+1])&1) r32|=1LL<>dep1[i+1])&1)) - { - if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<>dep2[i+1])&1)) - { - if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<0) - { - if((regs[i].was32>>us1[i])&1) r32|=1LL<0) - { - if((regs[i].was32>>us2[i])&1) r32|=1LL<>dep1[i])&1)) - { - if((regs[i].was32>>dep1[i])&1) r32|=1LL<>dep2[i])&1)) - { - if((regs[i].was32>>dep2[i])&1) r32|=1LL<0&®s[i].regmap_entry[hr]<64) { - if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) { - if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1)) - pr32[i]|=1LL<=istart;i--) { - if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) + if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP) { if(ba[i]=(start+slen*4)) { @@ -7753,7 +6191,7 @@ void clean_registers(int istart,int iend,int wr) if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<istart) { - if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP) + if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP) { // Don't store a register immediately after writing it, // may prevent dual-issue. @@ -7776,18 +6214,18 @@ void clean_registers(int istart,int iend,int wr) } printf("\n");*/ - //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) { + //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP)) { regs[i].dirty|=will_dirty_i; #ifndef DESTRUCTIVE_WRITEBACK regs[i].dirty&=wont_dirty_i; - if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) + if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP) { if(i>16)!=0x1000) { for(r=0;r>r)&1));*/} + }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/} } } } @@ -7799,7 +6237,7 @@ void clean_registers(int istart,int iend,int wr) if(r!=EXCLUDE_REG) { if(regs[i].regmap[r]==regmap_pre[i+1][r]) { regs[i+1].wasdirty&=wont_dirty_i|~(1<>r)&1));*/} + }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/} } } } @@ -7842,7 +6280,7 @@ void clean_registers(int istart,int iend,int wr) wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<>r)&1));*/ + /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/ } } } @@ -7862,8 +6300,6 @@ void disassemble_inst(int i) printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break; case SJUMP: printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break; - case FJUMP: - printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break; case RJUMP: if (opcode[i]==0x9&&rt1[i]!=31) printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]); @@ -7943,12 +6379,48 @@ void disassemble_inst(int i) static void disassemble_inst(int i) {} #endif // DISASM +#define DRC_TEST_VAL 0x74657374 + +static void new_dynarec_test(void) +{ + int (*testfunc)(void); + void *beginning; + int ret[2]; + size_t i; + + // check structure linkage + if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs)) + { + SysPrintf("linkage_arm* miscompilation/breakage detected.\n"); + } + + SysPrintf("testing if we can run recompiled code...\n"); + ((volatile u_int *)out)[0]++; // make cache dirty + + for (i = 0; i < ARRAY_SIZE(ret); i++) { + out = translation_cache; + beginning = start_block(); + emit_movimm(DRC_TEST_VAL + i, 0); // test + emit_ret(); + literal_pool(0); + end_block(beginning); + testfunc = beginning; + ret[i] = testfunc(); + } + + if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1) + SysPrintf("test passed.\n"); + else + SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]); + out = translation_cache; +} + // clear the state completely, instead of just marking // things invalid like invalidate_all_pages() does void new_dynarec_clear_full() { int n; - out=(u_char *)BASE_ADDR; + out = translation_cache; memset(invalid_code,1,sizeof(invalid_code)); memset(hash_table,0xff,sizeof(hash_table)); memset(mini_ht,-1,sizeof(mini_ht)); @@ -7961,15 +6433,6 @@ void new_dynarec_clear_full() stop_after_jal=0; inv_code_start=inv_code_end=~0; // TLB -#ifndef DISABLE_TLB - using_tlb=0; - for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF - memory_map[n]=-1; - for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF - memory_map[n]=((u_int)rdram-0x80000000)>>2; - for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF - memory_map[n]=-1; -#endif for(n=0;n<4096;n++) ll_clear(jump_in+n); for(n=0;n<4096;n++) ll_clear(jump_out+n); for(n=0;n<4096;n++) ll_clear(jump_dirty+n); @@ -7977,174 +6440,241 @@ void new_dynarec_clear_full() void new_dynarec_init() { - printf("Init new dynarec\n"); - out=(u_char *)BASE_ADDR; - if (mmap (out, 1<= 0x80000000 && addr < 0x80000000+RAM_SIZE) { + *limit = (addr & 0x80600000) + 0x00200000; + return (u_int *)(rdram + (addr&0x1fffff)); + } + return NULL; +} + +static u_int scan_for_ret(u_int addr) +{ + u_int limit = 0; + u_int *mem; + + mem = get_source_start(addr, &limit); + if (mem == NULL) + return addr; + + if (limit > addr + 0x1000) + limit = addr + 0x1000; + for (; addr < limit; addr += 4, mem++) { + if (*mem == 0x03e00008) // jr $ra + return addr + 8; + } + return addr; +} + +struct savestate_block { + uint32_t addr; + uint32_t regflags; +}; + +static int addr_cmp(const void *p1_, const void *p2_) +{ + const struct savestate_block *p1 = p1_, *p2 = p2_; + return p1->addr - p2->addr; +} + +int new_dynarec_save_blocks(void *save, int size) +{ + struct savestate_block *blocks = save; + int maxcount = size / sizeof(blocks[0]); + struct savestate_block tmp_blocks[1024]; + struct ll_entry *head; + int p, s, d, o, bcnt; + u_int addr; + + o = 0; + for (p = 0; p < ARRAY_SIZE(jump_in); p++) { + bcnt = 0; + for (head = jump_in[p]; head != NULL; head = head->next) { + tmp_blocks[bcnt].addr = head->vaddr; + tmp_blocks[bcnt].regflags = head->reg_sv_flags; + bcnt++; + } + if (bcnt < 1) + continue; + qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp); + + addr = tmp_blocks[0].addr; + for (s = d = 0; s < bcnt; s++) { + if (tmp_blocks[s].addr < addr) + continue; + if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr) + tmp_blocks[d++] = tmp_blocks[s]; + addr = scan_for_ret(tmp_blocks[s].addr); + } + + if (o + d > maxcount) + d = maxcount - o; + memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0])); + o += d; + } + + return o * sizeof(blocks[0]); +} + +void new_dynarec_load_blocks(const void *save, int size) +{ + const struct savestate_block *blocks = save; + int count = size / sizeof(blocks[0]); + u_int regs_save[32]; + uint32_t f; + int i, b; + + get_addr(psxRegs.pc); + + // change GPRs for speculation to at least partially work.. + memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save)); + for (i = 1; i < 32; i++) + psxRegs.GPR.r[i] = 0x80000000; + + for (b = 0; b < count; b++) { + for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) { + if (f & 1) + psxRegs.GPR.r[i] = 0x1f800000; + } + + get_addr(blocks[b].addr); + + for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) { + if (f & 1) + psxRegs.GPR.r[i] = 0x80000000; + } + } + + memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save)); +} + +int new_recompile_block(u_int addr) { -/* - if(addr==0x800cd050) { - int block; - for(block=0x80000;block<0x80800;block++) invalidate_block(block); - int n; - for(n=0;n<=2048;n++) ll_clear(jump_dirty+n); - } -*/ - //if(Count==365117028) tracedebug=1; - assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out); - //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out); + u_int pagelimit = 0; + u_int state_rflags = 0; + int i; + + assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out); //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr); - //if(debug) - //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum()); + //if(debug) //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29); - /*if(Count>=312978186) { - rlist(); - }*/ - //rlist(); + + // this is just for speculation + for (i = 1; i < 32; i++) { + if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000) + state_rflags |= 1 << i; + } + start = (u_int)addr&~3; - //assert(((u_int)addr&1)==0); + //assert(((u_int)addr&1)==0); // start-in-delay-slot flag new_dynarec_did_compile=1; -#ifdef PCSX if (Config.HLE && start == 0x80001000) // hlecall { // XXX: is this enough? Maybe check hleSoftCall? - u_int beginning=(u_int)out; + void *beginning=start_block(); u_int page=get_page(start); + invalid_code[start>>12]=0; emit_movimm(start,0); - emit_writeword(0,(int)&pcaddr); - emit_jmp((int)new_dyna_leave); + emit_writeword(0,&pcaddr); + emit_jmp(new_dyna_leave); literal_pool(0); -#ifdef __arm__ - __clear_cache((void *)beginning,out); -#endif - ll_add(jump_in+page,start,(void *)beginning); + end_block(beginning); + ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning); return 0; } - else if ((u_int)addr < 0x00200000 || - (0xa0000000 <= addr && addr < 0xa0200000)) { - // used for BIOS calls mostly? - source = (u_int *)((u_int)rdram+(start&0x1fffff)); - pagelimit = (addr&0xa0000000)|0x00200000; - } - else if (!Config.HLE && ( -/* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/ - (0xbfc00000 <= addr && addr < 0xbfc80000))) { - // BIOS - source = (u_int *)((u_int)psxR+(start&0x7ffff)); - pagelimit = (addr&0xfff00000)|0x80000; - } - else -#endif -#ifdef MUPEN64 - if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) { - source = (u_int *)((u_int)SP_DMEM+start-0xa4000000); - pagelimit = 0xa4001000; - } - else -#endif - if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) { - source = (u_int *)((u_int)rdram+start-0x80000000); - pagelimit = 0x80000000+RAM_SIZE; - } -#ifndef DISABLE_TLB - else if ((signed int)addr >= (signed int)0xC0000000) { - //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2)); - //if(tlb_LUT_r[start>>12]) - //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000); - if((signed int)memory_map[start>>12]>=0) { - source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2))); - pagelimit=(start+4096)&0xFFFFF000; - int map=memory_map[start>>12]; - int i; - for(i=0;i<5;i++) { - //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]); - if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096; - } - assem_debug("pagelimit=%x\n",pagelimit); - assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start); - } - else { - assem_debug("Compile at unmapped memory address: %x \n", (int)addr); - //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]); - return -1; // Caller will invoke exception handler - } - //printf("source= %x\n",(int)source); - } -#endif - else { - printf("Compile at bogus memory address: %x \n", (int)addr); - exit(1); + + source = get_source_start(start, &pagelimit); + if (source == NULL) { + SysPrintf("Compile at bogus memory address: %08x\n", addr); + abort(); } /* Pass 1: disassemble */ @@ -8158,12 +6688,12 @@ int new_recompile_block(int addr) /* Pass 9: linker */ /* Pass 10: garbage collection / free memory */ - int i,j; + int j; int done=0; unsigned int type,op,op2; //printf("addr = %x source = %x %x\n", addr,source,source[0]); - + /* Pass 1 disassembly */ for(i=0;!done;i++) { @@ -8211,7 +6741,7 @@ int new_recompile_block(int addr) case 0x33: strcpy(insn[i],"TLTU"); type=NI; break; case 0x34: strcpy(insn[i],"TEQ"); type=NI; break; case 0x36: strcpy(insn[i],"TNE"); type=NI; break; -#ifndef FORCE32 +#if 0 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break; case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break; case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break; @@ -8271,138 +6801,16 @@ int new_recompile_block(int addr) switch(op2) { case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break; + case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break; case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break; - case 0x10: strcpy(insn[i],"tlb"); type=NI; - switch(source[i]&0x3f) - { - case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break; - case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break; - case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break; - case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break; -#ifdef PCSX - case 0x10: strcpy(insn[i],"RFE"); type=COP0; break; -#else - case 0x18: strcpy(insn[i],"ERET"); type=COP0; break; -#endif - } + case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break; + case 0x10: strcpy(insn[i],"RFE"); type=COP0; break; } break; - case 0x11: strcpy(insn[i],"cop1"); type=NI; + case 0x11: strcpy(insn[i],"cop1"); type=COP1; op2=(source[i]>>21)&0x1f; - switch(op2) - { - case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break; - case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break; - case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break; - case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break; - case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break; - case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break; - case 0x08: strcpy(insn[i],"BC1"); type=FJUMP; - switch((source[i]>>16)&0x3) - { - case 0x00: strcpy(insn[i],"BC1F"); break; - case 0x01: strcpy(insn[i],"BC1T"); break; - case 0x02: strcpy(insn[i],"BC1FL"); break; - case 0x03: strcpy(insn[i],"BC1TL"); break; - } - break; - case 0x10: strcpy(insn[i],"C1.S"); type=NI; - switch(source[i]&0x3f) - { - case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break; - case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break; - case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break; - case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break; - case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break; - case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break; - case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break; - case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break; - case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break; - case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break; - case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break; - case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break; - case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break; - case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break; - case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break; - case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break; - case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break; - case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break; - case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break; - case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break; - case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break; - case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break; - case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break; - case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break; - case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break; - case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break; - case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break; - case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break; - case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break; - case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break; - case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break; - case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break; - case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break; - case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break; - case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break; - } - break; - case 0x11: strcpy(insn[i],"C1.D"); type=NI; - switch(source[i]&0x3f) - { - case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break; - case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break; - case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break; - case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break; - case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break; - case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break; - case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break; - case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break; - case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break; - case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break; - case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break; - case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break; - case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break; - case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break; - case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break; - case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break; - case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break; - case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break; - case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break; - case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break; - case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break; - case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break; - case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break; - case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break; - case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break; - case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break; - case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break; - case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break; - case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break; - case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break; - case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break; - case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break; - case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break; - case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break; - case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break; - } - break; - case 0x14: strcpy(insn[i],"C1.W"); type=NI; - switch(source[i]&0x3f) - { - case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break; - case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break; - } - break; - case 0x15: strcpy(insn[i],"C1.L"); type=NI; - switch(source[i]&0x3f) - { - case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break; - case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break; - } - break; - } break; -#ifndef FORCE32 +#if 0 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break; case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break; case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break; @@ -8419,14 +6827,14 @@ int new_recompile_block(int addr) case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break; case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break; case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break; -#ifndef FORCE32 +#if 0 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break; #endif case 0x28: strcpy(insn[i],"SB"); type=STORE; break; case 0x29: strcpy(insn[i],"SH"); type=STORE; break; case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break; case 0x2B: strcpy(insn[i],"SW"); type=STORE; break; -#ifndef FORCE32 +#if 0 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break; case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break; #endif @@ -8434,22 +6842,21 @@ int new_recompile_block(int addr) case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break; case 0x30: strcpy(insn[i],"LL"); type=NI; break; case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break; -#ifndef FORCE32 +#if 0 case 0x34: strcpy(insn[i],"LLD"); type=NI; break; case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break; case 0x37: strcpy(insn[i],"LD"); type=LOAD; break; #endif case 0x38: strcpy(insn[i],"SC"); type=NI; break; case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break; -#ifndef FORCE32 +#if 0 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break; case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break; case 0x3F: strcpy(insn[i],"SD"); type=STORE; break; #endif -#ifdef PCSX case 0x12: strcpy(insn[i],"COP2"); type=NI; op2=(source[i]>>21)&0x1f; - //if (op2 & 0x10) { + //if (op2 & 0x10) if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns if (gte_handlers[source[i]&0x3f]!=NULL) { if (gte_regnames[source[i]&0x3f]!=NULL) @@ -8470,17 +6877,14 @@ int new_recompile_block(int addr) case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break; case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break; case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break; -#endif default: strcpy(insn[i],"???"); type=NI; - printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr); + SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr); break; } itype[i]=type; opcode2[i]=op2; /* Get registers/immediates */ lt1[i]=0; - us1[i]=0; - us2[i]=0; dep1[i]=0; dep2[i]=0; gte_rs[i]=gte_rt[i]=0; @@ -8499,7 +6903,6 @@ int new_recompile_block(int addr) rt1[i]=0; rt2[i]=0; imm[i]=(short)source[i]; - if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD break; case LOADLR: // LWL/LWR only load part of the register, @@ -8509,7 +6912,6 @@ int new_recompile_block(int addr) rt1[i]=(source[i]>>16)&0x1f; rt2[i]=0; imm[i]=(short)source[i]; - if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL if(op==0x26) dep1[i]=rt1[i]; // LWR break; case IMM16: @@ -8523,8 +6925,6 @@ int new_recompile_block(int addr) }else{ imm[i]=(short)source[i]; } - if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU - if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI break; case UJUMP: @@ -8557,8 +6957,6 @@ int new_recompile_block(int addr) if(op&2) { // BGTZ/BLEZ rs2[i]=0; } - us1[i]=rs1[i]; - us2[i]=rs2[i]; likely[i]=op>>4; break; case SJUMP: @@ -8566,29 +6964,18 @@ int new_recompile_block(int addr) rs2[i]=CCREG; rt1[i]=0; rt2[i]=0; - us1[i]=rs1[i]; if(op2&0x10) { // BxxAL rt1[i]=31; // NOTE: If the branch is not taken, r31 is still overwritten } likely[i]=(op2&2)>>1; break; - case FJUMP: - rs1[i]=FSREG; - rs2[i]=CSREG; - rt1[i]=0; - rt2[i]=0; - likely[i]=((source[i])>>17)&1; - break; case ALU: rs1[i]=(source[i]>>21)&0x1f; // source rs2[i]=(source[i]>>16)&0x1f; // subtract amount rt1[i]=(source[i]>>11)&0x1f; // destination rt2[i]=0; - if(op2==0x2a||op2==0x2b) { // SLT/SLTU - us1[i]=rs1[i];us2[i]=rs2[i]; - } - else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR + if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR dep1[i]=rs1[i];dep2[i]=rs2[i]; } else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB @@ -8600,9 +6987,6 @@ int new_recompile_block(int addr) rs2[i]=(source[i]>>16)&0x1f; // divisor rt1[i]=HIREG; rt2[i]=LOREG; - if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU - us1[i]=rs1[i];us2[i]=rs2[i]; - } break; case MOV: rs1[i]=0; @@ -8622,8 +7006,6 @@ int new_recompile_block(int addr) rs2[i]=(source[i]>>21)&0x1f; // shift amount rt1[i]=(source[i]>>11)&0x1f; // destination rt2[i]=0; - // DSLLV/DSRLV/DSRAV are 64-bit - if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i]; break; case SHIFTIMM: rs1[i]=(source[i]>>16)&0x1f; @@ -8633,16 +7015,14 @@ int new_recompile_block(int addr) imm[i]=(source[i]>>6)&0x1f; // DSxx32 instructions if(op2>=0x3c) imm[i]|=0x20; - // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source - if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i]; break; case COP0: rs1[i]=0; rs2[i]=0; rt1[i]=0; rt2[i]=0; - if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0 - if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0 + if(op2==0||op2==2) rt1[i]=(source[i]>>16)&0x1F; // MFC0/CFC0 + if(op2==4||op2==6) rs1[i]=(source[i]>>16)&0x1F; // MTC0/CTC0 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET break; @@ -8653,7 +7033,6 @@ int new_recompile_block(int addr) rt2[i]=0; if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1 - if(op2==5) us1[i]=rs1[i]; // DMTC1 rs2[i]=CSREG; break; case COP2: @@ -8704,19 +7083,6 @@ int new_recompile_block(int addr) else gte_rs[i]|=3ll<<(v*2); } break; - case FLOAT: - case FCONV: - rs1[i]=0; - rs2[i]=CSREG; - rt1[i]=0; - rt2[i]=0; - break; - case FCOMP: - rs1[i]=FSREG; - rs2[i]=CSREG; - rt1[i]=FSREG; - rt2[i]=0; - break; case SYSCALL: case HLECALL: case INTCALL: @@ -8738,16 +7104,15 @@ int new_recompile_block(int addr) ba[i]=start+i*4+8; // Ignore never taken branch else if(type==SJUMP&&rs1[i]==0&&!(op2&1)) ba[i]=start+i*4+8; // Ignore never taken branch - else if(type==CJUMP||type==SJUMP||type==FJUMP) + else if(type==CJUMP||type==SJUMP) ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14); else ba[i]=-1; -#ifdef PCSX - if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) { + if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP)) { int do_in_intrp=0; // branch in delay slot? - if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) { + if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP) { // don't handle first branch and call interpreter if it's hit - printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr); + SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr); do_in_intrp=1; } // basic load delay detection @@ -8755,14 +7120,14 @@ int new_recompile_block(int addr) int t=(ba[i-1]-start)/4; if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) { // jump target wants DS result - potential load delay effect - printf("load delay @%08x (%08x)\n", addr + i*4, addr); + SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr); do_in_intrp=1; bt[t+1]=1; // expected return from interpreter } else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&& !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) { // v0 overwrite like this is a sign of trouble, bail out - printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr); + SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr); do_in_intrp=1; } } @@ -8775,7 +7140,6 @@ int new_recompile_block(int addr) i--; // don't compile the DS } } -#endif /* Is this the end of the block? */ if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) { if(rt1[i-1]==0) { // Continue past subroutine call (JAL) @@ -8809,11 +7173,11 @@ int new_recompile_block(int addr) // Stop if we're compiling junk if(itype[i]==NI&&opcode[i]==0x11) { done=stop_after_jal=1; - printf("Disabled speculative precompilation\n"); + SysPrintf("Disabled speculative precompilation\n"); } } slen=i; - if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) { + if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP) { if(start+i*4==pagelimit) { itype[i-1]=SPAN; } @@ -8823,14 +7187,12 @@ int new_recompile_block(int addr) /* Pass 2 - Register dependencies and branch targets */ unneeded_registers(0,slen-1,0); - + /* Pass 3 - Register allocation */ struct regstat current; // Current register allocations/status - current.is32=1; current.dirty=0; current.u=unneeded_reg[0]; - current.uu=unneeded_reg_upper[0]; clear_all_regs(current.regmap); alloc_reg(¤t,0,CCREG); dirty_reg(¤t,CCREG); @@ -8841,19 +7203,15 @@ int new_recompile_block(int addr) int cc=0; int hr=-1; -#ifndef FORCE32 - provisional_32bit(); -#endif if((u_int)addr&1) { // First instruction is delay slot cc=-1; bt[1]=1; ds=1; unneeded_reg[0]=1; - unneeded_reg_upper[0]=1; current.regmap[HOST_BTREG]=BTREG; } - + for(i=0;i1) - { - if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL - { - if(rs1[i-2]==0||rs2[i-2]==0) - { - if(rs1[i-2]) { - current.is32|=1LL<=0) current.regmap[hr]=-1; - } - if(rs2[i-2]) { - current.is32|=1LL<=0) current.regmap[hr]=-1; - } - } - } - } -#ifndef FORCE32 - // If something jumps here with 64-bit values - // then promote those registers to 64 bits - if(bt[i]) - { - uint64_t temp_is32=current.is32; - for(j=i-1;j>=0;j--) - { - if(ba[j]==start+i*4) - temp_is32&=branch_regs[j].is32; - } - for(j=i;j0&&r<64) - { - if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) { - temp_is32|=1LL<=0;j--) - { - if(ba[j]==start+i*4+4) - temp_is32&=branch_regs[j].is32; - } - for(j=i;j0) - { - if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) { - if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) - { - if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)) - { - //printf("dump %d/r%d\n",hr,r); - current.regmap[hr]=-1; - if(get_reg(current.regmap,r|64)>=0) - current.regmap[get_reg(current.regmap,r|64)]=-1; - } - } - } - } - } - } - } - else if(i>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)) - { - uint64_t temp_is32=current.is32; - for(j=i-1;j>=0;j--) - { - if(ba[j]==start+i*4+8) - temp_is32&=branch_regs[j].is32; - } - for(j=i;j0) - { - if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) { - if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63)) - { - //printf("dump %d/r%d\n",hr,r); - current.regmap[hr]=-1; - if(get_reg(current.regmap,r|64)>=0) - current.regmap[get_reg(current.regmap,r|64)]=-1; - } - } - } - } - } - } - #endif - if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) { + if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP) { if(i+1>rt1[i])&1) current.uu&=~((1LL<>rt1[i+1])&1) current.uu&=~((1LL<>rt1[i])&1) current.uu&=~((1LL<>r)&1) { regs[i].regmap_entry[hr]=-1; regs[i].regmap[hr]=-1; @@ -9076,20 +7284,10 @@ int new_recompile_block(int addr) //current.regmap[hr]=-1; }else regs[i].regmap_entry[hr]=r; - } - else { - if((current.uu>>(r&63))&1) { - regs[i].regmap_entry[hr]=-1; - regs[i].regmap[hr]=-1; - //Don't clear regs in the delay slot as the branch might need them - //current.regmap[hr]=-1; - }else - regs[i].regmap_entry[hr]=r; - } } } else { // First instruction expects CCREG to be allocated - if(i==0&&hr==HOST_CCREG) + if(i==0&&hr==HOST_CCREG) regs[i].regmap_entry[hr]=CCREG; else regs[i].regmap_entry[hr]=-1; @@ -9113,7 +7311,6 @@ int new_recompile_block(int addr) #ifdef REG_PREFETCH alloc_reg(¤t,i,PTEMP); #endif - //current.is32|=1LL<>rs1[i])&(current.is32>>rs2[i])&1)) - { - if(rs1[i]) alloc_reg64(¤t,i,rs1[i]); - if(rs2[i]) alloc_reg64(¤t,i,rs2[i]); - } if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))|| (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) { // The delay slot overwrites one of our conditions. @@ -9189,11 +7379,6 @@ int new_recompile_block(int addr) regs[i].wasconst=0; if(rs1[i]) alloc_reg(¤t,i,rs1[i]); if(rs2[i]) alloc_reg(¤t,i,rs2[i]); - if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1)) - { - if(rs1[i]) alloc_reg64(¤t,i,rs1[i]); - if(rs2[i]) alloc_reg64(¤t,i,rs2[i]); - } } else { @@ -9207,10 +7392,6 @@ int new_recompile_block(int addr) alloc_cc(¤t,i); dirty_reg(¤t,CCREG); alloc_reg(¤t,i,rs1[i]); - if(!(current.is32>>rs1[i]&1)) - { - alloc_reg64(¤t,i,rs1[i]); - } if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) { // The delay slot overwrites one of our conditions. // Allocate the branch condition registers instead. @@ -9218,10 +7399,6 @@ int new_recompile_block(int addr) current.wasconst=0; regs[i].wasconst=0; if(rs1[i]) alloc_reg(¤t,i,rs1[i]); - if(!((current.is32>>rs1[i])&1)) - { - if(rs1[i]) alloc_reg64(¤t,i,rs1[i]); - } } else { @@ -9240,11 +7417,6 @@ int new_recompile_block(int addr) dirty_reg(¤t,CCREG); alloc_reg(¤t,i,rs1[i]); alloc_reg(¤t,i,rs2[i]); - if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1)) - { - alloc_reg64(¤t,i,rs1[i]); - alloc_reg64(¤t,i,rs2[i]); - } } else if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL @@ -9255,10 +7427,6 @@ int new_recompile_block(int addr) alloc_cc(¤t,i); dirty_reg(¤t,CCREG); alloc_reg(¤t,i,rs1[i]); - if(!(current.is32>>rs1[i]&1)) - { - alloc_reg64(¤t,i,rs1[i]); - } } ds=1; //current.isconst=0; @@ -9275,17 +7443,12 @@ int new_recompile_block(int addr) alloc_cc(¤t,i); dirty_reg(¤t,CCREG); alloc_reg(¤t,i,rs1[i]); - if(!(current.is32>>rs1[i]&1)) - { - alloc_reg64(¤t,i,rs1[i]); - } if (rt1[i]==31) { // BLTZAL/BGEZAL alloc_reg(¤t,i,31); dirty_reg(¤t,31); //#ifdef REG_PREFETCH //alloc_reg(¤t,i,PTEMP); //#endif - //current.is32|=1LL<>rs1[i])&1)) - { - if(rs1[i]) alloc_reg64(¤t,i,rs1[i]); - } } else { @@ -9315,55 +7474,10 @@ int new_recompile_block(int addr) alloc_cc(¤t,i); dirty_reg(¤t,CCREG); alloc_reg(¤t,i,rs1[i]); - if(!(current.is32>>rs1[i]&1)) - { - alloc_reg64(¤t,i,rs1[i]); - } } ds=1; //current.isconst=0; break; - case FJUMP: - current.isconst=0; - current.wasconst=0; - regs[i].wasconst=0; - if(likely[i]==0) // BC1F/BC1T - { - // TODO: Theoretically we can run out of registers here on x86. - // The delay slot can allocate up to six, and we need to check - // CSREG before executing the delay slot. Possibly we can drop - // the cycle count and then reload it after checking that the - // FPU is in a usable state, or don't do out-of-order execution. - alloc_cc(¤t,i); - dirty_reg(¤t,CCREG); - alloc_reg(¤t,i,FSREG); - alloc_reg(¤t,i,CSREG); - if(itype[i+1]==FCOMP) { - // The delay slot overwrites the branch condition. - // Allocate the branch condition registers instead. - alloc_cc(¤t,i); - dirty_reg(¤t,CCREG); - alloc_reg(¤t,i,CSREG); - alloc_reg(¤t,i,FSREG); - } - else { - ooo[i]=1; - delayslot_alloc(¤t,i+1); - alloc_reg(¤t,i+1,CSREG); - } - } - else - // Don't alloc the delay slot yet because we might not execute it - if(likely[i]) // BC1FL/BC1TL - { - alloc_cc(¤t,i); - dirty_reg(¤t,CCREG); - alloc_reg(¤t,i,CSREG); - alloc_reg(¤t,i,FSREG); - } - ds=1; - current.isconst=0; - break; case IMM16: imm16_alloc(¤t,i); break; @@ -9395,7 +7509,7 @@ int new_recompile_block(int addr) break; case COP1: case COP2: - cop1_alloc(¤t,i); + cop12_alloc(¤t,i); break; case C1LS: c1ls_alloc(¤t,i); @@ -9406,15 +7520,6 @@ int new_recompile_block(int addr) case C2OP: c2op_alloc(¤t,i); break; - case FCONV: - fconv_alloc(¤t,i); - break; - case FLOAT: - float_alloc(¤t,i); - break; - case FCOMP: - fcomp_alloc(¤t,i); - break; case SYSCALL: case HLECALL: case INTCALL: @@ -9424,25 +7529,11 @@ int new_recompile_block(int addr) pagespan_alloc(¤t,i); break; } - - // Drop the upper half of registers that have become 32-bit - current.uu|=current.is32&((1LL<>rt1[i])&1) current.uu&=~((1LL<>rt1[i+1])&1) current.uu&=~((1LL<=0) { if(r!=regmap_pre[i][hr]) { @@ -9466,7 +7557,8 @@ int new_recompile_block(int addr) regs[i].regmap_entry[hr]=0; } else - if(r<64){ + { + assert(r<64); if((current.u>>r)&1) { regs[i].regmap_entry[hr]=-1; //regs[i].regmap[hr]=-1; @@ -9474,18 +7566,10 @@ int new_recompile_block(int addr) }else regs[i].regmap_entry[hr]=r; } - else { - if((current.uu>>(r&63))&1) { - regs[i].regmap_entry[hr]=-1; - //regs[i].regmap[hr]=-1; - current.regmap[hr]=-1; - }else - regs[i].regmap_entry[hr]=r; - } } } else { // Branches expect CCREG to be allocated at the target - if(regmap_pre[i][hr]==CCREG) + if(regmap_pre[i][hr]==CCREG) regs[i].regmap_entry[hr]=CCREG; else regs[i].regmap_entry[hr]=-1; @@ -9504,7 +7588,6 @@ int new_recompile_block(int addr) /* Branch post-alloc */ if(i>0) { - current.was32=current.is32; current.wasdirty=current.dirty; switch(itype[i-1]) { case UJUMP: @@ -9512,13 +7595,11 @@ int new_recompile_block(int addr) branch_regs[i-1].isconst=0; branch_regs[i-1].wasconst=0; branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<>rt1[i])&1) current.uu&=~((1LL<>rs1[i-1])&(current.is32>>rs2[i-1])&1)) - { - if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]); - if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]); - } } memcpy(&branch_regs[i-1],¤t,sizeof(current)); branch_regs[i-1].isconst=0; @@ -9593,23 +7661,15 @@ int new_recompile_block(int addr) // The delay slot overwrote the branch condition // Delay slot goes after the test (in order) current.u=branch_unneeded_reg[i-1]&~((1LL<>rt1[i])&1) current.uu&=~((1LL<>rs1[i-1]&1)) - { - alloc_reg64(¤t,i-1,rs1[i-1]); - } } memcpy(&branch_regs[i-1],¤t,sizeof(current)); branch_regs[i-1].isconst=0; @@ -9623,23 +7683,6 @@ int new_recompile_block(int addr) { memcpy(&branch_regs[i-1],¤t,sizeof(current)); branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<>rt1[i])&1) current.uu&=~((1LL<>rs1[i-1]&1)) - { - alloc_reg64(¤t,i-1,rs1[i-1]); - } - } - memcpy(&branch_regs[i-1],¤t,sizeof(current)); - branch_regs[i-1].isconst=0; - branch_regs[i-1].wasconst=0; - memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); - memcpy(constmap[i],constmap[i-1],sizeof(current_constmap)); - } else - // Alloc the delay slot in case the branch is taken - if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL + if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL { memcpy(&branch_regs[i-1],¤t,sizeof(current)); branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL)) + if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i]==SYSCALL||itype[i]==HLECALL)) { cc=0; } -#if defined(PCSX) && !defined(DRC_DBG) +#if !defined(DRC_DBG) else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2) { // GTE runs in parallel until accessed, divide by 2 for a rough guess cc+=gte_cycletab[source[i]&0x3f]/2; } - else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues + else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues { cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER) } + else if(i>1&&itype[i]==STORE&&itype[i-1]==STORE&&itype[i-2]==STORE&&!bt[i]) + { + cc+=4; + } else if(itype[i]==C2LS) { cc+=4; @@ -9815,9 +7823,7 @@ int new_recompile_block(int addr) cc++; } - flush_dirty_uppers(¤t); if(!is_ds[i]) { - regs[i].is32=current.is32; regs[i].dirty=current.dirty; regs[i].isconst=current.isconst; memcpy(constmap[i],current_constmap,sizeof(current_constmap)); @@ -9832,15 +7838,15 @@ int new_recompile_block(int addr) if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1; regs[i].waswritten=current.waswritten; } - + /* Pass 4 - Cull unused host registers */ - + uint64_t nr=0; - + for (i=slen-1;i>=0;i--) { int hr; - if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) + if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP) { if(ba[i]=(start+slen*4)) { @@ -9884,22 +7890,10 @@ int new_recompile_block(int addr) if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<>dep1[i+1])&1)) { - if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<>dep2[i+1])&1)) { - if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<>dep1[i])&1)) { - if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<>dep2[i])&1)) { - if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) { - if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) || - (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) { + if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) { if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) || - (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) { + if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) { if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0) - { - d1=dep1[i+1]; - d2=dep2[i+1]; - } - if(using_tlb) { - if(itype[i+1]==LOAD || itype[i+1]==LOADLR || - itype[i+1]==STORE || itype[i+1]==STORELR || - itype[i+1]==C1LS || itype[i+1]==C2LS) - map=TLREG; - } else + int map=0,temp=0; if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2 map=INVCP; @@ -10024,8 +7993,6 @@ int new_recompile_block(int addr) if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] && (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] && (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] && - (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] && - (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 && regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] && (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP && regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL && @@ -10037,8 +8004,6 @@ int new_recompile_block(int addr) if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] && (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] && (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] && - (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] && - (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 && branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] && (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP && branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL && @@ -10062,18 +8027,8 @@ int new_recompile_block(int addr) // Non-branch if(i>0) { - int d1=0,d2=0,map=-1,temp=-1; - if(get_reg(regs[i].regmap,rt1[i]|64)>=0) - { - d1=dep1[i]; - d2=dep2[i]; - } - if(using_tlb) { - if(itype[i]==LOAD || itype[i]==LOADLR || - itype[i]==STORE || itype[i]==STORELR || - itype[i]==C1LS || itype[i]==C2LS) - map=TLREG; - } else if(itype[i]==STORE || itype[i]==STORELR || + int map=-1,temp=-1; + if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2 map=INVCP; } @@ -10081,18 +8036,16 @@ int new_recompile_block(int addr) itype[i]==C1LS || itype[i]==C2LS) temp=FTEMP; if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] && - (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] && - (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 && regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] && (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map && (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG)) { if(i0) if(regmap_pre[i+1][hr]!=regs[i].regmap[hr]) - if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1)) { - printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]); + SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]); assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]); } regmap_pre[i+1][hr]=-1; @@ -10104,41 +8057,35 @@ int new_recompile_block(int addr) } } } - } - } + } // if needed + } // for hr } - + /* Pass 5 - Pre-allocate registers */ - + // If a register is allocated during a loop, try to allocate it for the // entire loop, if possible. This avoids loading/storing registers // inside of the loop. - + signed char f_regmap[HOST_REGS]; clear_all_regs(f_regmap); for(i=0;i=start && ba[i]<(start+i*4)) + if(ba[i]>=start && ba[i]<(start+i*4)) if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS - ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT - ||itype[i+1]==FCOMP||itype[i+1]==FCONV + ||itype[i+1]==SHIFT||itype[i+1]==COP1 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP) { int t=(ba[i]-start)>>2; - if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots + if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP)) // loop_preload can't handle jumps into delay slots if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated for(hr=0;hr64) { - if(!((regs[i].dirty>>hr)&1)) - f_regmap[hr]=regs[i].regmap[hr]; - else f_regmap[hr]=-1; - } - else if(regs[i].regmap[hr]>=0) { + if(regs[i].regmap[hr]>=0) { if(f_regmap[hr]!=regs[i].regmap[hr]) { // dealloc old register int n; @@ -10150,12 +8097,7 @@ int new_recompile_block(int addr) f_regmap[hr]=regs[i].regmap[hr]; } } - if(branch_regs[i].regmap[hr]>64) { - if(!((branch_regs[i].dirty>>hr)&1)) - f_regmap[hr]=branch_regs[i].regmap[hr]; - else f_regmap[hr]=-1; - } - else if(branch_regs[i].regmap[hr]>=0) { + if(branch_regs[i].regmap[hr]>=0) { if(f_regmap[hr]!=branch_regs[i].regmap[hr]) { // dealloc old register int n; @@ -10168,10 +8110,10 @@ int new_recompile_block(int addr) } } if(ooo[i]) { - if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) + if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) f_regmap[hr]=branch_regs[i].regmap[hr]; }else{ - if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) + if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) f_regmap[hr]=branch_regs[i].regmap[hr]; } // Avoid dirty->clean transition @@ -10192,15 +8134,7 @@ int new_recompile_block(int addr) { //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r); if(r<34&&((unneeded_reg[j]>>r)&1)) break; - if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break; - if(r>63) { - // NB This can exclude the case where the upper-half - // register is lower numbered than the lower-half - // register. Not sure if it's worth fixing... - if(get_reg(regs[j].regmap,r&63)<0) break; - if(get_reg(regs[j].regmap_entry,r&63)<0) break; - if(regs[j].is32&(1LL<<(r&63))) break; - } + assert(r < 64); if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63) %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r); int k; @@ -10220,7 +8154,7 @@ int new_recompile_block(int addr) //printf("no-match due to different register\n"); break; } - if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) { + if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP) { //printf("no-match due to branch\n"); break; } @@ -10228,22 +8162,9 @@ int new_recompile_block(int addr) if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) { break; } - if(r>63) { - // NB This can exclude the case where the upper-half - // register is lower numbered than the lower-half - // register. Not sure if it's worth fixing... - if(get_reg(regs[k-1].regmap,r&63)<0) break; - if(regs[k-1].is32&(1LL<<(r&63))) break; - } + assert(r < 64); k--; } - if(i\n",hr,start+k*4); while(k>16)!=0x1000) { regmap_pre[k+2][hr]=f_regmap[hr]; regs[k+2].wasdirty&=~(1<>16)==0x1000) { // Stop on unconditional branch break; } - if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) + if(itype[j]==CJUMP||itype[j]==SJUMP) { if(ooo[j]) { - if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) + if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break; }else{ - if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) + if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break; } if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) { @@ -10356,17 +8269,7 @@ int new_recompile_block(int addr) //printf("No free regs for store %x\n",start+j*4); break; } - if(f_regmap[hr]>=64) { - if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) { - break; - } - else - { - if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) { - break; - } - } - } + assert(f_regmap[hr]<64); } } } @@ -10377,11 +8280,7 @@ int new_recompile_block(int addr) for(hr=0;hr64) { - if(!((regs[i].dirty>>hr)&1)) - f_regmap[hr]=regs[i].regmap[hr]; - } - else if(regs[i].regmap[hr]>=0) { + if(regs[i].regmap[hr]>=0) { if(f_regmap[hr]!=regs[i].regmap[hr]) { // dealloc old register int n; @@ -10417,7 +8316,7 @@ int new_recompile_block(int addr) regs[k].isconst&=~(1<i&&f_regmap[HOST_CCREG]==CCREG) @@ -10452,199 +8351,18 @@ int new_recompile_block(int addr) } if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&& itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&& - itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&& - itype[i]!=FCONV&&itype[i]!=FCOMP) + itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1) { memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap)); } } } - - // Cache memory offset or tlb map pointer if a register is available - #ifndef HOST_IMM_ADDR32 - #ifndef RAM_OFFSET - if(using_tlb) - #endif - { - int earliest_available[HOST_REGS]; - int loop_start[HOST_REGS]; - int score[HOST_REGS]; - int end[HOST_REGS]; - int reg=using_tlb?MMREG:ROREG; - // Init - for(hr=0;hr=0) { - score[hr]=0;earliest_available[hr]=i+1; - loop_start[hr]=MAXBLOCK; - } - if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) { - if(branch_regs[i].regmap[hr]>=0) { - score[hr]=0;earliest_available[hr]=i+2; - loop_start[hr]=MAXBLOCK; - } - } - } - // No register allocations after unconditional jumps - if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000) - { - for(hr=0;hr=0) break; - if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) { - if(branch_regs[j].regmap[hr]>=0) break; - if(ooo[j]) { - if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break; - }else{ - if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break; - } - } - else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break; - if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) { - int t=(ba[j]-start)>>2; - if(t=earliest_available[hr]) { - if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated - // Score a point for hoisting loop invariant - if(t>16)==0x1000) - { - // Stop on unconditional branch - break; - } - else - if(itype[j]==LOAD||itype[j]==LOADLR|| - itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) { - score[hr]++; - end[hr]=j; - } - } - } - } - // Find highest score and allocate that register - int maxscore=0; - for(hr=0;hrscore[maxscore]) { - maxscore=hr; - //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4); - } - } - } - if(score[maxscore]>1) - { - if(i=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);} - assert(regs[j].regmap[maxscore]<0); - if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg; - regs[j].regmap[maxscore]=reg; - regs[j].dirty&=~(1<>16)!=0x1000) { - regmap_pre[j+2][maxscore]=reg; - regs[j+2].wasdirty&=~(1<>2; - if(t==loop_start[maxscore]) { - if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated - regs[t].regmap_entry[maxscore]=reg; - } - } - else - { - if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) { - regmap_pre[j+1][maxscore]=reg; - regs[j+1].wasdirty&=~(1<=0) { @@ -10717,46 +8435,6 @@ int new_recompile_block(int addr) } } } - // Preload map address - #ifndef HOST_IMM_ADDR32 - if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) { - hr=get_reg(regs[i+1].regmap,TLREG); - if(hr>=0) { - int sr=get_reg(regs[i+1].regmap,rs1[i+1]); - if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) { - int nr; - if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) - { - regs[i].regmap[hr]=MGEN1+((i+1)&1); - regmap_pre[i+1][hr]=MGEN1+((i+1)&1); - regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1); - regs[i].isconst&=~(1<=0) - { - // move it to another register - regs[i+1].regmap[hr]=-1; - regmap_pre[i+2][hr]=-1; - regs[i+1].regmap[nr]=TLREG; - regmap_pre[i+2][nr]=TLREG; - regs[i].regmap[nr]=MGEN1+((i+1)&1); - regmap_pre[i+1][nr]=MGEN1+((i+1)&1); - regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1); - regs[i].isconst&=~(1<=0;i--) - { - int hr; - if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) - { - if(ba[i]=(start+slen*4)) - { - // Branch out of this block, don't need anything - r32=0; - } - else - { - // Internal branch - // Need whatever matches the target - // (and doesn't get overwritten by the delay slot instruction) - r32=0; - int t=(ba[i]-start)>>2; - if(ba[i]>start+i*4) { - // Forward branch - if(!(requires_32bit[t]&~regs[i].was32)) - r32|=requires_32bit[t]&(~(1LL<>16)!=0x1000) - { - if(i0) - { - if((regs[i].was32>>us1[i+1])&1) r32|=1LL<0) - { - if((regs[i].was32>>us2[i+1])&1) r32|=1LL<>dep1[i+1])&1)) - { - if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<>dep2[i+1])&1)) - { - if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<0) - { - if((regs[i].was32>>us1[i])&1) r32|=1LL<0) - { - if((regs[i].was32>>us2[i])&1) r32|=1LL<>dep1[i])&1)) - { - if((regs[i].was32>>dep1[i])&1) r32|=1LL<>dep2[i])&1)) - { - if((regs[i].was32>>dep2[i])&1) r32|=1LL<0&®s[i].regmap_entry[hr]<64) { - if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) { - if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1)) - requires_32bit[i]|=1LL<=0;i--) { - if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) + if(itype[i]==CJUMP||itype[i]==SJUMP) { // Conditional branch if((source[i]>>16)!=0x1000&&i>r)&1) { - if(r==HIREG) printf(" HI"); - else if(r==LOREG) printf(" LO"); - else printf(" r%d",r); - } - } - printf(" 32:"); - for(r=0;r<=CCREG;r++) { - //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) { - if((regs[i].was32>>r)&1) { - if(r==CCREG) printf(" CC"); - else if(r==HIREG) printf(" HI"); - else if(r==LOREG) printf(" LO"); - else printf(" r%d",r); - } - } -#endif printf("\n"); #if defined(__i386__) || defined(__x86_64__) printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]); @@ -11016,6 +8558,7 @@ int new_recompile_block(int addr) #ifdef __arm__ printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]); #endif + #if defined(__i386__) || defined(__x86_64__) printf("needs: "); if(needed_reg[i]&1) printf("eax "); if((needed_reg[i]>>1)&1) printf("ecx "); @@ -11024,30 +8567,7 @@ int new_recompile_block(int addr) if((needed_reg[i]>>5)&1) printf("ebp "); if((needed_reg[i]>>6)&1) printf("esi "); if((needed_reg[i]>>7)&1) printf("edi "); - printf("r:"); - for(r=0;r<=CCREG;r++) { - //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) { - if((requires_32bit[i]>>r)&1) { - if(r==CCREG) printf(" CC"); - else if(r==HIREG) printf(" HI"); - else if(r==LOREG) printf(" LO"); - else printf(" r%d",r); - } - } printf("\n"); - /*printf("pr:"); - for(r=0;r<=CCREG;r++) { - //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) { - if((pr32[i]>>r)&1) { - if(r==CCREG) printf(" CC"); - else if(r==HIREG) printf(" HI"); - else if(r==LOREG) printf(" LO"); - else printf(" r%d",r); - } - } - if(pr32[i]!=requires_32bit[i]) printf(" OOPS"); - printf("\n");*/ - #if defined(__i386__) || defined(__x86_64__) printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]); printf("dirty: "); if(regs[i].wasdirty&1) printf("eax "); @@ -11106,54 +8626,23 @@ int new_recompile_block(int addr) if(regs[i].isconst) { printf("constants: "); #if defined(__i386__) || defined(__x86_64__) - if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]); - if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]); - if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]); - if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]); - if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]); - if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]); - if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]); + if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]); + if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]); + if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]); + if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]); + if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]); + if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]); + if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]); #endif - #ifdef __arm__ - if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]); - if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]); - if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]); - if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]); - if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]); - if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]); - if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]); - if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]); - if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]); - if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]); - if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]); - if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]); + #if defined(__arm__) || defined(__aarch64__) + int r; + for (r = 0; r < ARRAY_SIZE(constmap[i]); r++) + if ((regs[i].isconst >> r) & 1) + printf(" r%d=%x", r, (u_int)constmap[i][r]); #endif printf("\n"); } -#ifndef FORCE32 - printf(" 32:"); - for(r=0;r<=CCREG;r++) { - if((regs[i].is32>>r)&1) { - if(r==CCREG) printf(" CC"); - else if(r==HIREG) printf(" HI"); - else if(r==LOREG) printf(" LO"); - else printf(" r%d",r); - } - } - printf("\n"); -#endif - /*printf(" p32:"); - for(r=0;r<=CCREG;r++) { - if((p32[i]>>r)&1) { - if(r==CCREG) printf(" CC"); - else if(r==HIREG) printf(" HI"); - else if(r==LOREG) printf(" LO"); - else printf(" r%d",r); - } - } - if(p32[i]!=regs[i].is32) printf(" NO MATCH\n"); - else printf("\n");*/ - if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) { + if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP) { #if defined(__i386__) || defined(__x86_64__) printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); if(branch_regs[i].dirty&1) printf("eax "); @@ -11179,18 +8668,6 @@ int new_recompile_block(int addr) if((branch_regs[i].dirty>>10)&1) printf("r10 "); if((branch_regs[i].dirty>>12)&1) printf("r12 "); #endif -#ifndef FORCE32 - printf(" 32:"); - for(r=0;r<=CCREG;r++) { - if((branch_regs[i].is32>>r)&1) { - if(r==CCREG) printf(" CC"); - else if(r==HIREG) printf(" HI"); - else if(r==LOREG) printf(" LO"); - else printf(" r%d",r); - } - } - printf("\n"); -#endif } } #endif // DISASM @@ -11198,31 +8675,32 @@ int new_recompile_block(int addr) /* Pass 8 - Assembly */ linkcount=0;stubcount=0; ds=0;is_delayslot=0; - cop1_usable=0; - uint64_t is32_pre=0; u_int dirty_pre=0; - u_int beginning=(u_int)out; + void *beginning=start_block(); if((u_int)addr&1) { ds=1; pagespan_ds(); } - u_int instr_addr0_override=0; + void *instr_addr0_override = NULL; -#ifdef PCSX if (start == 0x80030000) { - // nasty hack for fastbios thing + // nasty hack for the fastbios thing // override block entry to this code - instr_addr0_override=(u_int)out; + instr_addr0_override = out; emit_movimm(start,0); // abuse io address var as a flag that we // have already returned here once - emit_readword((int)&address,1); - emit_writeword(0,(int)&pcaddr); - emit_writeword(0,(int)&address); + emit_readword(&address,1); + emit_writeword(0,&pcaddr); + emit_writeword(0,&address); emit_cmp(0,1); - emit_jne((int)new_dyna_leave); + #ifdef __aarch64__ + emit_jeq(out + 4*2); + emit_jmp(new_dyna_leave); + #else + emit_jne(new_dyna_leave); + #endif } -#endif for(i=0;i>16)!=0x1000)) { - wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32, - unneeded_reg[i],unneeded_reg_upper[i]); - wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre, - unneeded_reg[i],unneeded_reg_upper[i]); + wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]); } - if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) { - is32_pre=branch_regs[i].is32; + if((itype[i]==CJUMP||itype[i]==SJUMP)&&!likely[i]) { dirty_pre=branch_regs[i].dirty; }else{ - is32_pre=regs[i].is32; dirty_pre=regs[i].dirty; } #endif // write back if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000)) { - wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32, - unneeded_reg[i],unneeded_reg_upper[i]); + wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]); loop_preload(regmap_pre[i],regs[i].regmap_entry); } // branch target entry point - instr_addr[i]=(u_int)out; + instr_addr[i] = out; assem_debug("<->\n"); + drc_dbg_emit_do_cmp(i); + // load regs if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG) - wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32); - load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]); + wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty); + load_regs(regs[i].regmap_entry,regs[i].regmap,rs1[i],rs2[i]); address_generation(i,®s[i],regs[i].regmap_entry); - load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i); - if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) + load_consts(regmap_pre[i],regs[i].regmap,i); + if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP) { // Load the delay slot registers if necessary if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0)) - load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]); + load_regs(regs[i].regmap_entry,regs[i].regmap,rs1[i+1],rs1[i+1]); if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0)) - load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]); + load_regs(regs[i].regmap_entry,regs[i].regmap,rs2[i+1],rs2[i+1]); if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) - load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP); + load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP); } else if(i+11) { if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) { - assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP); + assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP); assert(i==slen); - if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) { - store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4); + if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP) { + store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4); if(regs[i-1].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG); } else if(!likely[i-2]) { - store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4); + store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4); assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG); } else { - store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4); + store_regs_bt(regs[i-2].regmap,regs[i-2].dirty,start+i*4); assert(regs[i-2].regmap[HOST_CCREG]==CCREG); } - add_to_linker((int)out,start+i*4,0); + add_to_linker(out,start+i*4,0); emit_jmp(0); } } else { assert(i>0); - assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP); - store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4); + assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP); + store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4); if(regs[i-1].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG); - add_to_linker((int)out,start+i*4,0); + add_to_linker(out,start+i*4,0); emit_jmp(0); } @@ -11399,7 +8864,7 @@ int new_recompile_block(int addr) // Stubs for(i=0;i %8x\n",link_addr[i][0],link_addr[i][1]); + assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target); literal_pool(64); - if(!link_addr[i][2]) + if (!link_addr[i].ext) { - void *stub=out; - void *addr=check_addr(link_addr[i][1]); - emit_extjump(link_addr[i][0],link_addr[i][1]); - if(addr) { - set_jump_target(link_addr[i][0],(int)addr); - add_link(link_addr[i][1],stub); + void *stub = out; + void *addr = check_addr(link_addr[i].target); + emit_extjump(link_addr[i].addr, link_addr[i].target); + if (addr) { + set_jump_target(link_addr[i].addr, addr); + add_link(link_addr[i].target,stub); } - else set_jump_target(link_addr[i][0],(int)stub); + else + set_jump_target(link_addr[i].addr, stub); } else { // Internal branch - int target=(link_addr[i][1]-start)>>2; + int target=(link_addr[i].target-start)>>2; assert(target>=0&&target>1); + //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1); //#else - set_jump_target(link_addr[i][0],instr_addr[target]); + set_jump_target(link_addr[i].addr, instr_addr[target]); //#endif } } @@ -11468,46 +8934,21 @@ int new_recompile_block(int addr) u_int page=get_page(vaddr); u_int vpage=get_vpage(vaddr); literal_pool(256); - //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<>16)^vaddr)&0xFFFF]; - if(ht_bin[0]==vaddr) { - ht_bin[1]=entry_point; - } - if(ht_bin[2]==vaddr) { - ht_bin[3]=entry_point; - } - } - else - { - u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32); - assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4); - assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r); - //int entry_point=(int)out; - ////assem_debug("entry_point: %x\n",entry_point); - //load_regs_entry(i); - //if(entry_point==(int)out) - // entry_point=instr_addr[i]; - //else - // emit_jmp(instr_addr[i]); - //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point); - ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out); - int entry_point=do_dirty_stub(i); - ll_add_32(jump_in+page,vaddr,r,(void *)entry_point); + struct ht_entry *ht_bin = hash_table_get(vaddr); + if (ht_bin->vaddr[0] == vaddr) + ht_bin->tcaddr[0] = entry_point; + if (ht_bin->vaddr[1] == vaddr) + ht_bin->tcaddr[1] = entry_point; } } } @@ -11518,50 +8959,38 @@ int new_recompile_block(int addr) // Align code if(((u_int)out)&7) emit_addnop(13); #endif - assert((u_int)out-beginningBASE_ADDR+(1< translation_cache+(1<>12;i<=(start+slen*4)>>12;i++) { invalid_code[i]=0; -#ifndef DISABLE_TLB - memory_map[i]|=0x40000000; - if((signed int)start>=(signed int)0xC0000000) { - assert(using_tlb); - j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12; - invalid_code[j]=0; - memory_map[j]|=0x40000000; - //printf("write protect physical page: %x (virtual %x)\n",j<<12,start); - } -#endif } inv_code_start=inv_code_end=~0; -#ifdef PCSX + // for PCSX we need to mark all mirrors too if(get_page(start)<(RAM_SIZE>>12)) for(i=start>>12;i<=(start+slen*4)>>12;i++) invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]= invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]= invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0; -#endif - + /* Pass 10 - Free memory by expiring oldest blocks */ - - int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535; + + int end=(((out-translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535; while(expirep!=end) { int shift=TARGET_SIZE_2-3; // Divide into 8 blocks - int base=BASE_ADDR+((expirep>>13)<>13)<>11)&3) { @@ -11580,25 +9009,27 @@ int new_recompile_block(int addr) case 2: // Clear hash table for(i=0;i<32;i++) { - int *ht_bin=hash_table[((expirep&2047)<<5)+i]; - if((ht_bin[3]>>shift)==(base>>shift) || - ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) { - inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]); - ht_bin[2]=ht_bin[3]=-1; - } - if((ht_bin[1]>>shift)==(base>>shift) || - ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) { - inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]); - ht_bin[0]=ht_bin[2]; - ht_bin[1]=ht_bin[3]; - ht_bin[2]=ht_bin[3]=-1; + struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i]; + if (((uintptr_t)ht_bin->tcaddr[1]>>shift) == (base>>shift) || + (((uintptr_t)ht_bin->tcaddr[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) { + inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]); + ht_bin->vaddr[1] = -1; + ht_bin->tcaddr[1] = NULL; + } + if (((uintptr_t)ht_bin->tcaddr[0]>>shift) == (base>>shift) || + (((uintptr_t)ht_bin->tcaddr[0]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) { + inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]); + ht_bin->vaddr[0] = ht_bin->vaddr[1]; + ht_bin->tcaddr[0] = ht_bin->tcaddr[1]; + ht_bin->vaddr[1] = -1; + ht_bin->tcaddr[1] = NULL; } } break; case 3: // Clear jump_out - #ifdef __arm__ - if((expirep&2047)==0) + #if defined(__arm__) || defined(__aarch64__) + if((expirep&2047)==0) do_clear_cache(); #endif ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);