X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fnew_dynarec.c;h=ca12ea98a36dded9b17b0eeed14d3ad89fe0adf4;hp=8d1e53ac064468dc7fc8799c4ffe0262049d7ef8;hb=581335b095ed820978d4c88f026abf462128eeb0;hpb=03f55e6b49eb81d099f33b67ee6b5fa4620a54bc

diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c
index 8d1e53ac..ca12ea98 100644
--- a/libpcsxcore/new_dynarec/new_dynarec.c
+++ b/libpcsxcore/new_dynarec/new_dynarec.c
@@ -83,22 +83,29 @@ struct ll_entry
   struct ll_entry *next;
 };
 
-  u_int start;
-  u_int *source;
-  char insn[MAXBLOCK][10];
-  u_char itype[MAXBLOCK];
-  u_char opcode[MAXBLOCK];
-  u_char opcode2[MAXBLOCK];
-  u_char bt[MAXBLOCK];
-  u_char rs1[MAXBLOCK];
-  u_char rs2[MAXBLOCK];
-  u_char rt1[MAXBLOCK];
-  u_char rt2[MAXBLOCK];
-  u_char us1[MAXBLOCK];
-  u_char us2[MAXBLOCK];
-  u_char dep1[MAXBLOCK];
-  u_char dep2[MAXBLOCK];
-  u_char lt1[MAXBLOCK];
+  // used by asm:
+  u_char *out;
+  u_int hash_table[65536][4]  __attribute__((aligned(16)));
+  struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
+  struct ll_entry *jump_dirty[4096];
+
+  static struct ll_entry *jump_out[4096];
+  static u_int start;
+  static u_int *source;
+  static char insn[MAXBLOCK][10];
+  static u_char itype[MAXBLOCK];
+  static u_char opcode[MAXBLOCK];
+  static u_char opcode2[MAXBLOCK];
+  static u_char bt[MAXBLOCK];
+  static u_char rs1[MAXBLOCK];
+  static u_char rs2[MAXBLOCK];
+  static u_char rt1[MAXBLOCK];
+  static u_char rt2[MAXBLOCK];
+  static u_char us1[MAXBLOCK];
+  static u_char us2[MAXBLOCK];
+  static u_char dep1[MAXBLOCK];
+  static u_char dep2[MAXBLOCK];
+  static u_char lt1[MAXBLOCK];
   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
   static uint64_t gte_rt[MAXBLOCK];
   static uint64_t gte_unneeded[MAXBLOCK];
@@ -107,59 +114,47 @@ struct ll_entry
   static u_int smrv_weak; // same, but somewhat less likely
   static u_int smrv_strong_next; // same, but after current insn executes
   static u_int smrv_weak_next;
-  int imm[MAXBLOCK];
-  u_int ba[MAXBLOCK];
-  char likely[MAXBLOCK];
-  char is_ds[MAXBLOCK];
-  char ooo[MAXBLOCK];
-  uint64_t unneeded_reg[MAXBLOCK];
-  uint64_t unneeded_reg_upper[MAXBLOCK];
-  uint64_t branch_unneeded_reg[MAXBLOCK];
-  uint64_t branch_unneeded_reg_upper[MAXBLOCK];
-  uint64_t p32[MAXBLOCK];
-  uint64_t pr32[MAXBLOCK];
-  signed char regmap_pre[MAXBLOCK][HOST_REGS];
+  static int imm[MAXBLOCK];
+  static u_int ba[MAXBLOCK];
+  static char likely[MAXBLOCK];
+  static char is_ds[MAXBLOCK];
+  static char ooo[MAXBLOCK];
+  static uint64_t unneeded_reg[MAXBLOCK];
+  static uint64_t unneeded_reg_upper[MAXBLOCK];
+  static uint64_t branch_unneeded_reg[MAXBLOCK];
+  static uint64_t branch_unneeded_reg_upper[MAXBLOCK];
+  static signed char regmap_pre[MAXBLOCK][HOST_REGS];
   static uint64_t current_constmap[HOST_REGS];
   static uint64_t constmap[MAXBLOCK][HOST_REGS];
   static struct regstat regs[MAXBLOCK];
   static struct regstat branch_regs[MAXBLOCK];
-  signed char minimum_free_regs[MAXBLOCK];
-  u_int needed_reg[MAXBLOCK];
-  uint64_t requires_32bit[MAXBLOCK];
-  u_int wont_dirty[MAXBLOCK];
-  u_int will_dirty[MAXBLOCK];
-  int ccadj[MAXBLOCK];
-  int slen;
-  u_int instr_addr[MAXBLOCK];
-  u_int link_addr[MAXBLOCK][3];
-  int linkcount;
-  u_int stubs[MAXBLOCK*3][8];
-  int stubcount;
-  u_int literals[1024][2];
-  int literalcount;
-  int is_delayslot;
-  int cop1_usable;
-  u_char *out;
-  struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
-  struct ll_entry *jump_out[4096];
-  struct ll_entry *jump_dirty[4096];
-  u_int hash_table[65536][4]  __attribute__((aligned(16)));
-  char shadow[1048576]  __attribute__((aligned(16)));
-  void *copy;
-  int expirep;
-#ifndef PCSX
-  u_int using_tlb;
-#else
-  static const u_int using_tlb=0;
-#endif
-  int new_dynarec_did_compile;
-  int new_dynarec_hacks;
-  u_int stop_after_jal;
+  static signed char minimum_free_regs[MAXBLOCK];
+  static u_int needed_reg[MAXBLOCK];
+  static u_int wont_dirty[MAXBLOCK];
+  static u_int will_dirty[MAXBLOCK];
+  static int ccadj[MAXBLOCK];
+  static int slen;
+  static u_int instr_addr[MAXBLOCK];
+  static u_int link_addr[MAXBLOCK][3];
+  static int linkcount;
+  static u_int stubs[MAXBLOCK*3][8];
+  static int stubcount;
+  static u_int literals[1024][2];
+  static int literalcount;
+  static int is_delayslot;
+  static int cop1_usable;
+  static char shadow[1048576]  __attribute__((aligned(16)));
+  static void *copy;
+  static int expirep;
+  static u_int stop_after_jal;
 #ifndef RAM_FIXED
   static u_int ram_offset;
 #else
   static const u_int ram_offset=0;
 #endif
+
+  int new_dynarec_hacks;
+  int new_dynarec_did_compile;
   extern u_char restore_candidate[512];
   extern int cycle_count;
 
@@ -171,20 +166,20 @@ struct ll_entry
 #define CSREG 35 // Coprocessor status
 #define CCREG 36 // Cycle count
 #define INVCP 37 // Pointer to invalid_code
-#define MMREG 38 // Pointer to memory_map
+//#define MMREG 38 // Pointer to memory_map
 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 #define TEMPREG 40
 #define FTEMP 40 // FPU temporary register
 #define PTEMP 41 // Prefetch temporary register
-#define TLREG 42 // TLB mapping offset
+//#define TLREG 42 // TLB mapping offset
 #define RHASH 43 // Return address hash
 #define RHTBL 44 // Return address hash table address
 #define RTEMP 45 // JR/JALR address register
 #define MAXREG 45
 #define AGEN1 46 // Address generation temporary register
-#define AGEN2 47 // Address generation temporary register
-#define MGEN1 48 // Maptable address generation temporary register
-#define MGEN2 49 // Maptable address generation temporary register
+//#define AGEN2 47 // Address generation temporary register
+//#define MGEN1 48 // Maptable address generation temporary register
+//#define MGEN2 49 // Maptable address generation temporary register
 #define BTREG 50 // Branch target temporary register
 
   /* instruction types */
@@ -193,7 +188,7 @@ struct ll_entry
 #define STORE 2   // Store
 #define LOADLR 3  // Unaligned load
 #define STORELR 4 // Unaligned store
-#define MOV 5     // Move 
+#define MOV 5     // Move
 #define ALU 6     // Arithmetic/logic
 #define MULTDIV 7 // Multiply/divide
 #define SHIFT 8   // Shift by register
@@ -247,7 +242,6 @@ void *get_addr_ht(u_int vaddr);
 void invalidate_block(u_int block);
 void invalidate_addr(u_int addr);
 void remove_hash(int vaddr);
-void jump_vaddr();
 void dyna_linker();
 void dyna_linker_ds();
 void verify_code();
@@ -256,40 +250,26 @@ void verify_code_ds();
 void cc_interrupt();
 void fp_exception();
 void fp_exception_ds();
-void jump_syscall();
 void jump_syscall_hle();
-void jump_eret();
 void jump_hlecall();
 void jump_intcall();
 void new_dyna_leave();
 
-// TLB
-void TLBWI_new();
-void TLBWR_new();
-void read_nomem_new();
-void read_nomemb_new();
-void read_nomemh_new();
-void read_nomemd_new();
-void write_nomem_new();
-void write_nomemb_new();
-void write_nomemh_new();
-void write_nomemd_new();
-void write_rdram_new();
-void write_rdramb_new();
-void write_rdramh_new();
-void write_rdramd_new();
-extern u_int memory_map[1048576];
-
 // Needed by assembler
-void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
-void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
-void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
-void load_all_regs(signed char i_regmap[]);
-void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
-void load_regs_entry(int t);
-void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
+static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
+static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
+static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
+static void load_all_regs(signed char i_regmap[]);
+static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
+static void load_regs_entry(int t);
+static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 
-int tracedebug=0;
+static int verify_dirty(u_int *ptr);
+static int get_final_value(int hr, int i, int *value);
+static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e);
+static void add_to_linker(int addr,int target,int ext);
+
+static int tracedebug=0;
 
 //#define DEBUG_CYCLE_COUNT 1
 
@@ -303,87 +283,21 @@ static int CLOCK_ADJUST(int x)
   return (x * cycle_multiplier + s * 50) / 100;
 }
 
-static void tlb_hacks()
-{
-#ifndef DISABLE_TLB
-  // Goldeneye hack
-  if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
-  {
-    u_int addr;
-    int n;
-    switch (ROM_HEADER->Country_code&0xFF) 
-    {
-      case 0x45: // U
-        addr=0x34b30;
-        break;                   
-      case 0x4A: // J 
-        addr=0x34b70;    
-        break;    
-      case 0x50: // E 
-        addr=0x329f0;
-        break;                        
-      default: 
-        // Unknown country code
-        addr=0;
-        break;
-    }
-    u_int rom_addr=(u_int)rom;
-    #ifdef ROM_COPY
-    // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
-    // in the lower 4G of memory to use this hack.  Copy it if necessary.
-    if((void *)rom>(void *)0xffffffff) {
-      munmap(ROM_COPY, 67108864);
-      if(mmap(ROM_COPY, 12582912,
-              PROT_READ | PROT_WRITE,
-              MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
-              -1, 0) <= 0) {printf("mmap() failed\n");}
-      memcpy(ROM_COPY,rom,12582912);
-      rom_addr=(u_int)ROM_COPY;
-    }
-    #endif
-    if(addr) {
-      for(n=0x7F000;n<0x80000;n++) {
-        memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
-      }
-    }
-  }
-#endif
-}
-
 static u_int get_page(u_int vaddr)
 {
-#ifndef PCSX
-  u_int page=(vaddr^0x80000000)>>12;
-#else
   u_int page=vaddr&~0xe0000000;
   if (page < 0x1000000)
     page &= ~0x0e00000; // RAM mirrors
   page>>=12;
-#endif
-#ifndef DISABLE_TLB
-  if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
-#endif
   if(page>2048) page=2048+(page&2047);
   return page;
 }
 
-#ifndef PCSX
-static u_int get_vpage(u_int vaddr)
-{
-  u_int vpage=(vaddr^0x80000000)>>12;
-#ifndef DISABLE_TLB
-  if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
-#endif
-  if(vpage>2048) vpage=2048+(vpage&2047);
-  return vpage;
-}
-#else
 // no virtual mem in PCSX
 static u_int get_vpage(u_int vaddr)
 {
   return get_page(vaddr);
 }
-#endif
 
 // Get address from virtual address
 // This is called from the recompiled JR/JALR instructions
@@ -397,10 +311,10 @@ void *get_addr(u_int vaddr)
   while(head!=NULL) {
     if(head->vaddr==vaddr) {
   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
-      int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
+      u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
       ht_bin[3]=ht_bin[1];
       ht_bin[2]=ht_bin[0];
-      ht_bin[1]=(int)head->addr;
+      ht_bin[1]=(u_int)head->addr;
       ht_bin[0]=vaddr;
       return head->addr;
     }
@@ -416,22 +330,13 @@ void *get_addr(u_int vaddr)
         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
         invalid_code[vaddr>>12]=0;
         inv_code_start=inv_code_end=~0;
-#ifndef DISABLE_TLB
-        memory_map[vaddr>>12]|=0x40000000;
-#endif
         if(vpage<2048) {
-#ifndef DISABLE_TLB
-          if(tlb_LUT_r[vaddr>>12]) {
-            invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
-            memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
-          }
-#endif
           restore_candidate[vpage>>3]|=1<<(vpage&7);
         }
         else restore_candidate[page>>3]|=1<<(page&7);
-        int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
+        u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
         if(ht_bin[0]==vaddr) {
-          ht_bin[1]=(int)head->addr; // Replace existing entry
+          ht_bin[1]=(u_int)head->addr; // Replace existing entry
         }
         else
         {
@@ -461,7 +366,7 @@ void *get_addr(u_int vaddr)
 void *get_addr_ht(u_int vaddr)
 {
   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
-  int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
+  u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
   return get_addr(vaddr);
@@ -523,7 +428,7 @@ static void flush_dirty_uppers(struct regstat *cur)
   for (hr=0;hr<HOST_REGS;hr++) {
     if((cur->dirty>>hr)&1) {
       reg=cur->regmap[hr];
-      if(reg>=64) 
+      if(reg>=64)
         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
     }
   }
@@ -662,10 +567,6 @@ void lsn(u_char hsn[], int i, int *preferred_reg)
   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
     hsn[FTEMP]=0;
   }
-  // Don't remove the TLB registers either
-  if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
-    hsn[TLREG]=0;
-  }
   // Don't remove the miniht registers
   if(itype[i]==UJUMP||itype[i]==RJUMP)
   {
@@ -680,7 +581,7 @@ int needed_again(int r, int i)
   int j;
   int b=-1;
   int rn=10;
-  
+
   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
   {
     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
@@ -733,6 +634,7 @@ int needed_again(int r, int i)
     }
   }*/
   if(rn<10) return 1;
+  (void)b;
   return 0;
 }
 
@@ -783,7 +685,7 @@ int loop_reg(int i, int r, int hr)
 void alloc_all(struct regstat *cur,int i)
 {
   int hr;
-  
+
   for(hr=0;hr<HOST_REGS;hr++) {
     if(hr!=EXCLUDE_REG) {
       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
@@ -802,119 +704,6 @@ void alloc_all(struct regstat *cur,int i)
   }
 }
 
-#ifndef FORCE32
-void div64(int64_t dividend,int64_t divisor)
-{
-  lo=dividend/divisor;
-  hi=dividend%divisor;
-  //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
-  //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
-}
-void divu64(uint64_t dividend,uint64_t divisor)
-{
-  lo=dividend/divisor;
-  hi=dividend%divisor;
-  //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
-  //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
-}
-
-void mult64(uint64_t m1,uint64_t m2)
-{
-   unsigned long long int op1, op2, op3, op4;
-   unsigned long long int result1, result2, result3, result4;
-   unsigned long long int temp1, temp2, temp3, temp4;
-   int sign = 0;
-   
-   if (m1 < 0)
-     {
-    op2 = -m1;
-    sign = 1 - sign;
-     }
-   else op2 = m1;
-   if (m2 < 0)
-     {
-    op4 = -m2;
-    sign = 1 - sign;
-     }
-   else op4 = m2;
-   
-   op1 = op2 & 0xFFFFFFFF;
-   op2 = (op2 >> 32) & 0xFFFFFFFF;
-   op3 = op4 & 0xFFFFFFFF;
-   op4 = (op4 >> 32) & 0xFFFFFFFF;
-   
-   temp1 = op1 * op3;
-   temp2 = (temp1 >> 32) + op1 * op4;
-   temp3 = op2 * op3;
-   temp4 = (temp3 >> 32) + op2 * op4;
-   
-   result1 = temp1 & 0xFFFFFFFF;
-   result2 = temp2 + (temp3 & 0xFFFFFFFF);
-   result3 = (result2 >> 32) + temp4;
-   result4 = (result3 >> 32);
-   
-   lo = result1 | (result2 << 32);
-   hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
-   if (sign)
-     {
-    hi = ~hi;
-    if (!lo) hi++;
-    else lo = ~lo + 1;
-     }
-}
-
-void multu64(uint64_t m1,uint64_t m2)
-{
-   unsigned long long int op1, op2, op3, op4;
-   unsigned long long int result1, result2, result3, result4;
-   unsigned long long int temp1, temp2, temp3, temp4;
-   
-   op1 = m1 & 0xFFFFFFFF;
-   op2 = (m1 >> 32) & 0xFFFFFFFF;
-   op3 = m2 & 0xFFFFFFFF;
-   op4 = (m2 >> 32) & 0xFFFFFFFF;
-   
-   temp1 = op1 * op3;
-   temp2 = (temp1 >> 32) + op1 * op4;
-   temp3 = op2 * op3;
-   temp4 = (temp3 >> 32) + op2 * op4;
-   
-   result1 = temp1 & 0xFFFFFFFF;
-   result2 = temp2 + (temp3 & 0xFFFFFFFF);
-   result3 = (result2 >> 32) + temp4;
-   result4 = (result3 >> 32);
-   
-   lo = result1 | (result2 << 32);
-   hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
-   
-  //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
-  //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
-}
-
-uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
-{
-  if(bits) {
-    original<<=64-bits;
-    original>>=64-bits;
-    loaded<<=bits;
-    original|=loaded;
-  }
-  else original=loaded;
-  return original;
-}
-uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
-{
-  if(bits^56) {
-    original>>=64-(bits^56);
-    original<<=64-(bits^56);
-    loaded>>=bits^56;
-    original|=loaded;
-  }
-  else original=loaded;
-  return original;
-}
-#endif
-
 #ifdef __i386__
 #include "assem_x86.c"
 #endif
@@ -993,7 +782,7 @@ void *check_addr(u_int vaddr)
 void remove_hash(int vaddr)
 {
   //printf("remove hash: %x\n",vaddr);
-  int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
+  u_int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
   if(ht_bin[2]==vaddr) {
     ht_bin[2]=ht_bin[3]=-1;
   }
@@ -1008,7 +797,7 @@ void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
 {
   struct ll_entry *next;
   while(*head) {
-    if(((u_int)((*head)->addr)>>shift)==(addr>>shift) || 
+    if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
     {
       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
@@ -1029,7 +818,7 @@ void ll_clear(struct ll_entry **head)
 {
   struct ll_entry *cur;
   struct ll_entry *next;
-  if(cur=*head) {
+  if((cur=*head)) {
     *head=0;
     while(cur) {
       next=cur->next;
@@ -1104,21 +893,9 @@ static void invalidate_block_range(u_int block, u_int first, u_int last)
   #ifdef __arm__
     do_clear_cache();
   #endif
-  
+
   // Don't trap writes
   invalid_code[block]=1;
-#ifndef DISABLE_TLB
-  // If there is a valid TLB entry for this page, remove write protect
-  if(tlb_LUT_w[block]) {
-    assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
-    // CHECK: Is this right?
-    memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
-    u_int real_block=tlb_LUT_w[block]>>12;
-    invalid_code[real_block]=1;
-    if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
-  }
-  else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
-#endif
 
   #ifdef USE_MINI_HT
   memset(mini_ht,-1,sizeof(mini_ht));
@@ -1147,14 +924,6 @@ void invalidate_block(u_int block)
           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
         }
       }
-#ifndef DISABLE_TLB
-      if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
-        if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
-          if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
-          if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
-        }
-      }
-#endif
     }
     head=head->next;
   }
@@ -1163,7 +932,6 @@ void invalidate_block(u_int block)
 
 void invalidate_addr(u_int addr)
 {
-#ifdef PCSX
   //static int rhits;
   // this check is done by the caller
   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
@@ -1217,7 +985,6 @@ void invalidate_addr(u_int addr)
       return;
     }
   }
-#endif
   invalidate_block(addr>>12);
 }
 
@@ -1225,7 +992,7 @@ void invalidate_addr(u_int addr)
 // Anything could have changed, so invalidate everything.
 void invalidate_all_pages()
 {
-  u_int page,n;
+  u_int page;
   for(page=0;page<4096;page++)
     invalidate_page(page);
   for(page=0;page<1048576;page++)
@@ -1239,19 +1006,6 @@ void invalidate_all_pages()
   #ifdef USE_MINI_HT
   memset(mini_ht,-1,sizeof(mini_ht));
   #endif
-  #ifndef DISABLE_TLB
-  // TLB
-  for(page=0;page<0x100000;page++) {
-    if(tlb_LUT_r[page]) {
-      memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
-      if(!tlb_LUT_w[page]||!invalid_code[page])
-        memory_map[page]|=0x40000000; // Write protect
-    }
-    else memory_map[page]=-1;
-    if(page==0x80000) page=0xC0000;
-  }
-  tlb_hacks();
-  #endif
 }
 
 // Add an entry to jump_out after making a link
@@ -1261,6 +1015,7 @@ void add_link(u_int vaddr,void *src)
   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
   int *ptr=(int *)(src+4);
   assert((*ptr&0x0fff0000)==0x059f0000);
+  (void)ptr;
   ll_add(jump_out+page,vaddr,src);
   //int ptr=get_pointer(src);
   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
@@ -1280,7 +1035,7 @@ void clean_blocks(u_int page)
       // Don't restore blocks which are about to expire from the cache
       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
         u_int start,end;
-        if(verify_dirty((int)head->addr)) {
+        if(verify_dirty(head->addr)) {
           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
           u_int i;
           u_int inv=0;
@@ -1290,13 +1045,6 @@ void clean_blocks(u_int page)
               inv|=invalid_code[i];
             }
           }
-#ifndef DISABLE_TLB
-          if((signed int)head->vaddr>=(signed int)0xC0000000) {
-            u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
-            //printf("addr=%x start=%x end=%x\n",addr,start,end);
-            if(addr<start||addr>=end) inv=1;
-          }
-#endif
           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
             inv=1;
           }
@@ -1304,19 +1052,16 @@ void clean_blocks(u_int page)
             void * clean_addr=(void *)get_clean_addr((int)head->addr);
             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
               u_int ppage=page;
-#ifndef DISABLE_TLB
-              if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
-#endif
               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
               //printf("page=%x, addr=%x\n",page,head->vaddr);
               //assert(head->vaddr>>12==(page|0x80000));
               ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
-              int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
+              u_int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
               if(ht_bin[0]==head->vaddr) {
-                ht_bin[1]=(int)clean_addr; // Replace existing entry
+                ht_bin[1]=(u_int)clean_addr; // Replace existing entry
               }
               if(ht_bin[2]==head->vaddr) {
-                ht_bin[3]=(int)clean_addr; // Replace existing entry
+                ht_bin[3]=(u_int)clean_addr; // Replace existing entry
               }
             }
           }
@@ -1643,8 +1388,6 @@ void load_alloc(struct regstat *current,int i)
     }
     else current->is32|=1LL<<rt1[i];
     dirty_reg(current,rt1[i]);
-    // If using TLB, need a register for pointer to the mapping table
-    if(using_tlb) alloc_reg(current,i,TLREG);
     // LWL/LWR need a temporary register for the old value
     if(opcode[i]==0x22||opcode[i]==0x26)
     {
@@ -1661,8 +1404,6 @@ void load_alloc(struct regstat *current,int i)
     {
       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
     }
-    // If using TLB, need a register for pointer to the mapping table
-    if(using_tlb) alloc_reg(current,i,TLREG);
     alloc_reg_temp(current,i,-1);
     minimum_free_regs[i]=1;
     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
@@ -1684,8 +1425,6 @@ void store_alloc(struct regstat *current,int i)
     alloc_reg64(current,i,rs2[i]);
     if(rs2[i]) alloc_reg(current,i,FTEMP);
   }
-  // If using TLB, need a register for pointer to the mapping table
-  if(using_tlb) alloc_reg(current,i,TLREG);
   #if defined(HOST_IMM8)
   // On CPUs without 32-bit immediates we need a pointer to invalid_code
   else alloc_reg(current,i,INVCP);
@@ -1708,8 +1447,6 @@ void c1ls_alloc(struct regstat *current,int i)
   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
     alloc_reg64(current,i,FTEMP);
   }
-  // If using TLB, need a register for pointer to the mapping table
-  if(using_tlb) alloc_reg(current,i,TLREG);
   #if defined(HOST_IMM8)
   // On CPUs without 32-bit immediates we need a pointer to invalid_code
   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
@@ -1724,11 +1461,9 @@ void c2ls_alloc(struct regstat *current,int i)
   clear_const(current,rt1[i]);
   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
   alloc_reg(current,i,FTEMP);
-  // If using TLB, need a register for pointer to the mapping table
-  if(using_tlb) alloc_reg(current,i,TLREG);
   #if defined(HOST_IMM8)
   // On CPUs without 32-bit immediates we need a pointer to invalid_code
-  else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
+  if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
     alloc_reg(current,i,INVCP);
   #endif
   // We need a temporary register for address generation
@@ -2021,7 +1756,7 @@ static void pagespan_alloc(struct regstat *current,int i)
   //else ...
 }
 
-add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
+static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
 {
   stubs[stubcount][0]=type;
   stubs[stubcount][1]=addr;
@@ -2044,12 +1779,6 @@ void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32
         if((dirty>>hr)&1) {
           if(regmap[hr]<64) {
             emit_storereg(r,hr);
-#ifndef FORCE32
-            if((is32>>regmap[hr])&1) {
-              emit_sarimm(hr,31,hr);
-              emit_storereg(r|64,hr);
-            }
-#endif
           }else{
             emit_storereg(r|64,hr);
           }
@@ -2087,12 +1816,6 @@ void rlist()
   for(i=0;i<32;i++)
     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
   printf("\n");
-#ifndef DISABLE_COP1
-  printf("TRACE: ");
-  for(i=0;i<32;i++)
-    printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
-  printf("\n");
-#endif
 }
 
 void enabletrace()
@@ -2126,11 +1849,6 @@ void memdebug(int i)
   //printf("TRACE: %x\n",(&i)[-1]);
 }
 
-void tlb_debug(u_int cause, u_int addr, u_int iaddr)
-{
-  printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
-}
-
 void alu_assemble(int i,struct regstat *i_regs)
 {
   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
@@ -2617,23 +2335,25 @@ void imm16_assemble(int i,struct regstat *i_regs)
                 emit_mov(sh,th);
               }
             }
-            if(opcode[i]==0x0d) //ORI
-            if(sl<0) {
-              emit_orimm(tl,imm[i],tl);
-            }else{
-              if(!((i_regs->wasconst>>sl)&1))
-                emit_orimm(sl,imm[i],tl);
-              else
-                emit_movimm(constmap[i][sl]|imm[i],tl);
+            if(opcode[i]==0x0d) { // ORI
+              if(sl<0) {
+                emit_orimm(tl,imm[i],tl);
+              }else{
+                if(!((i_regs->wasconst>>sl)&1))
+                  emit_orimm(sl,imm[i],tl);
+                else
+                  emit_movimm(constmap[i][sl]|imm[i],tl);
+              }
             }
-            if(opcode[i]==0x0e) //XORI
-            if(sl<0) {
-              emit_xorimm(tl,imm[i],tl);
-            }else{
-              if(!((i_regs->wasconst>>sl)&1))
-                emit_xorimm(sl,imm[i],tl);
-              else
-                emit_movimm(constmap[i][sl]^imm[i],tl);
+            if(opcode[i]==0x0e) { // XORI
+              if(sl<0) {
+                emit_xorimm(tl,imm[i],tl);
+              }else{
+                if(!((i_regs->wasconst>>sl)&1))
+                  emit_xorimm(sl,imm[i],tl);
+                else
+                  emit_movimm(constmap[i][sl]^imm[i],tl);
+              }
             }
           }
           else {
@@ -2812,14 +2532,12 @@ void load_assemble(int i,struct regstat *i_regs)
     c=(i_regs->wasconst>>s)&1;
     if (c) {
       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
-      if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
     }
   }
   //printf("load_assemble: c=%d\n",c);
   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
   // FIXME: Even if the load is a NOP, we should check for pagefaults...
-#ifdef PCSX
-  if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
+  if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
     ||rt1[i]==0) {
       // could be FIFO, must perform the read
       // ||dummy read
@@ -2827,7 +2545,6 @@ void load_assemble(int i,struct regstat *i_regs)
       tl=get_reg(i_regs->regmap,-1);
       assert(tl>=0);
   }
-#endif
   if(offset||s<0||c) addr=tl;
   else addr=s;
   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
@@ -2837,34 +2554,22 @@ void load_assemble(int i,struct regstat *i_regs)
   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
   reglist&=~(1<<tl);
   if(th>=0) reglist&=~(1<<th);
-  if(!using_tlb) {
-    if(!c) {
-      #ifdef RAM_OFFSET
-      map=get_reg(i_regs->regmap,ROREG);
-      if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
-      #endif
-//#define R29_HACK 1
-      #ifdef R29_HACK
-      // Strmnnrmn's speed hack
-      if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
-      #endif
-      {
-        jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
-      }
+  if(!c) {
+    #ifdef RAM_OFFSET
+    map=get_reg(i_regs->regmap,ROREG);
+    if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
+    #endif
+    #ifdef R29_HACK
+    // Strmnnrmn's speed hack
+    if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
+    #endif
+    {
+      jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
     }
-    else if(ram_offset&&memtarget) {
-      emit_addimm(addr,ram_offset,HOST_TEMPREG);
-      fastload_reg_override=HOST_TEMPREG;
-    }
-  }else{ // using tlb
-    int x=0;
-    if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
-    if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
-    map=get_reg(i_regs->regmap,TLREG);
-    assert(map>=0);
-    reglist&=~(1<<map);
-    map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
-    do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
+  }
+  else if(ram_offset&&memtarget) {
+    emit_addimm(addr,ram_offset,HOST_TEMPREG);
+    fastload_reg_override=HOST_TEMPREG;
   }
   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
   if (opcode[i]==0x20) { // LB
@@ -2877,7 +2582,6 @@ void load_assemble(int i,struct regstat *i_regs)
         #endif
         {
           //emit_xorimm(addr,3,tl);
-          //gen_tlb_addr_r(tl,map);
           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
           int x=0,a=tl;
 #ifdef BIG_ENDIAN_MIPS
@@ -2918,7 +2622,6 @@ void load_assemble(int i,struct regstat *i_regs)
           //emit_movswl_indexed_tlb(x,tl,map,tl);
           //else
           if(map>=0) {
-            gen_tlb_addr_r(a,map);
             emit_movswl_indexed(x,a,tl);
           }else{
             #if 1 //def RAM_OFFSET
@@ -2964,7 +2667,6 @@ void load_assemble(int i,struct regstat *i_regs)
         #endif
         {
           //emit_xorimm(addr,3,tl);
-          //gen_tlb_addr_r(tl,map);
           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
           int x=0,a=tl;
 #ifdef BIG_ENDIAN_MIPS
@@ -3005,7 +2707,6 @@ void load_assemble(int i,struct regstat *i_regs)
           //emit_movzwl_indexed_tlb(x,tl,map,tl);
           //#else
           if(map>=0) {
-            gen_tlb_addr_r(a,map);
             emit_movzwl_indexed(x,a,tl);
           }else{
             #if 1 //def RAM_OFFSET
@@ -3049,7 +2750,6 @@ void load_assemble(int i,struct regstat *i_regs)
       if(!dummy) {
         int a=addr;
         if(fastload_reg_override) a=fastload_reg_override;
-        //gen_tlb_addr_r(tl,map);
         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
         #ifdef HOST_IMM_ADDR32
@@ -3094,7 +2794,7 @@ void load_assemble(int i,struct regstat *i_regs)
     emit_call((int)memdebug);
     //emit_popa();
     restore_regs(0x100f);
-  }/**/
+  }*/
 }
 
 #ifndef loadlr_assemble
@@ -3110,7 +2810,7 @@ void store_assemble(int i,struct regstat *i_regs)
   int s,th,tl,map=-1;
   int addr,temp;
   int offset;
-  int jaddr=0,jaddr2,type;
+  int jaddr=0,type;
   int memtarget=0,c=0;
   int agr=AGEN1+(i&1);
   int faststore_reg_override=0;
@@ -3125,7 +2825,6 @@ void store_assemble(int i,struct regstat *i_regs)
     c=(i_regs->wasconst>>s)&1;
     if(c) {
       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
-      if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
     }
   }
   assert(tl>=0);
@@ -3136,48 +2835,12 @@ void store_assemble(int i,struct regstat *i_regs)
   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
   if(offset||s<0||c) addr=temp;
   else addr=s;
-  if(!using_tlb) {
-    if(!c) {
-      #ifndef PCSX
-      #ifdef R29_HACK
-      // Strmnnrmn's speed hack
-      if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
-      #endif
-      emit_cmpimm(addr,RAM_SIZE);
-      #ifdef DESTRUCTIVE_SHIFT
-      if(s==addr) emit_mov(s,temp);
-      #endif
-      #ifdef R29_HACK
-      memtarget=1;
-      if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
-      #endif
-      {
-        jaddr=(int)out;
-        #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
-        // Hint to branch predictor that the branch is unlikely to be taken
-        if(rs1[i]>=28)
-          emit_jno_unlikely(0);
-        else
-        #endif
-        emit_jno(0);
-      }
-      #else
-        jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
-      #endif
-    }
-    else if(ram_offset&&memtarget) {
-      emit_addimm(addr,ram_offset,HOST_TEMPREG);
-      faststore_reg_override=HOST_TEMPREG;
-    }
-  }else{ // using tlb
-    int x=0;
-    if (opcode[i]==0x28) x=3; // SB
-    if (opcode[i]==0x29) x=2; // SH
-    map=get_reg(i_regs->regmap,TLREG);
-    assert(map>=0);
-    reglist&=~(1<<map);
-    map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
-    do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
+  if(!c) {
+    jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
+  }
+  else if(ram_offset&&memtarget) {
+    emit_addimm(addr,ram_offset,HOST_TEMPREG);
+    faststore_reg_override=HOST_TEMPREG;
   }
 
   if (opcode[i]==0x28) { // SB
@@ -3190,7 +2853,6 @@ void store_assemble(int i,struct regstat *i_regs)
       if(!c) a=addr;
 #endif
       if(faststore_reg_override) a=faststore_reg_override;
-      //gen_tlb_addr_w(temp,map);
       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
       emit_writebyte_indexed_tlb(tl,x,a,map,a);
     }
@@ -3210,7 +2872,6 @@ void store_assemble(int i,struct regstat *i_regs)
       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
       //#else
       if(map>=0) {
-        gen_tlb_addr_w(a,map);
         emit_writehword_indexed(tl,x,a);
       }else
         //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
@@ -3245,15 +2906,13 @@ void store_assemble(int i,struct regstat *i_regs)
     }
     type=STORED_STUB;
   }
-#ifdef PCSX
   if(jaddr) {
     // PCSX store handlers don't check invcode again
     reglist|=1<<addr;
     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
     jaddr=0;
   }
-#endif
-  if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
+  if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
     if(!c||memtarget) {
       #ifdef DESTRUCTIVE_SHIFT
       // The x86 shift operation is 'destructive'; it overwrites the
@@ -3270,7 +2929,7 @@ void store_assemble(int i,struct regstat *i_regs)
       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
       emit_callne(invalidate_addr_reg[addr]);
       #else
-      jaddr2=(int)out;
+      int jaddr2=(int)out;
       emit_jne(0);
       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
       #endif
@@ -3331,16 +2990,16 @@ void store_assemble(int i,struct regstat *i_regs)
     #ifdef __arm__
     restore_regs(0x100f);
     #endif
-  }/**/
+  }*/
 }
 
 void storelr_assemble(int i,struct regstat *i_regs)
 {
   int s,th,tl;
   int temp;
-  int temp2;
+  int temp2=-1;
   int offset;
-  int jaddr=0,jaddr2;
+  int jaddr=0;
   int case1,case2,case3;
   int done0,done1,done2;
   int memtarget=0,c=0;
@@ -3356,7 +3015,6 @@ void storelr_assemble(int i,struct regstat *i_regs)
     c=(i_regs->isconst>>s)&1;
     if(c) {
       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
-      if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
     }
   }
   assert(tl>=0);
@@ -3364,41 +3022,26 @@ void storelr_assemble(int i,struct regstat *i_regs)
     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
   }
   assert(temp>=0);
-  if(!using_tlb) {
-    if(!c) {
-      emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
-      if(!offset&&s!=temp) emit_mov(s,temp);
-      jaddr=(int)out;
-      emit_jno(0);
-    }
-    else
-    {
-      if(!memtarget||!rs1[i]) {
-        jaddr=(int)out;
-        emit_jmp(0);
-      }
-    }
-    #ifdef RAM_OFFSET
-    int map=get_reg(i_regs->regmap,ROREG);
-    if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
-    gen_tlb_addr_w(temp,map);
-    #else
-    if((u_int)rdram!=0x80000000) 
-      emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
-    #endif
-  }else{ // using tlb
-    int map=get_reg(i_regs->regmap,TLREG);
-    assert(map>=0);
-    reglist&=~(1<<map);
-    map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
-    if(!c&&!offset&&s>=0) emit_mov(s,temp);
-    do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
-    if(!jaddr&&!memtarget) {
+  if(!c) {
+    emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
+    if(!offset&&s!=temp) emit_mov(s,temp);
+    jaddr=(int)out;
+    emit_jno(0);
+  }
+  else
+  {
+    if(!memtarget||!rs1[i]) {
       jaddr=(int)out;
       emit_jmp(0);
     }
-    gen_tlb_addr_w(temp,map);
   }
+  #ifdef RAM_OFFSET
+  int map=get_reg(i_regs->regmap,ROREG);
+  if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
+  #else
+  if((u_int)rdram!=0x80000000)
+    emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
+  #endif
 
   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
     temp2=get_reg(i_regs->regmap,FTEMP);
@@ -3541,7 +3184,7 @@ void storelr_assemble(int i,struct regstat *i_regs)
   }
   if(!c||!memtarget)
     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
-  if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
+  if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
     #ifdef RAM_OFFSET
     int map=get_reg(i_regs->regmap,ROREG);
     if(map<0) map=HOST_TEMPREG;
@@ -3559,7 +3202,7 @@ void storelr_assemble(int i,struct regstat *i_regs)
     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
     emit_callne(invalidate_addr_reg[temp]);
     #else
-    jaddr2=(int)out;
+    int jaddr2=(int)out;
     emit_jne(0);
     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
     #endif
@@ -3576,194 +3219,12 @@ void storelr_assemble(int i,struct regstat *i_regs)
     emit_call((int)memdebug);
     emit_popa();
     //restore_regs(0x100f);
-  /**/
+  */
 }
 
 void c1ls_assemble(int i,struct regstat *i_regs)
 {
-#ifndef DISABLE_COP1
-  int s,th,tl;
-  int temp,ar;
-  int map=-1;
-  int offset;
-  int c=0;
-  int jaddr,jaddr2=0,jaddr3,type;
-  int agr=AGEN1+(i&1);
-  u_int hr,reglist=0;
-  th=get_reg(i_regs->regmap,FTEMP|64);
-  tl=get_reg(i_regs->regmap,FTEMP);
-  s=get_reg(i_regs->regmap,rs1[i]);
-  temp=get_reg(i_regs->regmap,agr);
-  if(temp<0) temp=get_reg(i_regs->regmap,-1);
-  offset=imm[i];
-  assert(tl>=0);
-  assert(rs1[i]>0);
-  assert(temp>=0);
-  for(hr=0;hr<HOST_REGS;hr++) {
-    if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
-  }
-  if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
-  if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
-  {
-    // Loads use a temporary register which we need to save
-    reglist|=1<<temp;
-  }
-  if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
-    ar=temp;
-  else // LWC1/LDC1
-    ar=tl;
-  //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
-  //else c=(i_regs->wasconst>>s)&1;
-  if(s>=0) c=(i_regs->wasconst>>s)&1;
-  // Check cop1 unusable
-  if(!cop1_usable) {
-    signed char rs=get_reg(i_regs->regmap,CSREG);
-    assert(rs>=0);
-    emit_testimm(rs,0x20000000);
-    jaddr=(int)out;
-    emit_jeq(0);
-    add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
-    cop1_usable=1;
-  }
-  if (opcode[i]==0x39) { // SWC1 (get float address)
-    emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
-  }
-  if (opcode[i]==0x3D) { // SDC1 (get double address)
-    emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
-  }
-  // Generate address + offset
-  if(!using_tlb) {
-    if(!c)
-      emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
-  }
-  else
-  {
-    map=get_reg(i_regs->regmap,TLREG);
-    assert(map>=0);
-    reglist&=~(1<<map);
-    if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
-      map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
-    }
-    if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
-      map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
-    }
-  }
-  if (opcode[i]==0x39) { // SWC1 (read float)
-    emit_readword_indexed(0,tl,tl);
-  }
-  if (opcode[i]==0x3D) { // SDC1 (read double)
-    emit_readword_indexed(4,tl,th);
-    emit_readword_indexed(0,tl,tl);
-  }
-  if (opcode[i]==0x31) { // LWC1 (get target address)
-    emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
-  }
-  if (opcode[i]==0x35) { // LDC1 (get target address)
-    emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
-  }
-  if(!using_tlb) {
-    if(!c) {
-      jaddr2=(int)out;
-      emit_jno(0);
-    }
-    else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
-      jaddr2=(int)out;
-      emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
-    }
-    #ifdef DESTRUCTIVE_SHIFT
-    if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
-      if(!offset&&!c&&s>=0) emit_mov(s,ar);
-    }
-    #endif
-  }else{
-    if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
-      do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
-    }
-    if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
-      do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
-    }
-  }
-  if (opcode[i]==0x31) { // LWC1
-    //if(s>=0&&!c&&!offset) emit_mov(s,tl);
-    //gen_tlb_addr_r(ar,map);
-    //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
-    #ifdef HOST_IMM_ADDR32
-    if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
-    else
-    #endif
-    emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
-    type=LOADW_STUB;
-  }
-  if (opcode[i]==0x35) { // LDC1
-    assert(th>=0);
-    //if(s>=0&&!c&&!offset) emit_mov(s,tl);
-    //gen_tlb_addr_r(ar,map);
-    //emit_readword_indexed((int)rdram-0x80000000,tl,th);
-    //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
-    #ifdef HOST_IMM_ADDR32
-    if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
-    else
-    #endif
-    emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
-    type=LOADD_STUB;
-  }
-  if (opcode[i]==0x39) { // SWC1
-    //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
-    emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
-    type=STOREW_STUB;
-  }
-  if (opcode[i]==0x3D) { // SDC1
-    assert(th>=0);
-    //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
-    //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
-    emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
-    type=STORED_STUB;
-  }
-  if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
-    if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
-      #ifndef DESTRUCTIVE_SHIFT
-      temp=offset||c||s<0?ar:s;
-      #endif
-      #if defined(HOST_IMM8)
-      int ir=get_reg(i_regs->regmap,INVCP);
-      assert(ir>=0);
-      emit_cmpmem_indexedsr12_reg(ir,temp,1);
-      #else
-      emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
-      #endif
-      #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
-      emit_callne(invalidate_addr_reg[temp]);
-      #else
-      jaddr3=(int)out;
-      emit_jne(0);
-      add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
-      #endif
-    }
-  }
-  if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
-  if (opcode[i]==0x31) { // LWC1 (write float)
-    emit_writeword_indexed(tl,0,temp);
-  }
-  if (opcode[i]==0x35) { // LDC1 (write double)
-    emit_writeword_indexed(th,4,temp);
-    emit_writeword_indexed(tl,0,temp);
-  }
-  //if(opcode[i]==0x39)
-  /*if(opcode[i]==0x39||opcode[i]==0x31)
-  {
-    emit_pusha();
-        emit_readword((int)&last_count,ECX);
-        if(get_reg(i_regs->regmap,CCREG)<0)
-          emit_loadreg(CCREG,HOST_CCREG);
-        emit_add(HOST_CCREG,ECX,HOST_CCREG);
-        emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
-        emit_writeword(HOST_CCREG,(int)&Count);
-    emit_call((int)memdebug);
-    emit_popa();
-  }/**/
-#else
   cop1_unusable(i, i_regs);
-#endif
 }
 
 void c2ls_assemble(int i,struct regstat *i_regs)
@@ -3772,7 +3233,7 @@ void c2ls_assemble(int i,struct regstat *i_regs)
   int ar;
   int offset;
   int memtarget=0,c=0;
-  int jaddr2=0,jaddr3,type;
+  int jaddr2=0,type;
   int agr=AGEN1+(i&1);
   int fastio_reg_override=0;
   u_int hr,reglist=0;
@@ -3782,7 +3243,6 @@ void c2ls_assemble(int i,struct regstat *i_regs)
   offset=imm[i];
   assert(rs1[i]>0);
   assert(tl>=0);
-  assert(!using_tlb);
 
   for(hr=0;hr<HOST_REGS;hr++) {
     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
@@ -3854,7 +3314,7 @@ void c2ls_assemble(int i,struct regstat *i_regs)
     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
     emit_callne(invalidate_addr_reg[ar]);
     #else
-    jaddr3=(int)out;
+    int jaddr3=(int)out;
     emit_jne(0);
     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
     #endif
@@ -3915,6 +3375,7 @@ void syscall_assemble(int i,struct regstat *i_regs)
   signed char ccreg=get_reg(i_regs->regmap,CCREG);
   assert(ccreg==HOST_CCREG);
   assert(!is_delayslot);
+  (void)ccreg;
   emit_movimm(start+i*4,EAX); // Get PC
   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
   emit_jmp((int)jump_syscall_hle); // XXX
@@ -3925,6 +3386,7 @@ void hlecall_assemble(int i,struct regstat *i_regs)
   signed char ccreg=get_reg(i_regs->regmap,CCREG);
   assert(ccreg==HOST_CCREG);
   assert(!is_delayslot);
+  (void)ccreg;
   emit_movimm(start+i*4+4,0); // Get PC
   emit_movimm((int)psxHLEt[source[i]&7],1);
   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
@@ -3936,6 +3398,7 @@ void intcall_assemble(int i,struct regstat *i_regs)
   signed char ccreg=get_reg(i_regs->regmap,CCREG);
   assert(ccreg==HOST_CCREG);
   assert(!is_delayslot);
+  (void)ccreg;
   emit_movimm(start+i*4,0); // Get PC
   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
   emit_jmp((int)jump_intcall);
@@ -4004,7 +3467,7 @@ int internal_branch(uint64_t i_is32,int addr)
   if(addr&1) return 0; // Indirect (register) jump
   if(addr>=start && addr<start+slen*4-4)
   {
-    int t=(addr-start)>>2;
+    //int t=(addr-start)>>2;
     // Delay slots are not valid branch targets
     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
     // 64 -> 32 bit transition requires a recompile
@@ -4014,11 +3477,7 @@ int internal_branch(uint64_t i_is32,int addr)
       else printf("optimizable: yes\n");
     }*/
     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
-#ifndef FORCE32
-    if(requires_32bit[t]&~i_is32) return 0;
-    else
-#endif
-      return 1;
+    return 1;
   }
   return 0;
 }
@@ -4153,10 +3612,9 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
     int ra=-1;
     int agr=AGEN1+(i&1);
-    int mgr=MGEN1+(i&1);
     if(itype[i]==LOAD) {
       ra=get_reg(i_regs->regmap,rt1[i]);
-      if(ra<0) ra=get_reg(i_regs->regmap,-1); 
+      if(ra<0) ra=get_reg(i_regs->regmap,-1);
       assert(ra>=0);
     }
     if(itype[i]==LOADLR) {
@@ -4175,17 +3633,11 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
       }
     }
     int rs=get_reg(i_regs->regmap,rs1[i]);
-    int rm=get_reg(i_regs->regmap,TLREG);
     if(ra>=0) {
       int offset=imm[i];
       int c=(i_regs->wasconst>>rs)&1;
       if(rs1[i]==0) {
         // Using r0 as a base address
-        /*if(rm>=0) {
-          if(!entry||entry[rm]!=mgr) {
-            generate_map_const(offset,rm);
-          } // else did it in the previous cycle
-        }*/
         if(!entry||entry[ra]!=agr) {
           if (opcode[i]==0x22||opcode[i]==0x26) {
             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
@@ -4203,22 +3655,6 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
         //  printf("poor load scheduling!\n");
       }
       else if(c) {
-#ifndef DISABLE_TLB
-        if(rm>=0) {
-          if(!entry||entry[rm]!=mgr) {
-            if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
-              // Stores to memory go thru the mapper to detect self-modifying
-              // code, loads don't.
-              if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
-                 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
-                generate_map_const(constmap[i][rs]+offset,rm);
-            }else{
-              if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
-                generate_map_const(constmap[i][rs]+offset,rm);
-            }
-          }
-        }
-#endif
         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
           if(!entry||entry[ra]!=agr) {
             if (opcode[i]==0x22||opcode[i]==0x26) {
@@ -4227,8 +3663,7 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
             }else{
               #ifdef HOST_IMM_ADDR32
-              if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
-                 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
+              if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32)) // LWC1/LDC1/LWC2/LDC2
               #endif
               emit_movimm(constmap[i][rs]+offset,ra);
               regs[i].loadedconst|=1<<ra;
@@ -4248,32 +3683,6 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
   // Preload constants for next instruction
   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
     int agr,ra;
-    #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
-    // Mapper entry
-    agr=MGEN1+((i+1)&1);
-    ra=get_reg(i_regs->regmap,agr);
-    if(ra>=0) {
-      int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
-      int offset=imm[i+1];
-      int c=(regs[i+1].wasconst>>rs)&1;
-      if(c) {
-        if(itype[i+1]==STORE||itype[i+1]==STORELR
-           ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
-          // Stores to memory go thru the mapper to detect self-modifying
-          // code, loads don't.
-          if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
-             (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
-            generate_map_const(constmap[i+1][rs]+offset,ra);
-        }else{
-          if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
-            generate_map_const(constmap[i+1][rs]+offset,ra);
-        }
-      }
-      /*else if(rs1[i]==0) {
-        generate_map_const(offset,ra);
-      }*/
-    }
-    #endif
     // Actual address
     agr=AGEN1+((i+1)&1);
     ra=get_reg(i_regs->regmap,agr);
@@ -4288,8 +3697,7 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
         }else{
           #ifdef HOST_IMM_ADDR32
-          if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
-             (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
+          if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32)) // LWC1/LDC1/LWC2/LDC2
           #endif
           emit_movimm(constmap[i+1][rs]+offset,ra);
           regs[i+1].loadedconst|=1<<ra;
@@ -4309,7 +3717,7 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
   }
 }
 
-int get_final_value(int hr, int i, int *value)
+static int get_final_value(int hr, int i, int *value)
 {
   int reg=regs[i].regmap[hr];
   while(i<slen-1) {
@@ -4328,9 +3736,6 @@ int get_final_value(int hr, int i, int *value)
         // Load in delay slot, out-of-order execution
         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
         {
-          #ifdef HOST_IMM_ADDR32
-          if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
-          #endif
           // Precompute load address
           *value=constmap[i][hr]+imm[i+2];
           return 1;
@@ -4338,9 +3743,6 @@ int get_final_value(int hr, int i, int *value)
       }
       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
       {
-        #ifdef HOST_IMM_ADDR32
-        if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
-        #endif
         // Precompute load address
         *value=constmap[i][hr]+imm[i+1];
         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
@@ -4490,17 +3892,6 @@ void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
           if((i_dirty>>hr)&1) {
             if(i_regmap[hr]<64) {
               emit_storereg(i_regmap[hr],hr);
-#ifndef FORCE32
-              if( ((i_is32>>i_regmap[hr])&1) ) {
-                #ifdef DESTRUCTIVE_WRITEBACK
-                emit_sarimm(hr,31,hr);
-                emit_storereg(i_regmap[hr]|64,hr);
-                #else
-                emit_sarimm(hr,31,HOST_TEMPREG);
-                emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
-                #endif
-              }
-#endif
             }else{
               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
                 emit_storereg(i_regmap[hr],hr);
@@ -4526,17 +3917,6 @@ void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,in
             if((i_dirty>>hr)&1) {
               if(i_regmap[hr]<64) {
                 emit_storereg(i_regmap[hr],hr);
-#ifndef FORCE32
-                if( ((i_is32>>i_regmap[hr])&1) ) {
-                  #ifdef DESTRUCTIVE_WRITEBACK
-                  emit_sarimm(hr,31,hr);
-                  emit_storereg(i_regmap[hr]|64,hr);
-                  #else
-                  emit_sarimm(hr,31,HOST_TEMPREG);
-                  emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
-                  #endif
-                }
-#endif
               }else{
                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
                   emit_storereg(i_regmap[hr],hr);
@@ -4754,7 +4134,7 @@ int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
           {
             return 0;
           }
-          else 
+          else
           if((i_dirty>>hr)&1)
           {
             if(i_regmap[hr]<TEMPREG)
@@ -4792,9 +4172,6 @@ int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
       }
     }
     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
-#ifndef FORCE32
-    if(requires_32bit[t]&~i_is32) return 0;
-#endif
     // Delay slots are not valid branch targets
     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
     // Delay slots require additional processing, so do not match
@@ -5000,7 +4377,7 @@ void do_ccstub(int n)
       if(rs1[i]) {
         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
           emit_loadreg(rs1[i],s1l);
-      } 
+      }
       else {
         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
           emit_loadreg(rs2[i],s1l);
@@ -5191,7 +4568,7 @@ void do_ccstub(int n)
     load_all_regs(branch_regs[i].regmap);
   }
   emit_jmp(stubs[n][2]); // return address
-  
+
   /* This works but uses a lot of memory...
   emit_readword((int)&last_count,ECX);
   emit_add(HOST_CCREG,ECX,EAX);
@@ -5221,11 +4598,11 @@ void do_ccstub(int n)
   emit_jmpreg(EAX);*/
 }
 
-add_to_linker(int addr,int target,int ext)
+static void add_to_linker(int addr,int target,int ext)
 {
   link_addr[linkcount][0]=addr;
   link_addr[linkcount][1]=target;
-  link_addr[linkcount][2]=ext;  
+  link_addr[linkcount][2]=ext;
   linkcount++;
 }
 
@@ -5251,7 +4628,7 @@ static void ujump_assemble_write_ra(int i)
     #endif
     {
       #ifdef REG_PREFETCH
-      if(temp>=0) 
+      if(temp>=0)
       {
         if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
       }
@@ -5266,16 +4643,16 @@ static void ujump_assemble_write_ra(int i)
 
 void ujump_assemble(int i,struct regstat *i_regs)
 {
-  signed char *i_regmap=i_regs->regmap;
   int ra_done=0;
   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
   address_generation(i+1,i_regs,regs[i].regmap_entry);
   #ifdef REG_PREFETCH
   int temp=get_reg(branch_regs[i].regmap,PTEMP);
-  if(rt1[i]==31&&temp>=0) 
+  if(rt1[i]==31&&temp>=0)
   {
+    signed char *i_regmap=i_regs->regmap;
     int return_address=start+i*4+8;
-    if(get_reg(branch_regs[i].regmap,31)>0) 
+    if(get_reg(branch_regs[i].regmap,31)>0)
     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
   }
   #endif
@@ -5326,7 +4703,7 @@ static void rjump_assemble_write_ra(int i)
   assert(rt>=0);
   return_address=start+i*4+8;
   #ifdef REG_PREFETCH
-  if(temp>=0) 
+  if(temp>=0)
   {
     if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
   }
@@ -5339,9 +4716,8 @@ static void rjump_assemble_write_ra(int i)
 
 void rjump_assemble(int i,struct regstat *i_regs)
 {
-  signed char *i_regmap=i_regs->regmap;
   int temp;
-  int rs,cc,adj;
+  int rs,cc;
   int ra_done=0;
   rs=get_reg(branch_regs[i].regmap,rs1[i]);
   assert(rs>=0);
@@ -5355,9 +4731,10 @@ void rjump_assemble(int i,struct regstat *i_regs)
   }
   address_generation(i+1,i_regs,regs[i].regmap_entry);
   #ifdef REG_PREFETCH
-  if(rt1[i]==31) 
+  if(rt1[i]==31)
   {
     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
+      signed char *i_regmap=i_regs->regmap;
       int return_address=start+i*4+8;
       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
     }
@@ -5386,6 +4763,7 @@ void rjump_assemble(int i,struct regstat *i_regs)
     rjump_assemble_write_ra(i);
   cc=get_reg(branch_regs[i].regmap,CCREG);
   assert(cc==HOST_CCREG);
+  (void)cc;
   #ifdef USE_MINI_HT
   int rh=get_reg(branch_regs[i].regmap,RHASH);
   int ht=get_reg(branch_regs[i].regmap,RHTBL);
@@ -5416,13 +4794,11 @@ void rjump_assemble(int i,struct regstat *i_regs)
   //assert(adj==0);
   emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
-#ifdef PCSX
   if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
     // special case for RFE
     emit_jmp(0);
   else
-#endif
-  emit_jns(0);
+    emit_jns(0);
   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
   #ifdef USE_MINI_HT
   if(rs1[i]==31) {
@@ -5489,7 +4865,7 @@ void cjump_assemble(int i,struct regstat *i_regs)
   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
   if(i>(ba[i]-start)>>2) invert=1;
   #endif
-  
+
   if(ooo[i]) {
     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
@@ -5544,7 +4920,7 @@ void cjump_assemble(int i,struct regstat *i_regs)
     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
     cc=get_reg(branch_regs[i].regmap,CCREG);
     assert(cc==HOST_CCREG);
-    if(unconditional) 
+    if(unconditional)
       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
     //assem_debug("cycle count (adj)\n");
@@ -5616,7 +4992,7 @@ void cjump_assemble(int i,struct regstat *i_regs)
           emit_jne(0);
         }
       } // if(!only32)
-          
+
       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
       assert(s1l>=0);
       if(opcode[i]==4) // BEQ
@@ -5746,7 +5122,7 @@ void cjump_assemble(int i,struct regstat *i_regs)
           emit_jne(1);
         }
       } // if(!only32)
-          
+
       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
       assert(s1l>=0);
       if((opcode[i]&0x2f)==4) // BEQ
@@ -5929,7 +5305,7 @@ void sjump_assemble(int i,struct regstat *i_regs)
     }
     cc=get_reg(branch_regs[i].regmap,CCREG);
     assert(cc==HOST_CCREG);
-    if(unconditional) 
+    if(unconditional)
       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
     assem_debug("cycle count (adj)\n");
@@ -6016,7 +5392,7 @@ void sjump_assemble(int i,struct regstat *i_regs)
           }
         }
       } // if(!only32)
-          
+
       if(invert) {
         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
@@ -6264,7 +5640,7 @@ void fjump_assemble(int i,struct regstat *i_regs)
         {
         }
       } // if(!only32)
-          
+
       if(invert) {
         if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
@@ -6393,7 +5769,6 @@ static void pagespan_assemble(int i,struct regstat *i_regs)
   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
   int s2l=get_reg(i_regs->regmap,rs2[i]);
   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
-  void *nt_branch=NULL;
   int taken=0;
   int nottaken=0;
   int unconditional=0;
@@ -6410,7 +5785,7 @@ static void pagespan_assemble(int i,struct regstat *i_regs)
     s1h=s2h=-1;
   }
   int hr=0;
-  int addr,alt,ntaddr;
+  int addr=-1,alt=-1,ntaddr=-1;
   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
   else {
     while(hr<HOST_REGS)
@@ -6772,14 +6147,14 @@ void unneeded_registers(int istart,int iend,int r)
     {
       // If subroutine call, flag return address as a possible branch target
       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
-      
+
       if(ba[i]<start || ba[i]>=(start+slen*4))
       {
         // Branch out of this block, flush all regs
         u=1;
         uu=1;
         gte_u=gte_u_unknown;
-        /* Hexagon hack 
+        /* Hexagon hack
         if(itype[i]==UJUMP&&rt1[i]==31)
         {
           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
@@ -7002,387 +6377,33 @@ void unneeded_registers(int istart,int iend,int r)
     // R0 is always unneeded
     u|=1;uu|=1;
     // Save it
-    unneeded_reg[i]=u;
-    unneeded_reg_upper[i]=uu;
-    gte_unneeded[i]=gte_u;
-    /*
-    printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
-    printf("U:");
-    int r;
-    for(r=1;r<=CCREG;r++) {
-      if((unneeded_reg[i]>>r)&1) {
-        if(r==HIREG) printf(" HI");
-        else if(r==LOREG) printf(" LO");
-        else printf(" r%d",r);
-      }
-    }
-    printf(" UU:");
-    for(r=1;r<=CCREG;r++) {
-      if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
-        if(r==HIREG) printf(" HI");
-        else if(r==LOREG) printf(" LO");
-        else printf(" r%d",r);
-      }
-    }
-    printf("\n");*/
-  }
-#ifdef FORCE32
-  for (i=iend;i>=istart;i--)
-  {
-    unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
-  }
-#endif
-}
-
-// Identify registers which are likely to contain 32-bit values
-// This is used to predict whether any branches will jump to a
-// location with 64-bit values in registers.
-static void provisional_32bit()
-{
-  int i,j;
-  uint64_t is32=1;
-  uint64_t lastbranch=1;
-  
-  for(i=0;i<slen;i++)
-  {
-    if(i>0) {
-      if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
-        if(i>1) is32=lastbranch;
-        else is32=1;
-      }
-    }
-    if(i>1)
-    {
-      if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
-        if(likely[i-2]) {
-          if(i>2) is32=lastbranch;
-          else is32=1;
-        }
-      }
-      if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
-      {
-        if(rs1[i-2]==0||rs2[i-2]==0)
-        {
-          if(rs1[i-2]) {
-            is32|=1LL<<rs1[i-2];
-          }
-          if(rs2[i-2]) {
-            is32|=1LL<<rs2[i-2];
-          }
-        }
-      }
-    }
-    // If something jumps here with 64-bit values
-    // then promote those registers to 64 bits
-    if(bt[i])
-    {
-      uint64_t temp_is32=is32;
-      for(j=i-1;j>=0;j--)
-      {
-        if(ba[j]==start+i*4) 
-          //temp_is32&=branch_regs[j].is32;
-          temp_is32&=p32[j];
-      }
-      for(j=i;j<slen;j++)
-      {
-        if(ba[j]==start+i*4) 
-          temp_is32=1;
-      }
-      is32=temp_is32;
-    }
-    int type=itype[i];
-    int op=opcode[i];
-    int op2=opcode2[i];
-    int rt=rt1[i];
-    int s1=rs1[i];
-    int s2=rs2[i];
-    if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
-      // Branches don't write registers, consider the delay slot instead.
-      type=itype[i+1];
-      op=opcode[i+1];
-      op2=opcode2[i+1];
-      rt=rt1[i+1];
-      s1=rs1[i+1];
-      s2=rs2[i+1];
-      lastbranch=is32;
-    }
-    switch(type) {
-      case LOAD:
-        if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
-           opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
-          is32&=~(1LL<<rt);
-        else
-          is32|=1LL<<rt;
-        break;
-      case STORE:
-      case STORELR:
-        break;
-      case LOADLR:
-        if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
-        if(op==0x22) is32|=1LL<<rt; // LWL
-        break;
-      case IMM16:
-        if (op==0x08||op==0x09|| // ADDI/ADDIU
-            op==0x0a||op==0x0b|| // SLTI/SLTIU
-            op==0x0c|| // ANDI
-            op==0x0f)  // LUI
-        {
-          is32|=1LL<<rt;
-        }
-        if(op==0x18||op==0x19) { // DADDI/DADDIU
-          is32&=~(1LL<<rt);
-          //if(imm[i]==0)
-          //  is32|=((is32>>s1)&1LL)<<rt;
-        }
-        if(op==0x0d||op==0x0e) { // ORI/XORI
-          uint64_t sr=((is32>>s1)&1LL);
-          is32&=~(1LL<<rt);
-          is32|=sr<<rt;
-        }
-        break;
-      case UJUMP:
-        break;
-      case RJUMP:
-        break;
-      case CJUMP:
-        break;
-      case SJUMP:
-        break;
-      case FJUMP:
-        break;
-      case ALU:
-        if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
-          is32|=1LL<<rt;
-        }
-        if(op2==0x2a||op2==0x2b) { // SLT/SLTU
-          is32|=1LL<<rt;
-        }
-        else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
-          uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
-          is32&=~(1LL<<rt);
-          is32|=sr<<rt;
-        }
-        else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
-          if(s1==0&&s2==0) {
-            is32|=1LL<<rt;
-          }
-          else if(s2==0) {
-            uint64_t sr=((is32>>s1)&1LL);
-            is32&=~(1LL<<rt);
-            is32|=sr<<rt;
-          }
-          else if(s1==0) {
-            uint64_t sr=((is32>>s2)&1LL);
-            is32&=~(1LL<<rt);
-            is32|=sr<<rt;
-          }
-          else {
-            is32&=~(1LL<<rt);
-          }
-        }
-        else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
-          if(s1==0&&s2==0) {
-            is32|=1LL<<rt;
-          }
-          else if(s2==0) {
-            uint64_t sr=((is32>>s1)&1LL);
-            is32&=~(1LL<<rt);
-            is32|=sr<<rt;
-          }
-          else {
-            is32&=~(1LL<<rt);
-          }
-        }
-        break;
-      case MULTDIV:
-        if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
-          is32&=~((1LL<<HIREG)|(1LL<<LOREG));
-        }
-        else {
-          is32|=(1LL<<HIREG)|(1LL<<LOREG);
-        }
-        break;
-      case MOV:
-        {
-          uint64_t sr=((is32>>s1)&1LL);
-          is32&=~(1LL<<rt);
-          is32|=sr<<rt;
-        }
-        break;
-      case SHIFT:
-        if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
-        else is32|=1LL<<rt; // SLLV/SRLV/SRAV
-        break;
-      case SHIFTIMM:
-        is32|=1LL<<rt;
-        // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
-        if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
-        break;
-      case COP0:
-        if(op2==0) is32|=1LL<<rt; // MFC0
-        break;
-      case COP1:
-      case COP2:
-        if(op2==0) is32|=1LL<<rt; // MFC1
-        if(op2==1) is32&=~(1LL<<rt); // DMFC1
-        if(op2==2) is32|=1LL<<rt; // CFC1
-        break;
-      case C1LS:
-      case C2LS:
-        break;
-      case FLOAT:
-      case FCONV:
-        break;
-      case FCOMP:
-        break;
-      case C2OP:
-      case SYSCALL:
-      case HLECALL:
-        break;
-      default:
-        break;
-    }
-    is32|=1;
-    p32[i]=is32;
-
-    if(i>0)
-    {
-      if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
-      {
-        if(rt1[i-1]==31) // JAL/JALR
-        {
-          // Subroutine call will return here, don't alloc any registers
-          is32=1;
-        }
-        else if(i+1<slen)
-        {
-          // Internal branch will jump here, match registers to caller
-          is32=0x3FFFFFFFFLL;
-        }
-      }
-    }
-  }
-}
-
-// Identify registers which may be assumed to contain 32-bit values
-// and where optimizations will rely on this.
-// This is used to determine whether backward branches can safely
-// jump to a location with 64-bit values in registers.
-static void provisional_r32()
-{
-  u_int r32=0;
-  int i;
-  
-  for (i=slen-1;i>=0;i--)
-  {
-    int hr;
-    if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
-    {
-      if(ba[i]<start || ba[i]>=(start+slen*4))
-      {
-        // Branch out of this block, don't need anything
-        r32=0;
-      }
-      else
-      {
-        // Internal branch
-        // Need whatever matches the target
-        // (and doesn't get overwritten by the delay slot instruction)
-        r32=0;
-        int t=(ba[i]-start)>>2;
-        if(ba[i]>start+i*4) {
-          // Forward branch
-          //if(!(requires_32bit[t]&~regs[i].was32))
-          //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
-          if(!(pr32[t]&~regs[i].was32))
-            r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
-        }else{
-          // Backward branch
-          if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
-            r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
-        }
-      }
-      // Conditional branch may need registers for following instructions
-      if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
-      {
-        if(i<slen-2) {
-          //r32|=requires_32bit[i+2];
-          r32|=pr32[i+2];
-          r32&=regs[i].was32;
-          // Mark this address as a branch target since it may be called
-          // upon return from interrupt
-          //bt[i+2]=1;
-        }
-      }
-      // Merge in delay slot
-      if(!likely[i]) {
-        // These are overwritten unless the branch is "likely"
-        // and the delay slot is nullified if not taken
-        r32&=~(1LL<<rt1[i+1]);
-        r32&=~(1LL<<rt2[i+1]);
-      }
-      // Assume these are needed (delay slot)
-      if(us1[i+1]>0)
-      {
-        if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
-      }
-      if(us2[i+1]>0)
-      {
-        if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
-      }
-      if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
-      {
-        if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
-      }
-      if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
-      {
-        if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
+    unneeded_reg[i]=u;
+    unneeded_reg_upper[i]=uu;
+    gte_unneeded[i]=gte_u;
+    /*
+    printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
+    printf("U:");
+    int r;
+    for(r=1;r<=CCREG;r++) {
+      if((unneeded_reg[i]>>r)&1) {
+        if(r==HIREG) printf(" HI");
+        else if(r==LOREG) printf(" LO");
+        else printf(" r%d",r);
       }
     }
-    else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
-    {
-      // SYSCALL instruction (software interrupt)
-      r32=0;
-    }
-    else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
-    {
-      // ERET instruction (return from interrupt)
-      r32=0;
-    }
-    // Check 32 bits
-    r32&=~(1LL<<rt1[i]);
-    r32&=~(1LL<<rt2[i]);
-    if(us1[i]>0)
-    {
-      if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
-    }
-    if(us2[i]>0)
-    {
-      if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
-    }
-    if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
-    {
-      if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
-    }
-    if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
-    {
-      if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
-    }
-    //requires_32bit[i]=r32;
-    pr32[i]=r32;
-    
-    // Dirty registers which are 32-bit, require 32-bit input
-    // as they will be written as 32-bit values
-    for(hr=0;hr<HOST_REGS;hr++)
-    {
-      if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
-        if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
-          if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
-          pr32[i]|=1LL<<regs[i].regmap_entry[hr];
-          //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
-        }
+    printf(" UU:");
+    for(r=1;r<=CCREG;r++) {
+      if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
+        if(r==HIREG) printf(" HI");
+        else if(r==LOREG) printf(" LO");
+        else printf(" r%d",r);
       }
     }
+    printf("\n");*/
+  }
+  for (i=iend;i>=istart;i--)
+  {
+    unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
   }
 }
 
@@ -7723,7 +6744,7 @@ void clean_registers(int istart,int iend,int wr)
         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
         if(i>istart) {
-          if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP) 
+          if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
           {
             // Don't store a register immediately after writing it,
             // may prevent dual-issue.
@@ -7757,7 +6778,7 @@ void clean_registers(int istart,int iend,int wr)
               if(r!=EXCLUDE_REG) {
                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
-                }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
+                }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
               }
             }
           }
@@ -7769,7 +6790,7 @@ void clean_registers(int istart,int iend,int wr)
               if(r!=EXCLUDE_REG) {
                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
-                }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
+                }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
               }
             }
           }
@@ -7812,7 +6833,7 @@ void clean_registers(int istart,int iend,int wr)
             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
           } else {
             wont_dirty_i|=1<<r;
-            /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
+            /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
           }
         }
       }
@@ -7953,15 +6974,6 @@ void new_dynarec_clear_full()
   stop_after_jal=0;
   inv_code_start=inv_code_end=~0;
   // TLB
-#ifndef DISABLE_TLB
-  using_tlb=0;
-  for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
-    memory_map[n]=-1;
-  for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
-    memory_map[n]=((u_int)rdram-0x80000000)>>2;
-  for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
-    memory_map[n]=-1;
-#endif
   for(n=0;n<4096;n++) ll_clear(jump_in+n);
   for(n=0;n<4096;n++) ll_clear(jump_out+n);
   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
@@ -7983,58 +6995,12 @@ void new_dynarec_init()
   if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
     SysPrintf("mprotect() failed: %s\n", strerror(errno));
 #endif
-#ifdef MUPEN64
-  rdword=&readmem_dword;
-  fake_pc.f.r.rs=&readmem_dword;
-  fake_pc.f.r.rt=&readmem_dword;
-  fake_pc.f.r.rd=&readmem_dword;
-#endif
-  int n;
   cycle_multiplier=200;
   new_dynarec_clear_full();
 #ifdef HOST_IMM8
   // Copy this into local area so we don't have to put it in every literal pool
   invc_ptr=invalid_code;
 #endif
-#ifdef MUPEN64
-  for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
-    writemem[n] = write_nomem_new;
-    writememb[n] = write_nomemb_new;
-    writememh[n] = write_nomemh_new;
-#ifndef FORCE32
-    writememd[n] = write_nomemd_new;
-#endif
-    readmem[n] = read_nomem_new;
-    readmemb[n] = read_nomemb_new;
-    readmemh[n] = read_nomemh_new;
-#ifndef FORCE32
-    readmemd[n] = read_nomemd_new;
-#endif
-  }
-  for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
-    writemem[n] = write_rdram_new;
-    writememb[n] = write_rdramb_new;
-    writememh[n] = write_rdramh_new;
-#ifndef FORCE32
-    writememd[n] = write_rdramd_new;
-#endif
-  }
-  for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
-    writemem[n] = write_nomem_new;
-    writememb[n] = write_nomemb_new;
-    writememh[n] = write_nomemh_new;
-#ifndef FORCE32
-    writememd[n] = write_nomemd_new;
-#endif
-    readmem[n] = read_nomem_new;
-    readmemb[n] = read_nomemb_new;
-    readmemh[n] = read_nomemh_new;
-#ifndef FORCE32
-    readmemd[n] = read_nomemd_new;
-#endif
-  }
-#endif
-  tlb_hacks();
   arch_init();
   new_dynarec_test();
 #ifndef RAM_FIXED
@@ -8077,6 +7043,7 @@ static u_int *get_source_start(u_int addr, u_int *limit)
     *limit = (addr & 0x80600000) + 0x00200000;
     return (u_int *)((u_int)rdram + (addr&0x1fffff));
   }
+  return NULL;
 }
 
 static u_int scan_for_ret(u_int addr)
@@ -8094,6 +7061,7 @@ static u_int scan_for_ret(u_int addr)
     if (*mem == 0x03e00008) // jr $ra
       return addr + 8;
   }
+  return addr;
 }
 
 struct savestate_block {
@@ -8187,7 +7155,7 @@ int new_recompile_block(int addr)
   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
-  //if(debug) 
+  //if(debug)
   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
   /*if(Count>=312978186) {
@@ -8243,7 +7211,7 @@ int new_recompile_block(int addr)
   unsigned int type,op,op2;
 
   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
-  
+
   /* Pass 1 disassembly */
 
   for(i=0;!done;i++) {
@@ -8291,7 +7259,7 @@ int new_recompile_block(int addr)
           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
-#ifndef FORCE32
+#if 0
           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
@@ -8359,11 +7327,8 @@ int new_recompile_block(int addr)
             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
-#ifdef PCSX
             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
-#else
-            case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
-#endif
+            //case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
           }
         }
         break;
@@ -8482,7 +7447,7 @@ int new_recompile_block(int addr)
           break;
         }
         break;
-#ifndef FORCE32
+#if 0
       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
@@ -8499,14 +7464,14 @@ int new_recompile_block(int addr)
       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
-#ifndef FORCE32
+#if 0
       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
 #endif
       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
-#ifndef FORCE32
+#if 0
       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
 #endif
@@ -8514,19 +7479,18 @@ int new_recompile_block(int addr)
       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
-#ifndef FORCE32
+#if 0
       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
 #endif
       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
-#ifndef FORCE32
+#if 0
       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
 #endif
-#ifdef PCSX
       case 0x12: strcpy(insn[i],"COP2"); type=NI;
         op2=(source[i]>>21)&0x1f;
         //if (op2 & 0x10) {
@@ -8550,7 +7514,6 @@ int new_recompile_block(int addr)
       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
-#endif
       default: strcpy(insn[i],"???"); type=NI;
         SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
         break;
@@ -8821,7 +7784,6 @@ int new_recompile_block(int addr)
     else if(type==CJUMP||type==SJUMP||type==FJUMP)
       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
     else ba[i]=-1;
-#ifdef PCSX
     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
       int do_in_intrp=0;
       // branch in delay slot?
@@ -8855,7 +7817,6 @@ int new_recompile_block(int addr)
         i--; // don't compile the DS
       }
     }
-#endif
     /* Is this the end of the block? */
     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
@@ -8903,7 +7864,7 @@ int new_recompile_block(int addr)
   /* Pass 2 - Register dependencies and branch targets */
 
   unneeded_registers(0,slen-1,0);
-  
+
   /* Pass 3 - Register allocation */
 
   struct regstat current; // Current register allocations/status
@@ -8921,9 +7882,6 @@ int new_recompile_block(int addr)
   int cc=0;
   int hr=-1;
 
-#ifndef FORCE32
-  provisional_32bit();
-#endif
   if((u_int)addr&1) {
     // First instruction is delay slot
     cc=-1;
@@ -8933,7 +7891,7 @@ int new_recompile_block(int addr)
     unneeded_reg_upper[0]=1;
     current.regmap[HOST_BTREG]=BTREG;
   }
-  
+
   for(i=0;i<slen;i++)
   {
     if(bt[i])
@@ -8966,126 +7924,13 @@ int new_recompile_block(int addr)
         }
       }
     }
-#ifndef FORCE32
-    // If something jumps here with 64-bit values
-    // then promote those registers to 64 bits
-    if(bt[i])
-    {
-      uint64_t temp_is32=current.is32;
-      for(j=i-1;j>=0;j--)
-      {
-        if(ba[j]==start+i*4) 
-          temp_is32&=branch_regs[j].is32;
-      }
-      for(j=i;j<slen;j++)
-      {
-        if(ba[j]==start+i*4) 
-          //temp_is32=1;
-          temp_is32&=p32[j];
-      }
-      if(temp_is32!=current.is32) {
-        //printf("dumping 32-bit regs (%x)\n",start+i*4);
-        #ifndef DESTRUCTIVE_WRITEBACK
-        if(ds)
-        #endif
-        for(hr=0;hr<HOST_REGS;hr++)
-        {
-          int r=current.regmap[hr];
-          if(r>0&&r<64)
-          {
-            if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
-              temp_is32|=1LL<<r;
-              //printf("restore %d\n",r);
-            }
-          }
-        }
-        current.is32=temp_is32;
-      }
-    }
-#else
     current.is32=-1LL;
-#endif
 
     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
     regs[i].wasconst=current.isconst;
     regs[i].was32=current.is32;
     regs[i].wasdirty=current.dirty;
     regs[i].loadedconst=0;
-    #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
-    // To change a dirty register from 32 to 64 bits, we must write
-    // it out during the previous cycle (for branches, 2 cycles)
-    if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
-    {
-      uint64_t temp_is32=current.is32;
-      for(j=i-1;j>=0;j--)
-      {
-        if(ba[j]==start+i*4+4) 
-          temp_is32&=branch_regs[j].is32;
-      }
-      for(j=i;j<slen;j++)
-      {
-        if(ba[j]==start+i*4+4) 
-          //temp_is32=1;
-          temp_is32&=p32[j];
-      }
-      if(temp_is32!=current.is32) {
-        //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
-        for(hr=0;hr<HOST_REGS;hr++)
-        {
-          int r=current.regmap[hr];
-          if(r>0)
-          {
-            if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
-              if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
-              {
-                if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
-                {
-                  //printf("dump %d/r%d\n",hr,r);
-                  current.regmap[hr]=-1;
-                  if(get_reg(current.regmap,r|64)>=0) 
-                    current.regmap[get_reg(current.regmap,r|64)]=-1;
-                }
-              }
-            }
-          }
-        }
-      }
-    }
-    else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
-    {
-      uint64_t temp_is32=current.is32;
-      for(j=i-1;j>=0;j--)
-      {
-        if(ba[j]==start+i*4+8) 
-          temp_is32&=branch_regs[j].is32;
-      }
-      for(j=i;j<slen;j++)
-      {
-        if(ba[j]==start+i*4+8) 
-          //temp_is32=1;
-          temp_is32&=p32[j];
-      }
-      if(temp_is32!=current.is32) {
-        //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
-        for(hr=0;hr<HOST_REGS;hr++)
-        {
-          int r=current.regmap[hr];
-          if(r>0)
-          {
-            if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
-              if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
-              {
-                //printf("dump %d/r%d\n",hr,r);
-                current.regmap[hr]=-1;
-                if(get_reg(current.regmap,r|64)>=0) 
-                  current.regmap[get_reg(current.regmap,r|64)]=-1;
-              }
-            }
-          }
-        }
-      }
-    }
-    #endif
     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
       if(i+1<slen) {
         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
@@ -9169,7 +8014,7 @@ int new_recompile_block(int addr)
           }
         } else {
           // First instruction expects CCREG to be allocated
-          if(i==0&&hr==HOST_CCREG) 
+          if(i==0&&hr==HOST_CCREG)
             regs[i].regmap_entry[hr]=CCREG;
           else
             regs[i].regmap_entry[hr]=-1;
@@ -9504,7 +8349,7 @@ int new_recompile_block(int addr)
           pagespan_alloc(&current,i);
           break;
       }
-      
+
       // Drop the upper half of registers that have become 32-bit
       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
@@ -9522,7 +8367,7 @@ int new_recompile_block(int addr)
       // Create entry (branch target) regmap
       for(hr=0;hr<HOST_REGS;hr++)
       {
-        int r,or,er;
+        int r,or;
         r=current.regmap[hr];
         if(r>=0) {
           if(r!=regmap_pre[i][hr]) {
@@ -9565,7 +8410,7 @@ int new_recompile_block(int addr)
           }
         } else {
           // Branches expect CCREG to be allocated at the target
-          if(regmap_pre[i][hr]==CCREG) 
+          if(regmap_pre[i][hr]==CCREG)
             regs[i].regmap_entry[hr]=CCREG;
           else
             regs[i].regmap_entry[hr]=-1;
@@ -9875,7 +8720,7 @@ int new_recompile_block(int addr)
     {
       cc=0;
     }
-#if defined(PCSX) && !defined(DRC_DBG)
+#if !defined(DRC_DBG)
     else if(itype[i]==C2OP&&gte_cycletab[source[i]&0x3f]>2)
     {
       // GTE runs in parallel until accessed, divide by 2 for a rough guess
@@ -9885,6 +8730,10 @@ int new_recompile_block(int addr)
     {
       cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
     }
+    else if(i>1&&itype[i]==STORE&&itype[i-1]==STORE&&itype[i-2]==STORE&&!bt[i])
+    {
+      cc+=4;
+    }
     else if(itype[i]==C2LS)
     {
       cc+=4;
@@ -9912,11 +8761,11 @@ int new_recompile_block(int addr)
     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
     regs[i].waswritten=current.waswritten;
   }
-  
+
   /* Pass 4 - Cull unused host registers */
-  
+
   uint64_t nr=0;
-  
+
   for (i=slen-1;i>=0;i--)
   {
     int hr;
@@ -10058,7 +8907,7 @@ int new_recompile_block(int addr)
     }
     // Save it
     needed_reg[i]=nr;
-    
+
     // Deallocate unneeded registers
     for(hr=0;hr<HOST_REGS;hr++)
     {
@@ -10088,12 +8937,6 @@ int new_recompile_block(int addr)
             d1=dep1[i+1];
             d2=dep2[i+1];
           }
-          if(using_tlb) {
-            if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
-               itype[i+1]==STORE || itype[i+1]==STORELR ||
-               itype[i+1]==C1LS || itype[i+1]==C2LS)
-            map=TLREG;
-          } else
           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
             map=INVCP;
@@ -10148,12 +8991,7 @@ int new_recompile_block(int addr)
               d1=dep1[i];
               d2=dep2[i];
             }
-            if(using_tlb) {
-              if(itype[i]==LOAD || itype[i]==LOADLR ||
-                 itype[i]==STORE || itype[i]==STORELR ||
-                 itype[i]==C1LS || itype[i]==C2LS)
-              map=TLREG;
-            } else if(itype[i]==STORE || itype[i]==STORELR ||
+            if(itype[i]==STORE || itype[i]==STORELR ||
                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
               map=INVCP;
             }
@@ -10187,20 +9025,20 @@ int new_recompile_block(int addr)
       }
     }
   }
-  
+
   /* Pass 5 - Pre-allocate registers */
-  
+
   // If a register is allocated during a loop, try to allocate it for the
   // entire loop, if possible.  This avoids loading/storing registers
   // inside of the loop.
-  
+
   signed char f_regmap[HOST_REGS];
   clear_all_regs(f_regmap);
   for(i=0;i<slen-1;i++)
   {
     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
     {
-      if(ba[i]>=start && ba[i]<(start+i*4)) 
+      if(ba[i]>=start && ba[i]<(start+i*4))
       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
@@ -10248,10 +9086,10 @@ int new_recompile_block(int addr)
             }
           }
           if(ooo[i]) {
-            if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) 
+            if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
               f_regmap[hr]=branch_regs[i].regmap[hr];
           }else{
-            if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) 
+            if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
               f_regmap[hr]=branch_regs[i].regmap[hr];
           }
           // Avoid dirty->clean transition
@@ -10421,10 +9259,10 @@ int new_recompile_block(int addr)
                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
                 {
                   if(ooo[j]) {
-                    if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) 
+                    if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
                       break;
                   }else{
-                    if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) 
+                    if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
                       break;
                   }
                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
@@ -10497,7 +9335,7 @@ int new_recompile_block(int addr)
             regs[k].isconst&=~(1<<HOST_CCREG);
             k++;
           }
-          regs[j].regmap_entry[HOST_CCREG]=CCREG;          
+          regs[j].regmap_entry[HOST_CCREG]=CCREG;
         }
         // Work backwards from the branch target
         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
@@ -10539,18 +9377,18 @@ int new_recompile_block(int addr)
       }
     }
   }
-  
+
   // Cache memory offset or tlb map pointer if a register is available
   #ifndef HOST_IMM_ADDR32
   #ifndef RAM_OFFSET
-  if(using_tlb)
+  if(0)
   #endif
   {
     int earliest_available[HOST_REGS];
     int loop_start[HOST_REGS];
     int score[HOST_REGS];
     int end[HOST_REGS];
-    int reg=using_tlb?MMREG:ROREG;
+    int reg=ROREG;
 
     // Init
     for(hr=0;hr<HOST_REGS;hr++) {
@@ -10719,7 +9557,7 @@ int new_recompile_block(int addr)
     }
   }
   #endif
-  
+
   // This allocates registers (if possible) one instruction prior
   // to use, which can avoid a load-use penalty on certain CPUs.
   for(i=0;i<slen-1;i++)
@@ -10780,7 +9618,7 @@ int new_recompile_block(int addr)
               }
             }
           }
-          // Load source into target register 
+          // Load source into target register
           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
             {
@@ -10797,46 +9635,6 @@ int new_recompile_block(int addr)
               }
             }
           }
-          // Preload map address
-          #ifndef HOST_IMM_ADDR32
-          if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
-            hr=get_reg(regs[i+1].regmap,TLREG);
-            if(hr>=0) {
-              int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
-              if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
-                int nr;
-                if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
-                {
-                  regs[i].regmap[hr]=MGEN1+((i+1)&1);
-                  regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
-                  regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
-                  regs[i].isconst&=~(1<<hr);
-                  regs[i].isconst|=regs[i+1].isconst&(1<<hr);
-                  constmap[i][hr]=constmap[i+1][hr];
-                  regs[i+1].wasdirty&=~(1<<hr);
-                  regs[i].dirty&=~(1<<hr);
-                }
-                else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
-                {
-                  // move it to another register
-                  regs[i+1].regmap[hr]=-1;
-                  regmap_pre[i+2][hr]=-1;
-                  regs[i+1].regmap[nr]=TLREG;
-                  regmap_pre[i+2][nr]=TLREG;
-                  regs[i].regmap[nr]=MGEN1+((i+1)&1);
-                  regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
-                  regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
-                  regs[i].isconst&=~(1<<nr);
-                  regs[i+1].isconst&=~(1<<nr);
-                  regs[i].dirty&=~(1<<nr);
-                  regs[i+1].wasdirty&=~(1<<nr);
-                  regs[i+1].dirty&=~(1<<nr);
-                  regs[i+2].wasdirty&=~(1<<nr);
-                }
-              }
-            }
-          }
-          #endif
           // Address for store instruction (non-constant)
           if(itype[i+1]==STORE||itype[i+1]==STORELR
              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
@@ -10894,7 +9692,7 @@ int new_recompile_block(int addr)
             }
           }
           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
-            if(itype[i+1]==LOAD) 
+            if(itype[i+1]==LOAD)
               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
               hr=get_reg(regs[i+1].regmap,FTEMP);
@@ -10918,126 +9716,11 @@ int new_recompile_block(int addr)
       }
     }
   }
-  
+
   /* Pass 6 - Optimize clean/dirty state */
   clean_registers(0,slen-1,1);
-  
-  /* Pass 7 - Identify 32-bit registers */
-#ifndef FORCE32
-  provisional_r32();
 
-  u_int r32=0;
-  
-  for (i=slen-1;i>=0;i--)
-  {
-    int hr;
-    if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
-    {
-      if(ba[i]<start || ba[i]>=(start+slen*4))
-      {
-        // Branch out of this block, don't need anything
-        r32=0;
-      }
-      else
-      {
-        // Internal branch
-        // Need whatever matches the target
-        // (and doesn't get overwritten by the delay slot instruction)
-        r32=0;
-        int t=(ba[i]-start)>>2;
-        if(ba[i]>start+i*4) {
-          // Forward branch
-          if(!(requires_32bit[t]&~regs[i].was32))
-            r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
-        }else{
-          // Backward branch
-          //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
-          //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
-          if(!(pr32[t]&~regs[i].was32))
-            r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
-        }
-      }
-      // Conditional branch may need registers for following instructions
-      if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
-      {
-        if(i<slen-2) {
-          r32|=requires_32bit[i+2];
-          r32&=regs[i].was32;
-          // Mark this address as a branch target since it may be called
-          // upon return from interrupt
-          bt[i+2]=1;
-        }
-      }
-      // Merge in delay slot
-      if(!likely[i]) {
-        // These are overwritten unless the branch is "likely"
-        // and the delay slot is nullified if not taken
-        r32&=~(1LL<<rt1[i+1]);
-        r32&=~(1LL<<rt2[i+1]);
-      }
-      // Assume these are needed (delay slot)
-      if(us1[i+1]>0)
-      {
-        if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
-      }
-      if(us2[i+1]>0)
-      {
-        if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
-      }
-      if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
-      {
-        if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
-      }
-      if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
-      {
-        if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
-      }
-    }
-    else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
-    {
-      // SYSCALL instruction (software interrupt)
-      r32=0;
-    }
-    else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
-    {
-      // ERET instruction (return from interrupt)
-      r32=0;
-    }
-    // Check 32 bits
-    r32&=~(1LL<<rt1[i]);
-    r32&=~(1LL<<rt2[i]);
-    if(us1[i]>0)
-    {
-      if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
-    }
-    if(us2[i]>0)
-    {
-      if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
-    }
-    if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
-    {
-      if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
-    }
-    if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
-    {
-      if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
-    }
-    requires_32bit[i]=r32;
-    
-    // Dirty registers which are 32-bit, require 32-bit input
-    // as they will be written as 32-bit values
-    for(hr=0;hr<HOST_REGS;hr++)
-    {
-      if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
-        if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
-          if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
-          requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
-        }
-      }
-    }
-    //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
-  }
-#else
+  /* Pass 7 - Identify 32-bit registers */
   for (i=slen-1;i>=0;i--)
   {
     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
@@ -11050,7 +9733,6 @@ int new_recompile_block(int addr)
       }
     }
   }
-#endif
 
   if(itype[slen-1]==SPAN) {
     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
@@ -11069,26 +9751,6 @@ int new_recompile_block(int addr)
         else printf(" r%d",r);
       }
     }
-#ifndef FORCE32
-    printf(" UU:");
-    for(r=1;r<=CCREG;r++) {
-      if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
-        if(r==HIREG) printf(" HI");
-        else if(r==LOREG) printf(" LO");
-        else printf(" r%d",r);
-      }
-    }
-    printf(" 32:");
-    for(r=0;r<=CCREG;r++) {
-      //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
-      if((regs[i].was32>>r)&1) {
-        if(r==CCREG) printf(" CC");
-        else if(r==HIREG) printf(" HI");
-        else if(r==LOREG) printf(" LO");
-        else printf(" r%d",r);
-      }
-    }
-#endif
     printf("\n");
     #if defined(__i386__) || defined(__x86_64__)
     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
@@ -11104,29 +9766,7 @@ int new_recompile_block(int addr)
     if((needed_reg[i]>>5)&1) printf("ebp ");
     if((needed_reg[i]>>6)&1) printf("esi ");
     if((needed_reg[i]>>7)&1) printf("edi ");
-    printf("r:");
-    for(r=0;r<=CCREG;r++) {
-      //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
-      if((requires_32bit[i]>>r)&1) {
-        if(r==CCREG) printf(" CC");
-        else if(r==HIREG) printf(" HI");
-        else if(r==LOREG) printf(" LO");
-        else printf(" r%d",r);
-      }
-    }
     printf("\n");
-    /*printf("pr:");
-    for(r=0;r<=CCREG;r++) {
-      //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
-      if((pr32[i]>>r)&1) {
-        if(r==CCREG) printf(" CC");
-        else if(r==HIREG) printf(" HI");
-        else if(r==LOREG) printf(" LO");
-        else printf(" r%d",r);
-      }
-    }
-    if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
-    printf("\n");*/
     #if defined(__i386__) || defined(__x86_64__)
     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
     printf("dirty: ");
@@ -11210,29 +9850,6 @@ int new_recompile_block(int addr)
       #endif
       printf("\n");
     }
-#ifndef FORCE32
-    printf(" 32:");
-    for(r=0;r<=CCREG;r++) {
-      if((regs[i].is32>>r)&1) {
-        if(r==CCREG) printf(" CC");
-        else if(r==HIREG) printf(" HI");
-        else if(r==LOREG) printf(" LO");
-        else printf(" r%d",r);
-      }
-    }
-    printf("\n");
-#endif
-    /*printf(" p32:");
-    for(r=0;r<=CCREG;r++) {
-      if((p32[i]>>r)&1) {
-        if(r==CCREG) printf(" CC");
-        else if(r==HIREG) printf(" HI");
-        else if(r==LOREG) printf(" LO");
-        else printf(" r%d",r);
-      }
-    }
-    if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
-    else printf("\n");*/
     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
       #if defined(__i386__) || defined(__x86_64__)
       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
@@ -11259,18 +9876,6 @@ int new_recompile_block(int addr)
       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
       #endif
-#ifndef FORCE32
-      printf(" 32:");
-      for(r=0;r<=CCREG;r++) {
-        if((branch_regs[i].is32>>r)&1) {
-          if(r==CCREG) printf(" CC");
-          else if(r==HIREG) printf(" HI");
-          else if(r==LOREG) printf(" LO");
-          else printf(" r%d",r);
-        }
-      }
-      printf("\n");
-#endif
     }
   }
 #endif // DISASM
@@ -11288,7 +9893,6 @@ int new_recompile_block(int addr)
   }
   u_int instr_addr0_override=0;
 
-#ifdef PCSX
   if (start == 0x80030000) {
     // nasty hack for fastbios thing
     // override block entry to this code
@@ -11302,7 +9906,6 @@ int new_recompile_block(int addr)
     emit_cmp(0,1);
     emit_jne((int)new_dyna_leave);
   }
-#endif
   for(i=0;i<slen;i++)
   {
     //if(ds) printf("ds: ");
@@ -11316,8 +9919,6 @@ int new_recompile_block(int addr)
       #ifndef DESTRUCTIVE_WRITEBACK
       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
       {
-        wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
-              unneeded_reg[i],unneeded_reg_upper[i]);
         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
               unneeded_reg[i],unneeded_reg_upper[i]);
       }
@@ -11558,7 +10159,7 @@ int new_recompile_block(int addr)
           // replace it with the new address.
           // Don't add new entries.  We'll insert the
           // ones that actually get used in check_addr().
-          int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
+          u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
           if(ht_bin[0]==vaddr) {
             ht_bin[1]=entry_point;
           }
@@ -11579,41 +10180,30 @@ int new_recompile_block(int addr)
   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
   memcpy(copy,source,slen*4);
   copy+=slen*4;
-  
+
   #ifdef __arm__
   __clear_cache((void *)beginning,out);
   #endif
-  
+
   // If we're within 256K of the end of the buffer,
   // start over from the beginning. (Is 256K enough?)
   if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
-  
+
   // Trap writes to any of the pages we compiled
   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
     invalid_code[i]=0;
-#ifndef DISABLE_TLB
-    memory_map[i]|=0x40000000;
-    if((signed int)start>=(signed int)0xC0000000) {
-      assert(using_tlb);
-      j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
-      invalid_code[j]=0;
-      memory_map[j]|=0x40000000;
-      //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
-    }
-#endif
   }
   inv_code_start=inv_code_end=~0;
-#ifdef PCSX
+
   // for PCSX we need to mark all mirrors too
   if(get_page(start)<(RAM_SIZE>>12))
     for(i=start>>12;i<=(start+slen*4)>>12;i++)
       invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
       invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
       invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
-#endif
-  
+
   /* Pass 10 - Free memory by expiring oldest blocks */
-  
+
   int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
   while(expirep!=end)
   {
@@ -11637,7 +10227,7 @@ int new_recompile_block(int addr)
       case 2:
         // Clear hash table
         for(i=0;i<32;i++) {
-          int *ht_bin=hash_table[((expirep&2047)<<5)+i];
+          u_int *ht_bin=hash_table[((expirep&2047)<<5)+i];
           if((ht_bin[3]>>shift)==(base>>shift) ||
              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
@@ -11655,7 +10245,7 @@ int new_recompile_block(int addr)
       case 3:
         // Clear jump_out
         #ifdef __arm__
-        if((expirep&2047)==0) 
+        if((expirep&2047)==0)
           do_clear_cache();
         #endif
         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);