X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fpcsxmem.c;h=601a6ee849964e5ac19bf2158a41ad285245face;hp=ae35f2dffb1b8ffb720dcd711a213ed525f868f1;hb=1f77c86322bf6567909da192fdbf6c28c0596a13;hpb=3eaa704818ac8d59d31ff362d99a673ee7118641

diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c
index ae35f2df..601a6ee8 100644
--- a/libpcsxcore/new_dynarec/pcsxmem.c
+++ b/libpcsxcore/new_dynarec/pcsxmem.c
@@ -1,5 +1,5 @@
 /*
- * (C) Gražvydas "notaz" Ignotas, 2010
+ * (C) Gražvydas "notaz" Ignotas, 2010-2011
  *
  * This work is licensed under the terms of GNU GPL version 2 or later.
  * See the COPYING file in the top-level directory.
@@ -15,7 +15,7 @@
 //#define memprintf printf
 #define memprintf(...)
 
-static int ram_is_ro;
+int pcsx_ram_is_ro;
 
 static void read_mem8()
 {
@@ -74,6 +74,7 @@ extern void ari_write_ram32();
 extern void ari_write_ram_mirror8();
 extern void ari_write_ram_mirror16();
 extern void ari_write_ram_mirror32();
+extern void ari_write_ram_mirror_ro32();
 extern void ari_read_bios8();
 extern void ari_read_bios16();
 extern void ari_read_bios32();
@@ -91,12 +92,6 @@ void (*writemem[0x10000])();
 void (*writememb[0x10000])();
 void (*writememh[0x10000])();
 
-static void write_mem_check_ro32()
-{
-	if (!ram_is_ro)
-		*(u32 *)(address | 0x80000000) = word;
-}
-
 static void write_biu()
 {
 	memprintf("write_biu %08x, %08x @%08x %u\n", address, word, psxRegs.pc, psxRegs.cycle);
@@ -106,10 +101,10 @@ static void write_biu()
 
 	switch (word) {
 	case 0x800: case 0x804:
-		ram_is_ro = 1;
+		pcsx_ram_is_ro = 1;
 		break;
 	case 0: case 0x1e988:
-		ram_is_ro = 0;
+		pcsx_ram_is_ro = 0;
 		break;
 	default:
 		memprintf("write_biu: unexpected val: %08x\n", word);
@@ -184,8 +179,15 @@ static void io_write_imask32(u32 value)
 
 static void io_write_dma_icr32(u32 value)
 {
-	u32 tmp = ~value & HW_DMA_ICR;
-	HW_DMA_ICR = ((tmp ^ value) & 0xffffff) ^ tmp;
+	u32 tmp = value & 0x00ff803f;
+	tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
+	if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
+	    || tmp & HW_DMA_ICR_BUS_ERROR) {
+		if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
+			psxHu32ref(0x1070) |= SWAP32(8);
+		tmp |= HW_DMA_ICR_IRQ_SENT;
+	}
+	HW_DMA_ICR = SWAPu32(tmp);
 }
 
 #define make_dma_func(n) \
@@ -342,8 +344,8 @@ void new_dyna_pcsx_mem_init(void)
 	}
 
 	// stupid BIOS RAM check
-	writemem[0] = write_mem_check_ro32;
-	ram_is_ro = 0;
+	writemem[0] = ari_write_ram_mirror_ro32;
+	pcsx_ram_is_ro = 0;
 
 	// RAM direct
 	for (i = 0x8000; i < 0x8020; i++) {