X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fpsxhw.c;h=c90f8c73d5bfb9c50b61766c9f3e2b1661c83c5a;hp=9123f76ceb209b72e5b7551a2cb2e0e2b4620e2d;hb=581335b095ed820978d4c88f026abf462128eeb0;hpb=ef79bbde537d6b9c745a7d86cb9df1d04c35590d diff --git a/libpcsxcore/psxhw.c b/libpcsxcore/psxhw.c index 9123f76c..c90f8c73 100644 --- a/libpcsxcore/psxhw.c +++ b/libpcsxcore/psxhw.c @@ -24,6 +24,10 @@ #include "psxhw.h" #include "mdec.h" #include "cdrom.h" +#include "gpu.h" + +//#undef PSXHW_LOG +//#define PSXHW_LOG printf void psxHwReset() { if (Config.Sio) psxHu32ref(0x1070) |= SWAP32(0x80); @@ -34,6 +38,7 @@ void psxHwReset() { mdecInit(); // initialize mdec decoder cdrReset(); psxRcntInit(); + HW_GPU_STATUS = 0x14802000; } u8 psxHwRead8(u32 add) { @@ -235,7 +240,10 @@ u32 psxHwRead32(u32 add) { #endif return hard; case 0x1f801814: - hard = GPU_readStatus(); + gpuSyncPluginSR(); + hard = HW_GPU_STATUS; + if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS) + hard |= PSXGPU_LCF & (psxRegs.cycle << 20); #ifdef PSXHW_LOG PSXHW_LOG("GPU STATUS 32bit read %x\n", hard); #endif @@ -423,7 +431,7 @@ void psxHwWrite16(u32 add, u16 value) { #endif if (Config.Sio) psxHu16ref(0x1070) |= SWAPu16(0x80); if (Config.SpuIrq) psxHu16ref(0x1070) |= SWAPu16(0x200); - psxHu16ref(0x1070) &= SWAPu16((psxHu16(0x1074) & value)); + psxHu16ref(0x1070) &= SWAPu16(value); return; case 0x1f801074: @@ -431,6 +439,8 @@ void psxHwWrite16(u32 add, u16 value) { PSXHW_LOG("IMASK 16bit write %x\n", value); #endif psxHu16ref(0x1074) = SWAPu16(value); + if (psxHu16ref(0x1070) & value) + new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1); return; case 0x1f801100: @@ -483,7 +493,7 @@ void psxHwWrite16(u32 add, u16 value) { default: if (add>=0x1f801c00 && add<0x1f801e00) { - SPU_writeRegister(add, value); + SPU_writeRegister(add, value, psxRegs.cycle); return; } @@ -536,13 +546,15 @@ void psxHwWrite32(u32 add, u32 value) { #endif if (Config.Sio) psxHu32ref(0x1070) |= SWAPu32(0x80); if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAPu32(0x200); - psxHu32ref(0x1070) &= SWAPu32((psxHu32(0x1074) & value)); + psxHu32ref(0x1070) &= SWAPu32(value); return; case 0x1f801074: #ifdef PSXHW_LOG PSXHW_LOG("IMASK 32bit write %x\n", value); #endif psxHu32ref(0x1074) = SWAPu32(value); + if (psxHu32ref(0x1070) & value) + new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1); return; #ifdef PSXHW_LOG @@ -654,8 +666,15 @@ void psxHwWrite32(u32 add, u32 value) { PSXHW_LOG("DMA ICR 32bit write %x\n", value); #endif { - u32 tmp = (~value) & SWAPu32(HW_DMA_ICR); - HW_DMA_ICR = SWAPu32(((tmp ^ value) & 0xffffff) ^ tmp); + u32 tmp = value & 0x00ff803f; + tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000; + if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000) + || tmp & HW_DMA_ICR_BUS_ERROR) { + if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT)) + psxHu32ref(0x1070) |= SWAP32(8); + tmp |= HW_DMA_ICR_IRQ_SENT; + } + HW_DMA_ICR = SWAPu32(tmp); return; } @@ -668,7 +687,9 @@ void psxHwWrite32(u32 add, u32 value) { #ifdef PSXHW_LOG PSXHW_LOG("GPU STATUS 32bit write %x\n", value); #endif - GPU_writeStatus(value); return; + GPU_writeStatus(value); + gpuSyncPluginSR(); + return; case 0x1f801820: mdecWrite0(value); break; @@ -724,6 +745,13 @@ void psxHwWrite32(u32 add, u32 value) { psxRcntWtarget(2, value & 0xffff); return; default: + // Dukes of Hazard 2 - car engine noise + if (add>=0x1f801c00 && add<0x1f801e00) { + SPU_writeRegister(add, value&0xffff, psxRegs.cycle); + SPU_writeRegister(add + 2, value>>16, psxRegs.cycle); + return; + } + psxHu32ref(add) = SWAPu32(value); #ifdef PSXHW_LOG PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value); @@ -736,6 +764,6 @@ void psxHwWrite32(u32 add, u32 value) { #endif } -int psxHwFreeze(gzFile f, int Mode) { +int psxHwFreeze(void *f, int Mode) { return 0; }