X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fpsxinterpreter.c;h=02e00a9f16906d80f6c6b94aabd98244df642342;hp=8eb4749de46c7882e62d5be0bd4b471c8ec20b13;hb=9c45ca93727acdf3053a9fefaa1d5773d219133e;hpb=c7a56f4f574167acc7e3751cf04aa9bf9ebba913 diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c index 8eb4749d..02e00a9f 100644 --- a/libpcsxcore/psxinterpreter.c +++ b/libpcsxcore/psxinterpreter.c @@ -25,6 +25,7 @@ #include "r3000a.h" #include "gte.h" #include "psxhle.h" +#include "debug.h" static int branch = 0; static int branch2 = 0; @@ -38,16 +39,75 @@ static u32 branchPC; #define debugI() #endif -inline void execI(); +void execI(); // Subsets void (*psxBSC[64])(); void (*psxSPC[64])(); void (*psxREG[32])(); void (*psxCP0[32])(); -void (*psxCP2[64])(); +void (*psxCP2[64])(struct psxCP2Regs *regs); void (*psxCP2BSC[32])(); +#ifdef ICACHE_EMULATION +/* +Formula One 2001 : +Use old CPU cache code when the RAM location is updated with new code (affects in-game racing) +*/ +static u8* ICache_Addr; +static u8* ICache_Code; +uint32_t *Read_ICache(uint32_t pc) +{ + uint32_t pc_bank, pc_offset, pc_cache; + uint8_t *IAddr, *ICode; + + pc_bank = pc >> 24; + pc_offset = pc & 0xffffff; + pc_cache = pc & 0xfff; + + IAddr = ICache_Addr; + ICode = ICache_Code; + + // cached - RAM + if (pc_bank == 0x80 || pc_bank == 0x00) + { + if (SWAP32(*(uint32_t *)(IAddr + pc_cache)) == pc_offset) + { + // Cache hit - return last opcode used + return (uint32_t *)(ICode + pc_cache); + } + else + { + // Cache miss - addresses don't match + // - default: 0xffffffff (not init) + + // cache line is 4 bytes wide + pc_offset &= ~0xf; + pc_cache &= ~0xf; + + // address line + *(uint32_t *)(IAddr + pc_cache + 0x0) = SWAP32(pc_offset + 0x0); + *(uint32_t *)(IAddr + pc_cache + 0x4) = SWAP32(pc_offset + 0x4); + *(uint32_t *)(IAddr + pc_cache + 0x8) = SWAP32(pc_offset + 0x8); + *(uint32_t *)(IAddr + pc_cache + 0xc) = SWAP32(pc_offset + 0xc); + + // opcode line + pc_offset = pc & ~0xf; + *(uint32_t *)(ICode + pc_cache + 0x0) = psxMu32ref(pc_offset + 0x0); + *(uint32_t *)(ICode + pc_cache + 0x4) = psxMu32ref(pc_offset + 0x4); + *(uint32_t *)(ICode + pc_cache + 0x8) = psxMu32ref(pc_offset + 0x8); + *(uint32_t *)(ICode + pc_cache + 0xc) = psxMu32ref(pc_offset + 0xc); + } + } + + /* + TODO: Probably should add cached BIOS + */ + // default + return (uint32_t *)PSXM(pc); +} +#endif + static void delayRead(int reg, u32 bpc) { u32 rold, rnew; @@ -265,7 +325,17 @@ void psxDelayTest(int reg, u32 bpc) { u32 *code; u32 tmp; - code = (u32 *)PSXM(bpc); + #ifdef ICACHE_EMULATION + if (Config.icache_emulation) + { + code = Read_ICache(psxRegs.pc); + } + else + #endif + { + code = (u32 *)PSXM(psxRegs.pc); + } + tmp = ((code == NULL) ? 0 : SWAP32(*code)); branch = 1; @@ -289,7 +359,16 @@ static u32 psxBranchNoDelay(void) { u32 *code; u32 temp; - code = (u32 *)PSXM(psxRegs.pc); + #ifdef ICACHE_EMULATION + if (Config.icache_emulation) + { + code = Read_ICache(psxRegs.pc); + } + else + #endif + { + code = (u32 *)PSXM(psxRegs.pc); + } psxRegs.code = ((code == NULL) ? 0 : SWAP32(*code)); switch (_Op_) { case 0x00: // SPECIAL @@ -407,7 +486,7 @@ static int psxDelayBranchTest(u32 tar1) { return psxDelayBranchExec(tmp2); } -__inline void doBranch(u32 tar) { +static void doBranch(u32 tar) { u32 *code; u32 tmp; @@ -418,7 +497,16 @@ __inline void doBranch(u32 tar) { if (psxDelayBranchTest(tar)) return; - code = (u32 *)PSXM(psxRegs.pc); + #ifdef ICACHE_EMULATION + if (Config.icache_emulation) + { + code = Read_ICache(psxRegs.pc); + } + else + #endif + { + code = (u32 *)PSXM(psxRegs.pc); + } psxRegs.code = ((code == NULL) ? 0 : SWAP32(*code)); debugI(); @@ -500,14 +588,27 @@ void psxSLTU() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) < _u32(_rRt_); } // Rd * Format: OP rs, rt * *********************************************************/ void psxDIV() { - if (_i32(_rRt_) != 0) { - _i32(_rLo_) = _i32(_rRs_) / _i32(_rRt_); - _i32(_rHi_) = _i32(_rRs_) % _i32(_rRt_); - } - else { - _i32(_rLo_) = _i32(_rRs_) >= 0 ? 0xffffffff : 1; - _i32(_rHi_) = _i32(_rRs_); - } + if (!_i32(_rRt_)) { + _i32(_rHi_) = _i32(_rRs_); + if (_i32(_rRs_) & 0x80000000) { + _i32(_rLo_) = 1; + } else { + _i32(_rLo_) = 0xFFFFFFFF; + } +/* + * Notaz said that this was "not needed" for ARM platforms and could slow it down so let's disable for ARM. + * This fixes a crash issue that can happen when running Amidog's CPU test. + * (It still stays stuck to a black screen but at least it doesn't crash anymore) + */ +#if !defined(__arm__) && !defined(__aarch64__) + } else if (_i32(_rRs_) == 0x80000000 && _i32(_rRt_) == 0xFFFFFFFF) { + _i32(_rLo_) = 0x80000000; + _i32(_rHi_) = 0; +#endif + } else { + _i32(_rLo_) = _i32(_rRs_) / _i32(_rRt_); + _i32(_rHi_) = _i32(_rRs_) % _i32(_rRt_); + } } void psxDIVU() { @@ -540,7 +641,7 @@ void psxMULTU() { * Format: OP rs, offset * *********************************************************/ #define RepZBranchi32(op) if(_i32(_rRs_) op 0) doBranch(_BranchTarget_); -#define RepZBranchLinki32(op) if(_i32(_rRs_) op 0) { _SetLink(31); doBranch(_BranchTarget_); } +#define RepZBranchLinki32(op) { _SetLink(31); if(_i32(_rRs_) op 0) { doBranch(_BranchTarget_); } } void psxBGEZ() { RepZBranchi32(>=) } // Branch if Rs >= 0 void psxBGEZAL() { RepZBranchLinki32(>=) } // Branch if Rs >= 0 and link @@ -561,9 +662,9 @@ void psxSRL() { if (!_Rd_) return; _u32(_rRd_) = _u32(_rRt_) >> _Sa_; } // Rd = * Shift arithmetic with variant register shift * * Format: OP rd, rt, rs * *********************************************************/ -void psxSLLV() { if (!_Rd_) return; _u32(_rRd_) = _u32(_rRt_) << _u32(_rRs_); } // Rd = Rt << rs -void psxSRAV() { if (!_Rd_) return; _i32(_rRd_) = _i32(_rRt_) >> _u32(_rRs_); } // Rd = Rt >> rs (arithmetic) -void psxSRLV() { if (!_Rd_) return; _u32(_rRd_) = _u32(_rRt_) >> _u32(_rRs_); } // Rd = Rt >> rs (logical) +void psxSLLV() { if (!_Rd_) return; _u32(_rRd_) = _u32(_rRt_) << (_u32(_rRs_) & 0x1F); } // Rd = Rt << rs +void psxSRAV() { if (!_Rd_) return; _i32(_rRd_) = _i32(_rRt_) >> (_u32(_rRs_) & 0x1F); } // Rd = Rt >> rs (arithmetic) +void psxSRLV() { if (!_Rd_) return; _u32(_rRd_) = _u32(_rRt_) >> (_u32(_rRs_) & 0x1F); } // Rd = Rt >> rs (logical) /********************************************************* * Load higher 16 bits of the first word in GPR with imm * @@ -590,7 +691,8 @@ void psxMTLO() { _rLo_ = _rRs_; } // Lo = Rs * Format: OP * *********************************************************/ void psxBREAK() { - // Break exception - psx rom doens't handles this + psxRegs.pc -= 4; + psxException(0x24, branch); } void psxSYSCALL() { @@ -602,6 +704,7 @@ void psxRFE() { // SysPrintf("psxRFE\n"); psxRegs.CP0.n.Status = (psxRegs.CP0.n.Status & 0xfffffff0) | ((psxRegs.CP0.n.Status & 0x3c) >> 2); + psxTestSWInts(); } /********************************************************* @@ -625,14 +728,14 @@ void psxJAL() { _SetLink(31); doBranch(_JumpTarget_); } * Format: OP rs, rd * *********************************************************/ void psxJR() { - doBranch(_u32(_rRs_)); + doBranch(_rRs_ & ~3); psxJumpTest(); } void psxJALR() { u32 temp = _u32(_rRs_); if (_Rd_) { _SetLink(_Rd_); } - doBranch(temp); + doBranch(temp & ~3); } /********************************************************* @@ -726,9 +829,9 @@ void psxLWR() { */ } -void psxSB() { psxMemWrite8 (_oB_, _u8 (_rRt_)); } -void psxSH() { psxMemWrite16(_oB_, _u16(_rRt_)); } -void psxSW() { psxMemWrite32(_oB_, _u32(_rRt_)); } +void psxSB() { psxMemWrite8 (_oB_, _rRt_ & 0xff); } +void psxSH() { psxMemWrite16(_oB_, _rRt_ & 0xffff); } +void psxSW() { psxMemWrite32(_oB_, _rRt_); } u32 SWL_MASK[4] = { 0xffffff00, 0xffff0000, 0xff000000, 0 }; u32 SWL_SHIFT[4] = { 24, 16, 8, 0 }; @@ -779,15 +882,14 @@ void psxMFC0() { if (!_Rt_) return; _i32(_rRt_) = (int)_rFs_; } void psxCFC0() { if (!_Rt_) return; _i32(_rRt_) = (int)_rFs_; } void psxTestSWInts() { - // the next code is untested, if u know please - // tell me if it works ok or not (linuzappz) if (psxRegs.CP0.n.Cause & psxRegs.CP0.n.Status & 0x0300 && - psxRegs.CP0.n.Status & 0x1) { + psxRegs.CP0.n.Status & 0x1) { + psxRegs.CP0.n.Cause &= ~0x7c; psxException(psxRegs.CP0.n.Cause, branch); } } -__inline void MTC0(int reg, u32 val) { +void MTC0(int reg, u32 val) { // SysPrintf("MTC0 %d: %x\n", reg, val); switch (reg) { case 12: // Status @@ -796,7 +898,8 @@ __inline void MTC0(int reg, u32 val) { break; case 13: // Cause - psxRegs.CP0.n.Cause = val & ~(0xfc00); + psxRegs.CP0.n.Cause &= ~0x0300; + psxRegs.CP0.n.Cause |= val & 0x0300; psxTestSWInts(); break; @@ -832,16 +935,22 @@ void psxCOP0() { } void psxCOP2() { - psxCP2[_Funct_](); + psxCP2[_Funct_]((struct psxCP2Regs *)&psxRegs.CP2D); } -void psxBASIC() { +void psxBASIC(struct psxCP2Regs *regs) { psxCP2BSC[_Rs_](); } void psxHLE() { // psxHLEt[psxRegs.code & 0xffff](); - psxHLEt[psxRegs.code & 0x07](); // HDHOSHY experimental patch +// psxHLEt[psxRegs.code & 0x07](); // HDHOSHY experimental patch + uint32_t hleCode = psxRegs.code & 0x03ffffff; + if (hleCode >= (sizeof(psxHLEt) / sizeof(psxHLEt[0]))) { + psxNULL(); + } else { + psxHLEt[hleCode](); + } } void (*psxBSC[64])() = { @@ -881,7 +990,7 @@ void (*psxCP0[32])() = { psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL }; -void (*psxCP2[64])() = { +void (*psxCP2[64])(struct psxCP2Regs *regs) = { psxBASIC, gteRTPS , psxNULL , psxNULL, psxNULL, psxNULL , gteNCLIP, psxNULL, // 00 psxNULL , psxNULL , psxNULL , psxNULL, gteOP , psxNULL , psxNULL , psxNULL, // 08 gteDPCS , gteINTPL, gteMVMVA, gteNCDS, gteCDP , psxNULL , gteNCDT , psxNULL, // 10 @@ -903,10 +1012,38 @@ void (*psxCP2BSC[32])() = { /////////////////////////////////////////// static int intInit() { + #ifdef ICACHE_EMULATION + /* We have to allocate the icache memory even if + * the user has not enabled it as otherwise it can cause issues. + */ + if (!ICache_Addr) + { + ICache_Addr = malloc(0x1000); + if (!ICache_Addr) + { + return -1; + } + } + + if (!ICache_Code) + { + ICache_Code = malloc(0x1000); + if (!ICache_Code) + { + return -1; + } + } + memset(ICache_Addr, 0xff, 0x1000); + memset(ICache_Code, 0xff, 0x1000); + #endif return 0; } static void intReset() { + #ifdef ICACHE_EMULATION + memset(ICache_Addr, 0xff, 0x1000); + memset(ICache_Code, 0xff, 0x1000); + #endif } void intExecute() { @@ -923,12 +1060,46 @@ void intExecuteBlock() { static void intClear(u32 Addr, u32 Size) { } +void intNotify (int note, void *data) { + #ifdef ICACHE_EMULATION + /* Gameblabla - Only clear the icache if it's isolated */ + if (note == R3000ACPU_NOTIFY_CACHE_ISOLATED) + { + memset(ICache_Addr, 0xff, 0x1000); + memset(ICache_Code, 0xff, 0x1000); + } + #endif +} + static void intShutdown() { + #ifdef ICACHE_EMULATION + if (ICache_Addr) + { + free(ICache_Addr); + ICache_Addr = NULL; + } + + if (ICache_Code) + { + free(ICache_Code); + ICache_Code = NULL; + } + #endif } // interpreter execution -inline void execI() { - u32 *code = (u32 *)PSXM(psxRegs.pc); +void execI() { + u32 *code; + #ifdef ICACHE_EMULATION + if (Config.icache_emulation) + { + code = Read_ICache(psxRegs.pc); + } + else + #endif + { + code = (u32 *)PSXM(psxRegs.pc); + } psxRegs.code = ((code == NULL) ? 0 : SWAP32(*code)); debugI(); @@ -947,5 +1118,8 @@ R3000Acpu psxInt = { intExecute, intExecuteBlock, intClear, +#ifdef ICACHE_EMULATION + intNotify, +#endif intShutdown };