X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fr3000a.c;h=82eb88578534c9a3411eb5806b655aacb7cae03b;hp=b5fe3bd16b167af5c1c249f3e32febcb9fa38ebd;hb=HEAD;hpb=dc4fa8bcd7d8fb9ccd6c742a350f69e0683350e0

diff --git a/libpcsxcore/r3000a.c b/libpcsxcore/r3000a.c
index b5fe3bd1..0c29dba7 100644
--- a/libpcsxcore/r3000a.c
+++ b/libpcsxcore/r3000a.c
@@ -26,6 +26,8 @@
 #include "mdec.h"
 #include "gte.h"
 #include "psxinterpreter.h"
+#include "psxbios.h"
+#include "psxevents.h"
 #include "../include/compiler_features.h"
 
 R3000Acpu *psxCpu = NULL;
@@ -34,8 +36,6 @@ psxRegisters psxRegs;
 #endif
 
 int psxInit() {
-	SysPrintf(_("Running PCSX Version %s (%s).\n"), PCSX_VERSION, __DATE__);
-
 #ifndef DRC_DISABLE
 	if (Config.Cpu == CPU_INTERPRETER) {
 		psxCpu = &psxInt;
@@ -53,6 +53,7 @@ int psxInit() {
 }
 
 void psxReset() {
+	boolean introBypassed = FALSE;
 	psxMemReset();
 
 	memset(&psxRegs, 0, sizeof(psxRegs));
@@ -61,8 +62,10 @@ void psxReset() {
 
 	psxRegs.CP0.n.SR   = 0x10600000; // COP0 enabled | BEV = 1 | TS = 1
 	psxRegs.CP0.n.PRid = 0x00000002; // PRevID = Revision ID, same as R3000A
-	if (Config.HLE)
-		psxRegs.CP0.n.SR |= 1u << 30; // COP2 enabled
+	if (Config.HLE) {
+		psxRegs.CP0.n.SR |= 1u << 30;    // COP2 enabled
+		psxRegs.CP0.n.SR &= ~(1u << 22); // RAM exception vector
+	}
 
 	psxCpu->ApplyConfig();
 	psxCpu->Reset();
@@ -70,13 +73,14 @@ void psxReset() {
 	psxHwReset();
 	psxBiosInit();
 
-	BiosLikeGPUSetup(); // a bit of a hack but whatever
-
 	if (!Config.HLE) {
 		psxExecuteBios();
-		if (psxRegs.pc == 0x80030000 && !Config.SlowBoot)
-			BiosBootBypass();
+		if (psxRegs.pc == 0x80030000 && !Config.SlowBoot) {
+			introBypassed = BiosBootBypass();
+		}
 	}
+	if (Config.HLE || introBypassed)
+		psxBiosSetupBootState();
 
 #ifdef EMU_LOG
 	EMU_LOG("*BIOS END*\n");
@@ -107,7 +111,7 @@ void psxException(u32 cause, enum R3000Abdt bdt, psxCP0Regs *cp0) {
 	}
 
 	// Set the Cause
-	cp0->n.Cause = (bdt << 30) | (cp0->n.Cause & 0x300) | cause;
+	cp0->n.Cause = (bdt << 30) | (cp0->n.Cause & 0x700) | cause;
 
 	// Set the EPC & PC
 	cp0->n.EPC = bdt ? psxRegs.pc - 4 : psxRegs.pc;
@@ -125,84 +129,10 @@ void psxBranchTest() {
 	if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
 		psxRcntUpdate();
 
-	if (psxRegs.interrupt) {
-		if ((psxRegs.interrupt & (1 << PSXINT_SIO))) { // sio
-			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) {
-				psxRegs.interrupt &= ~(1 << PSXINT_SIO);
-				sioInterrupt();
-			}
-		}
-		if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr
-			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) {
-				psxRegs.interrupt &= ~(1 << PSXINT_CDR);
-				cdrInterrupt();
-			}
-		}
-		if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read
-			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) {
-				psxRegs.interrupt &= ~(1 << PSXINT_CDREAD);
-				cdrPlayReadInterrupt();
-			}
-		}
-		if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma
-			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) {
-				psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA);
-				gpuInterrupt();
-			}
-		}
-		if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma
-			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) {
-				psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA);
-				mdec1Interrupt();
-			}
-		}
-		if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma
-			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) {
-				psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA);
-				spuInterrupt();
-			}
-		}
-		if (psxRegs.interrupt & (1 << PSXINT_MDECINDMA)) { // mdec in
-			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECINDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECINDMA].cycle) {
-				psxRegs.interrupt &= ~(1 << PSXINT_MDECINDMA);
-				mdec0Interrupt();
-			}
-		}
-		if (psxRegs.interrupt & (1 << PSXINT_GPUOTCDMA)) { // gpu otc
-			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle) {
-				psxRegs.interrupt &= ~(1 << PSXINT_GPUOTCDMA);
-				gpuotcInterrupt();
-			}
-		}
-		if (psxRegs.interrupt & (1 << PSXINT_CDRDMA)) { // cdrom
-			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDMA].sCycle) >= psxRegs.intCycle[PSXINT_CDRDMA].cycle) {
-				psxRegs.interrupt &= ~(1 << PSXINT_CDRDMA);
-				cdrDmaInterrupt();
-			}
-		}
-		if (psxRegs.interrupt & (1 << PSXINT_CDRLID)) { // cdr lid states
-			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRLID].sCycle) >= psxRegs.intCycle[PSXINT_CDRLID].cycle) {
-				psxRegs.interrupt &= ~(1 << PSXINT_CDRLID);
-				cdrLidSeekInterrupt();
-			}
-		}
-		if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update
-			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) {
-				psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE);
-				spuUpdate();
-			}
-		}
-	}
+	irq_test(&psxRegs.CP0);
 
-	if (psxHu32(0x1070) & psxHu32(0x1074)) {
-		if ((psxRegs.CP0.n.SR & 0x401) == 0x401) {
-#ifdef PSXCPU_LOG
-			PSXCPU_LOG("Interrupt: %x %x\n", psxHu32(0x1070), psxHu32(0x1074));
-#endif
-//			SysPrintf("Interrupt (%x): %x %x\n", psxRegs.cycle, psxHu32(0x1070), psxHu32(0x1074));
-			psxException(0x400, 0, &psxRegs.CP0);
-		}
-	}
+	if (unlikely(psxRegs.pc == psxRegs.biosBranchCheck))
+		psxBiosCheckBranch();
 }
 
 void psxJumpTest() {
@@ -247,3 +177,45 @@ void psxExecuteBios() {
 		SysPrintf("non-standard BIOS detected (%d, %08x)\n", i, psxRegs.pc);
 }
 
+// irq10 stuff, very preliminary
+static int irq10count;
+
+static void psxScheduleIrq10One(u32 cycles_abs) {
+	// schedule relative to frame start
+	u32 c = cycles_abs - rcnts[3].cycleStart;
+	assert((s32)c >= 0);
+	psxRegs.interrupt |= 1 << PSXINT_IRQ10;
+	psxRegs.intCycle[PSXINT_IRQ10].cycle = c;
+	psxRegs.intCycle[PSXINT_IRQ10].sCycle = rcnts[3].cycleStart;
+	set_event_raw_abs(PSXINT_IRQ10, cycles_abs);
+}
+
+void irq10Interrupt() {
+	u32 prevc = psxRegs.intCycle[PSXINT_IRQ10].sCycle
+		+ psxRegs.intCycle[PSXINT_IRQ10].cycle;
+
+	psxHu32ref(0x1070) |= SWAPu32(0x400);
+
+#if 0
+	s32 framec = psxRegs.cycle - rcnts[3].cycleStart;
+	printf("%d:%03d irq10 #%d %3d m=%d,%d\n", frame_counter,
+		(s32)((float)framec / (PSXCLK / 60 / 263.0f)),
+		irq10count, psxRegs.cycle - prevc,
+		(psxRegs.CP0.n.SR & 0x401) != 0x401, !(psxHu32(0x1074) & 0x400));
+#endif
+	if (--irq10count > 0) {
+		u32 cycles_per_line = Config.PsxType
+			? PSXCLK / 50 / 314 : PSXCLK / 60 / 263;
+		psxScheduleIrq10One(prevc + cycles_per_line);
+	}
+}
+
+void psxScheduleIrq10(int irq_count, int x_cycles, int y) {
+	//printf("%s %d, %d, %d\n", __func__, irq_count, x_cycles, y);
+	u32 cycles_per_frame = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
+	u32 cycles = rcnts[3].cycleStart + cycles_per_frame;
+	cycles += y * cycles_per_frame / (Config.PsxType ? 314 : 263);
+	cycles += x_cycles;
+	psxScheduleIrq10One(cycles);
+	irq10count = irq_count;
+}