X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=plugins%2Fgpu_neon%2Fgpu.c;h=02dd37210cc8e54cce8ae789606d709b9a3982f9;hp=f905f0ad8a8105e0174e632f2232a8d5c29f30ac;hb=69b09c0d33efd71ebe4886cfae41c162803683d5;hpb=1ab64c5413f79cc38f9b17520df69a4e01041046

diff --git a/plugins/gpu_neon/gpu.c b/plugins/gpu_neon/gpu.c
index f905f0ad..02dd3721 100644
--- a/plugins/gpu_neon/gpu.c
+++ b/plugins/gpu_neon/gpu.c
@@ -8,62 +8,119 @@
  * See the COPYING file in the top-level directory.
  */
 
-#include <stdint.h>
+#include <stdio.h>
 #include <string.h>
+#include "gpu.h"
 
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#define unlikely(x) __builtin_expect((x), 0)
+#define noinline __attribute__((noinline))
 
-static struct {
-  uint16_t vram[1024 * 512];
-  uint16_t guard[1024 * 512]; // overdraw guard
-  uint32_t regs[16];
-  union {
-    uint32_t reg;
-    struct {
-      uint32_t tx:4;    //  0 texture page
-      uint32_t ty:1;
-      uint32_t abr:2;
-      uint32_t tp:2;    //  7 t.p. mode (4,8,15bpp)
-      uint32_t dtd:1;   //  9 dither
-      uint32_t dfe:1;
-      uint32_t md:1;    // 11 set mask bit when drawing
-      uint32_t me:1;    // 12 no draw on mask
-      uint32_t unkn:3;
-      uint32_t width1:1;// 16
-      uint32_t width0:2;
-      uint32_t height:1;
-      uint32_t video:1; // 20 NTSC,PAL
-      uint32_t rgb24:1;
-      uint32_t inter:1; // 22 interlace on
-      uint32_t den:1;   // 23 display not enabled
-      uint32_t unkn2:2;
-      uint32_t busy:1;  // 26 !busy drawing
-      uint32_t img:1;   // 27 ready to DMA
-      uint32_t com:1;   // 28 ready for commands
-      uint32_t dma:2;   // 29 off, ?, to vram, from vram
-      uint32_t lcf:1;   // 21 odd frame/blanking?
-    };
-  } status;
-  struct {
-    int x, y, w, h;
-    int y1, y2;
-  } screen;
-  uint32_t blanking;
-} gpu;
+#define gpu_log(fmt, ...) \
+  printf("%d:%03d: " fmt, *gpu.state.frame_count, *gpu.state.hcnt, ##__VA_ARGS__)
 
-long GPUinit(void)
+//#define log_io gpu_log
+#define log_io(...)
+//#define log_anomaly gpu_log
+#define log_anomaly(...)
+
+struct psx_gpu gpu __attribute__((aligned(2048)));
+
+static noinline void do_reset(void)
 {
-  return 0;
+  memset(gpu.regs, 0, sizeof(gpu.regs));
+  gpu.status.reg = 0x14802000;
+  gpu.gp0 = 0;
+  gpu.regs[3] = 1;
+  gpu.screen.hres = gpu.screen.w = 256;
+  gpu.screen.vres = gpu.screen.h = 240;
 }
 
-long GPUshutdown(void)
+static noinline void update_width(void)
 {
-  return 0;
+  int sw = gpu.screen.x2 - gpu.screen.x1;
+  if (sw <= 0 || sw >= 2560)
+    // full width
+    gpu.screen.w = gpu.screen.hres;
+  else
+    gpu.screen.w = sw * gpu.screen.hres / 2560;
 }
 
-uint32_t GPUreadStatus(void)
+static noinline void update_height(void)
+{
+  int sh = gpu.screen.y2 - gpu.screen.y1;
+  if (gpu.status.dheight)
+    sh *= 2;
+  if (sh <= 0)
+    sh = gpu.screen.vres;
+
+  gpu.screen.h = sh;
+}
+
+static noinline void decide_frameskip(void)
 {
-  return gpu.status.reg | (gpu.blanking << 31);
+  if (gpu.frameskip.active)
+    gpu.frameskip.cnt++;
+  else {
+    gpu.frameskip.cnt = 0;
+    gpu.frameskip.frame_ready = 1;
+  }
+
+  if (!gpu.frameskip.active && *gpu.frameskip.advice)
+    gpu.frameskip.active = 1;
+  else if (gpu.frameskip.set > 0 && gpu.frameskip.cnt < gpu.frameskip.set)
+    gpu.frameskip.active = 1;
+  else
+    gpu.frameskip.active = 0;
+}
+
+static noinline void decide_frameskip_allow(uint32_t cmd_e3)
+{
+  // no frameskip if it decides to draw to display area,
+  // but not for interlace since it'll most likely always do that
+  uint32_t x = cmd_e3 & 0x3ff;
+  uint32_t y = (cmd_e3 >> 10) & 0x3ff;
+  gpu.frameskip.allow = gpu.status.interlace ||
+    (uint32_t)(x - gpu.screen.x) >= (uint32_t)gpu.screen.w ||
+    (uint32_t)(y - gpu.screen.y) >= (uint32_t)gpu.screen.h;
+}
+
+static noinline void get_gpu_info(uint32_t data)
+{
+  switch (data & 0x0f) {
+    case 0x02:
+    case 0x03:
+    case 0x04:
+    case 0x05:
+      gpu.gp0 = gpu.ex_regs[data & 7] & 0xfffff;
+      break;
+    case 0x06:
+      gpu.gp0 = gpu.ex_regs[5] & 0xfffff;
+      break;
+    case 0x07:
+      gpu.gp0 = 2;
+      break;
+    default:
+      gpu.gp0 = 0;
+      break;
+  }
+}
+
+long GPUinit(void)
+{
+  int ret;
+  ret  = vout_init();
+  ret |= renderer_init();
+
+  gpu.state.frame_count = &gpu.zero;
+  gpu.state.hcnt = &gpu.zero;
+  do_reset();
+  return ret;
+}
+
+long GPUshutdown(void)
+{
+  return vout_finish();
 }
 
 void GPUwriteStatus(uint32_t data)
@@ -72,11 +129,20 @@ void GPUwriteStatus(uint32_t data)
   static const short vres[4] = { 240, 480, 256, 480 };
   uint32_t cmd = data >> 24;
 
-  switch (data >> 24) {
+  if (cmd < ARRAY_SIZE(gpu.regs)) {
+    if (cmd != 0 && cmd != 5 && gpu.regs[cmd] == data)
+      return;
+    gpu.regs[cmd] = data;
+  }
+
+  gpu.state.fb_dirty = 1;
+
+  switch (cmd) {
     case 0x00:
+      do_reset();
       break;
     case 0x03:
-      gpu.status.den = data & 1;
+      gpu.status.blanking = data & 1;
       break;
     case 0x04:
       gpu.status.dma = data & 3;
@@ -84,159 +150,391 @@ void GPUwriteStatus(uint32_t data)
     case 0x05:
       gpu.screen.x = data & 0x3ff;
       gpu.screen.y = (data >> 10) & 0x3ff;
+      if (gpu.frameskip.set) {
+        decide_frameskip_allow(gpu.ex_regs[3]);
+        if (gpu.frameskip.last_flip_frame != *gpu.state.frame_count) {
+          decide_frameskip();
+          gpu.frameskip.last_flip_frame = *gpu.state.frame_count;
+        }
+      }
+      break;
+    case 0x06:
+      gpu.screen.x1 = data & 0xfff;
+      gpu.screen.x2 = (data >> 12) & 0xfff;
+      update_width();
       break;
     case 0x07:
       gpu.screen.y1 = data & 0x3ff;
       gpu.screen.y2 = (data >> 10) & 0x3ff;
+      update_height();
       break;
     case 0x08:
       gpu.status.reg = (gpu.status.reg & ~0x7f0000) | ((data & 0x3F) << 17) | ((data & 0x40) << 10);
-      gpu.screen.w = hres[(gpu.status.reg >> 16) & 7];
-      gpu.screen.h = vres[(gpu.status.reg >> 19) & 3];
+      gpu.screen.hres = hres[(gpu.status.reg >> 16) & 7];
+      gpu.screen.vres = vres[(gpu.status.reg >> 19) & 3];
+      update_width();
+      update_height();
+      break;
+    default:
+      if ((cmd & 0xf0) == 0x10)
+        get_gpu_info(data);
       break;
   }
-
-  if (cmd < ARRAY_SIZE(gpu.regs))
-    gpu.regs[cmd] = data;
 }
 
-void GPUreadDataMem(uint32_t *mem, int count)
+const unsigned char cmd_lengths[256] =
 {
-}
-
-uint32_t GPUreadData(void)
+	0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	3, 3, 3, 3, 6, 6, 6, 6, 4, 4, 4, 4, 8, 8, 8, 8, // 20
+	5, 5, 5, 5, 8, 8, 8, 8, 7, 7, 7, 7, 11, 11, 11, 11,
+	2, 2, 2, 2, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, // 40
+	3, 3, 3, 3, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4, 4,
+	2, 2, 2, 2, 3, 3, 3, 3, 1, 1, 1, 1, 2, 2, 2, 2, // 60
+	1, 1, 1, 1, 2, 2, 2, 2, 1, 1, 1, 1, 2, 2, 2, 2,
+	3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 80
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // a0
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // c0
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // e0
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+#define VRAM_MEM_XY(x, y) &gpu.vram[(y) * 1024 + (x)]
+
+static inline void do_vram_line(int x, int y, uint16_t *mem, int l, int is_read)
 {
-  return 0;
+  uint16_t *vram = VRAM_MEM_XY(x, y);
+  if (is_read)
+    memcpy(mem, vram, l * 2);
+  else
+    memcpy(vram, mem, l * 2);
 }
 
-void GPUwriteDataMem(uint32_t *mem, int count)
+static int do_vram_io(uint32_t *data, int count, int is_read)
 {
-}
+  int count_initial = count;
+  uint16_t *sdata = (uint16_t *)data;
+  int x = gpu.dma.x, y = gpu.dma.y;
+  int w = gpu.dma.w, h = gpu.dma.h;
+  int o = gpu.dma.offset;
+  int l;
+  count *= 2; // operate in 16bpp pixels
+
+  if (gpu.dma.offset) {
+    l = w - gpu.dma.offset;
+    if (count < l)
+      l = count;
+
+    do_vram_line(x + o, y, sdata, l, is_read);
+
+    if (o + l < w)
+      o += l;
+    else {
+      o = 0;
+      y++;
+      h--;
+    }
+    sdata += l;
+    count -= l;
+  }
 
-void GPUwriteData(uint32_t gdata)
-{
+  for (; h > 0 && count >= w; sdata += w, count -= w, y++, h--) {
+    y &= 511;
+    do_vram_line(x, y, sdata, w, is_read);
+  }
+
+  if (h > 0 && count > 0) {
+    y &= 511;
+    do_vram_line(x, y, sdata, count, is_read);
+    o = count;
+    count = 0;
+  }
+  gpu.dma.y = y;
+  gpu.dma.h = h;
+  gpu.dma.offset = o;
+
+  return count_initial - count / 2;
 }
 
-long GPUdmaChain(uint32_t *base, uint32_t addr)
+static void start_vram_transfer(uint32_t pos_word, uint32_t size_word, int is_read)
 {
-  return 0;
+  if (gpu.dma.h)
+    log_anomaly("start_vram_transfer while old unfinished\n");
+
+  gpu.dma.x = pos_word & 1023;
+  gpu.dma.y = (pos_word >> 16) & 511;
+  gpu.dma.w = size_word & 0xffff; // ?
+  gpu.dma.h = size_word >> 16;
+  gpu.dma.offset = 0;
+
+  renderer_flush_queues();
+  if (is_read) {
+    gpu.status.img = 1;
+    // XXX: wrong for width 1
+    memcpy(&gpu.gp0, VRAM_MEM_XY(gpu.dma.x, gpu.dma.y), 4);
+  }
+  else {
+    renderer_invalidate_caches(gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h);
+  }
+
+  log_io("start_vram_transfer %c (%d, %d) %dx%d\n", is_read ? 'r' : 'w',
+    gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h);
 }
 
-typedef struct GPUFREEZETAG
+static int check_cmd(uint32_t *data, int count)
 {
-  uint32_t ulFreezeVersion;      // should be always 1 for now (set by main emu)
-  uint32_t ulStatus;             // current gpu status
-  uint32_t ulControl[256];       // latest control register values
-  unsigned char psxVRam[1024*1024*2]; // current VRam image (full 2 MB for ZN)
-} GPUFreeze_t;
+  int len, cmd, start, pos;
+  int vram_dirty = 0;
 
-long GPUfreeze(uint32_t type, GPUFreeze_t *freeze)
-{
-  switch (type) {
-    case 1: // save
-      memcpy(freeze->psxVRam, gpu.vram, sizeof(gpu.vram));
-      memcpy(freeze->ulControl, gpu.regs, sizeof(gpu.regs));
-      freeze->ulStatus = gpu.status.reg;
-      freeze->ulControl[255] = gpu.blanking; // abuse free space
-      break;
-    case 0: // load
-      memcpy(gpu.vram, freeze->psxVRam, sizeof(gpu.vram));
-      memcpy(gpu.regs, freeze->ulControl, sizeof(gpu.regs));
-      gpu.status.reg = freeze->ulStatus;
-      gpu.blanking = freeze->ulControl[255];
-      GPUwriteStatus((5 << 24) | gpu.regs[5]);
-      GPUwriteStatus((7 << 24) | gpu.regs[7]);
-      GPUwriteStatus((8 << 24) | gpu.regs[8]);
+  // process buffer
+  for (start = pos = 0; pos < count; )
+  {
+    cmd = -1;
+    len = 0;
+
+    if (gpu.dma.h) {
+      pos += do_vram_io(data + pos, count - pos, 0);
+      if (pos == count)
+        break;
+      start = pos;
+    }
+
+    // do look-ahead pass to detect SR changes and VRAM i/o
+    while (pos < count) {
+      uint32_t *list = data + pos;
+      cmd = list[0] >> 24;
+      len = 1 + cmd_lengths[cmd];
+
+      //printf("  %3d: %02x %d\n", pos, cmd, len);
+      if ((cmd & 0xf4) == 0x24) {
+        // flat textured prim
+        gpu.ex_regs[1] &= ~0x1ff;
+        gpu.ex_regs[1] |= list[4] & 0x1ff;
+      }
+      else if ((cmd & 0xf4) == 0x34) {
+        // shaded textured prim
+        gpu.ex_regs[1] &= ~0x1ff;
+        gpu.ex_regs[1] |= list[5] & 0x1ff;
+      }
+      else if (cmd == 0xe3)
+        decide_frameskip_allow(list[0]);
+
+      if (2 <= cmd && cmd < 0xc0)
+        vram_dirty = 1;
+      else if ((cmd & 0xf8) == 0xe0)
+        gpu.ex_regs[cmd & 7] = list[0];
+
+      if (pos + len > count) {
+        cmd = -1;
+        break; // incomplete cmd
+      }
+      if (cmd == 0xa0 || cmd == 0xc0)
+        break; // image i/o
+      pos += len;
+    }
+
+    if (pos - start > 0) {
+      if (!gpu.frameskip.active || !gpu.frameskip.allow)
+        do_cmd_list(data + start, pos - start);
+      start = pos;
+    }
+
+    if (cmd == 0xa0 || cmd == 0xc0) {
+      // consume vram write/read cmd
+      start_vram_transfer(data[pos + 1], data[pos + 2], cmd == 0xc0);
+      pos += len;
+    }
+    else if (cmd == -1)
       break;
   }
 
-  return 1;
+  gpu.status.reg &= ~0x1fff;
+  gpu.status.reg |= gpu.ex_regs[1] & 0x7ff;
+  gpu.status.reg |= (gpu.ex_regs[6] & 3) << 11;
+
+  if (gpu.frameskip.active)
+    renderer_sync_ecmds(gpu.ex_regs);
+  gpu.state.fb_dirty |= vram_dirty;
+
+  return count - pos;
 }
 
-void GPUvBlank(int val)
+void flush_cmd_buffer(void)
 {
-  gpu.blanking = !!val;
+  int left = check_cmd(gpu.cmd_buffer, gpu.cmd_len);
+  if (left > 0)
+    memmove(gpu.cmd_buffer, gpu.cmd_buffer + gpu.cmd_len - left, left * 4);
+  gpu.cmd_len = left;
 }
 
-// rearmed specific
-
-#include "../../frontend/plugin_lib.h"
-#include "../../frontend/arm_utils.h"
-
-static const struct rearmed_cbs *cbs;
-static void *screen_buf;
-
-static void blit(void)
+void GPUwriteDataMem(uint32_t *mem, int count)
 {
-  static uint32_t old_status, old_h;
-  int x = gpu.screen.x & ~3; // alignment needed by blitter
-  int y = gpu.screen.y;
-  int w = gpu.screen.w;
-  int h;
-  uint16_t *srcs;
-  uint8_t  *dest;
+  int left;
 
-  srcs = &gpu.vram[y * 1024 + x];
+  log_io("gpu_dma_write %p %d\n", mem, count);
 
-  h = gpu.screen.y2 - gpu.screen.y1;
+  if (unlikely(gpu.cmd_len > 0))
+    flush_cmd_buffer();
 
-  if (h <= 0)
-    return;
+  left = check_cmd(mem, count);
+  if (left)
+    log_anomaly("GPUwriteDataMem: discarded %d/%d words\n", left, count);
+}
 
-  if ((gpu.status.reg ^ old_status) & ((7<<16)|(1<<21)) || h != old_h) // width|rgb24 change?
+void GPUwriteData(uint32_t data)
+{
+  log_io("gpu_write %08x\n", data);
+  gpu.cmd_buffer[gpu.cmd_len++] = data;
+  if (gpu.cmd_len >= CMD_BUFFER_LEN)
+    flush_cmd_buffer();
+}
+
+long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
+{
+  uint32_t addr, *list;
+  uint32_t *llist_entry = NULL;
+  int len, left, count;
+  long cpu_cycles = 0;
+
+  if (unlikely(gpu.cmd_len > 0))
+    flush_cmd_buffer();
+
+  // ff7 sends it's main list twice, detect this
+  if (*gpu.state.frame_count == gpu.state.last_list.frame &&
+      *gpu.state.hcnt - gpu.state.last_list.hcnt <= 1 &&
+       gpu.state.last_list.cycles > 2048)
   {
-    old_status = gpu.status.reg;
-    old_h = h;
-    screen_buf = cbs->pl_fbdev_set_mode(w, h, gpu.status.rgb24 ? 24 : 16);
+    llist_entry = rambase + (gpu.state.last_list.addr & 0x1fffff) / 4;
+    *llist_entry |= 0x800000;
   }
-  dest = screen_buf;
 
-  if (gpu.status.rgb24)
+  log_io("gpu_dma_chain\n");
+  addr = start_addr & 0xffffff;
+  for (count = 0; addr != 0xffffff; count++)
   {
-#ifndef MAEMO
-    for (; h-- > 0; dest += w * 3, srcs += 1024)
-    {
-      bgr888_to_rgb888(dest, srcs, w * 3);
+    list = rambase + (addr & 0x1fffff) / 4;
+    len = list[0] >> 24;
+    addr = list[0] & 0xffffff;
+    cpu_cycles += 10;
+    if (len > 0)
+      cpu_cycles += 5 + len;
+
+    log_io(".chain %08x #%d\n", (list - rambase) * 4, len);
+
+    // loop detection marker
+    // (bit23 set causes DMA error on real machine, so
+    //  unlikely to be ever set by the game)
+    list[0] |= 0x800000;
+
+    if (len) {
+      left = check_cmd(list + 1, len);
+      if (left)
+        log_anomaly("GPUdmaChain: discarded %d/%d words\n", left, len);
     }
-#else
-    for (; h-- > 0; dest += w * 2, srcs += 1024)
-    {
-      bgr888_to_rgb565(dest, srcs, w * 3);
-    }
-#endif
+
+    if (addr & 0x800000)
+      break;
   }
-  else
-  {
-    for (; h-- > 0; dest += w * 2, srcs += 1024)
-    {
-      bgr555_to_rgb565(dest, srcs, w * 2);
-    }
+
+  // remove loop detection markers
+  addr = start_addr & 0x1fffff;
+  while (count-- > 0) {
+    list = rambase + addr / 4;
+    addr = list[0] & 0x1fffff;
+    list[0] &= ~0x800000;
   }
+  if (llist_entry)
+    *llist_entry &= ~0x800000;
+
+  gpu.state.last_list.frame = *gpu.state.frame_count;
+  gpu.state.last_list.hcnt = *gpu.state.hcnt;
+  gpu.state.last_list.cycles = cpu_cycles;
+  gpu.state.last_list.addr = start_addr;
 
-  screen_buf = cbs->pl_fbdev_flip();
+  return cpu_cycles;
 }
 
-void GPUupdateLace(void)
+void GPUreadDataMem(uint32_t *mem, int count)
 {
-  blit();
+  log_io("gpu_dma_read  %p %d\n", mem, count);
+
+  if (unlikely(gpu.cmd_len > 0))
+    flush_cmd_buffer();
+
+  if (gpu.dma.h)
+    do_vram_io(mem, count, 1);
 }
 
-long GPUopen(void)
+uint32_t GPUreadData(void)
 {
-  cbs->pl_fbdev_open();
-  screen_buf = cbs->pl_fbdev_flip();
-  return 0;
+  uint32_t ret;
+
+  if (unlikely(gpu.cmd_len > 0))
+    flush_cmd_buffer();
+
+  ret = gpu.gp0;
+  if (gpu.dma.h)
+    do_vram_io(&ret, 1, 1);
+
+  log_io("gpu_read %08x\n", ret);
+  return ret;
 }
 
-long GPUclose(void)
+uint32_t GPUreadStatus(void)
+{
+  uint32_t ret;
+
+  if (unlikely(gpu.cmd_len > 0))
+    flush_cmd_buffer();
+
+  ret = gpu.status.reg;
+  log_io("gpu_read_status %08x\n", ret);
+  return ret;
+}
+
+struct GPUFreeze
+{
+  uint32_t ulFreezeVersion;      // should be always 1 for now (set by main emu)
+  uint32_t ulStatus;             // current gpu status
+  uint32_t ulControl[256];       // latest control register values
+  unsigned char psxVRam[1024*1024*2]; // current VRam image (full 2 MB for ZN)
+};
+
+long GPUfreeze(uint32_t type, struct GPUFreeze *freeze)
 {
-  cbs->pl_fbdev_close();
-  return 0;
+  int i;
+
+  switch (type) {
+    case 1: // save
+      if (gpu.cmd_len > 0)
+        flush_cmd_buffer();
+      memcpy(freeze->psxVRam, gpu.vram, sizeof(gpu.vram));
+      memcpy(freeze->ulControl, gpu.regs, sizeof(gpu.regs));
+      memcpy(freeze->ulControl + 0xe0, gpu.ex_regs, sizeof(gpu.ex_regs));
+      freeze->ulStatus = gpu.status.reg;
+      break;
+    case 0: // load
+      renderer_invalidate_caches(0, 0, 1024, 512);
+      memcpy(gpu.vram, freeze->psxVRam, sizeof(gpu.vram));
+      memcpy(gpu.regs, freeze->ulControl, sizeof(gpu.regs));
+      memcpy(gpu.ex_regs, freeze->ulControl + 0xe0, sizeof(gpu.ex_regs));
+      gpu.status.reg = freeze->ulStatus;
+      for (i = 8; i > 0; i--) {
+        gpu.regs[i] ^= 1; // avoid reg change detection
+        GPUwriteStatus((i << 24) | (gpu.regs[i] ^ 1));
+      }
+      renderer_sync_ecmds(gpu.ex_regs);
+      break;
+  }
+
+  return 1;
 }
 
-void GPUrearmedCallbacks(const struct rearmed_cbs *cbs_)
+void GPUvBlank(int is_vblank, int lcf)
 {
-  cbs = cbs_;
 }
 
 // vim:shiftwidth=2:expandtab