X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=plugins%2Fgpu_neon%2Fgpu.c;h=24f731e428c75fea01310ff3abc1f62db06f63e4;hp=da6317ecd7e9cd0a9095a1e23693dbf1b09b7176;hb=90ca49139cdc64ab374f2e763cb4c28fffd0a7b8;hpb=56f08d8331df07ee6b17dfdba0ca2b5f0b1058c8

diff --git a/plugins/gpu_neon/gpu.c b/plugins/gpu_neon/gpu.c
index da6317ec..24f731e4 100644
--- a/plugins/gpu_neon/gpu.c
+++ b/plugins/gpu_neon/gpu.c
@@ -14,18 +14,107 @@
 
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 #define unlikely(x) __builtin_expect((x), 0)
+#define noinline __attribute__((noinline))
 
-//#define log_io printf
+#define gpu_log(fmt, ...) \
+  printf("%d:%03d: " fmt, *gpu.state.frame_count, *gpu.state.hcnt, ##__VA_ARGS__)
+
+//#define log_io gpu_log
 #define log_io(...)
-#define log_anomaly printf
+//#define log_anomaly gpu_log
+#define log_anomaly(...)
 
-struct psx_gpu gpu __attribute__((aligned(64)));
+struct psx_gpu gpu __attribute__((aligned(2048)));
 
-long GPUinit(void)
+static noinline void do_reset(void)
 {
-  int ret = vout_init();
+  memset(gpu.regs, 0, sizeof(gpu.regs));
   gpu.status.reg = 0x14802000;
-  gpu.lcf_hc = &gpu.zero;
+  gpu.gp0 = 0;
+  gpu.regs[3] = 1;
+  gpu.screen.hres = gpu.screen.w = 256;
+  gpu.screen.vres = gpu.screen.h = 240;
+}
+
+static noinline void update_width(void)
+{
+  int sw = gpu.screen.x2 - gpu.screen.x1;
+  if (sw <= 0 || sw >= 2560)
+    // full width
+    gpu.screen.w = gpu.screen.hres;
+  else
+    gpu.screen.w = sw * gpu.screen.hres / 2560;
+}
+
+static noinline void update_height(void)
+{
+  int sh = gpu.screen.y2 - gpu.screen.y1;
+  if (gpu.status.dheight)
+    sh *= 2;
+  if (sh <= 0)
+    sh = gpu.screen.vres;
+
+  gpu.screen.h = sh;
+}
+
+static noinline void decide_frameskip(void)
+{
+  if (gpu.frameskip.active)
+    gpu.frameskip.cnt++;
+  else {
+    gpu.frameskip.cnt = 0;
+    gpu.frameskip.frame_ready = 1;
+  }
+
+  if (!gpu.frameskip.active && *gpu.frameskip.advice)
+    gpu.frameskip.active = 1;
+  else if (gpu.frameskip.set > 0 && gpu.frameskip.cnt < gpu.frameskip.set)
+    gpu.frameskip.active = 1;
+  else
+    gpu.frameskip.active = 0;
+}
+
+static noinline void decide_frameskip_allow(uint32_t cmd_e3)
+{
+  // no frameskip if it decides to draw to display area,
+  // but not for interlace since it'll most likely always do that
+  uint32_t x = cmd_e3 & 0x3ff;
+  uint32_t y = (cmd_e3 >> 10) & 0x3ff;
+  gpu.frameskip.allow = gpu.status.interlace ||
+    (uint32_t)(x - gpu.screen.x) >= (uint32_t)gpu.screen.w ||
+    (uint32_t)(y - gpu.screen.y) >= (uint32_t)gpu.screen.h;
+}
+
+static noinline void get_gpu_info(uint32_t data)
+{
+  switch (data & 0x0f) {
+    case 0x02:
+    case 0x03:
+    case 0x04:
+    case 0x05:
+      gpu.gp0 = gpu.ex_regs[data & 7] & 0xfffff;
+      break;
+    case 0x06:
+      gpu.gp0 = gpu.ex_regs[5] & 0xfffff;
+      break;
+    case 0x07:
+      gpu.gp0 = 2;
+      break;
+    default:
+      gpu.gp0 = 0;
+      break;
+  }
+}
+
+long GPUinit(void)
+{
+  int ret;
+  ret  = vout_init();
+  ret |= renderer_init();
+
+  gpu.state.frame_count = &gpu.zero;
+  gpu.state.hcnt = &gpu.zero;
+  do_reset();
   return ret;
 }
 
@@ -40,9 +129,17 @@ void GPUwriteStatus(uint32_t data)
   static const short vres[4] = { 240, 480, 256, 480 };
   uint32_t cmd = data >> 24;
 
-  switch (data >> 24) {
+  if (cmd < ARRAY_SIZE(gpu.regs)) {
+    if (cmd != 0 && cmd != 5 && gpu.regs[cmd] == data)
+      return;
+    gpu.regs[cmd] = data;
+  }
+
+  gpu.state.fb_dirty = 1;
+
+  switch (cmd) {
     case 0x00:
-      gpu.status.reg = 0x14802000;
+      do_reset();
       break;
     case 0x03:
       gpu.status.blanking = data & 1;
@@ -53,20 +150,36 @@ void GPUwriteStatus(uint32_t data)
     case 0x05:
       gpu.screen.x = data & 0x3ff;
       gpu.screen.y = (data >> 10) & 0x3ff;
+      if (gpu.frameskip.set) {
+        decide_frameskip_allow(gpu.ex_regs[3]);
+        if (gpu.frameskip.last_flip_frame != *gpu.state.frame_count) {
+          decide_frameskip();
+          gpu.frameskip.last_flip_frame = *gpu.state.frame_count;
+        }
+      }
+      break;
+    case 0x06:
+      gpu.screen.x1 = data & 0xfff;
+      gpu.screen.x2 = (data >> 12) & 0xfff;
+      update_width();
       break;
     case 0x07:
       gpu.screen.y1 = data & 0x3ff;
       gpu.screen.y2 = (data >> 10) & 0x3ff;
+      update_height();
       break;
     case 0x08:
       gpu.status.reg = (gpu.status.reg & ~0x7f0000) | ((data & 0x3F) << 17) | ((data & 0x40) << 10);
-      gpu.screen.w = hres[(gpu.status.reg >> 16) & 7];
-      gpu.screen.h = vres[(gpu.status.reg >> 19) & 3];
+      gpu.screen.hres = hres[(gpu.status.reg >> 16) & 7];
+      gpu.screen.vres = vres[(gpu.status.reg >> 19) & 3];
+      update_width();
+      update_height();
+      break;
+    default:
+      if ((cmd & 0xf0) == 0x10)
+        get_gpu_info(data);
       break;
   }
-
-  if (cmd < ARRAY_SIZE(gpu.regs))
-    gpu.regs[cmd] = data;
 }
 
 const unsigned char cmd_lengths[256] =
@@ -106,18 +219,26 @@ static int do_vram_io(uint32_t *data, int count, int is_read)
   uint16_t *sdata = (uint16_t *)data;
   int x = gpu.dma.x, y = gpu.dma.y;
   int w = gpu.dma.w, h = gpu.dma.h;
+  int o = gpu.dma.offset;
   int l;
   count *= 2; // operate in 16bpp pixels
 
   if (gpu.dma.offset) {
     l = w - gpu.dma.offset;
-    if (l > count)
+    if (count < l)
       l = count;
-    do_vram_line(x + gpu.dma.offset, y, sdata, l, is_read);
+
+    do_vram_line(x + o, y, sdata, l, is_read);
+
+    if (o + l < w)
+      o += l;
+    else {
+      o = 0;
+      y++;
+      h--;
+    }
     sdata += l;
     count -= l;
-    y++;
-    h--;
   }
 
   for (; h > 0 && count >= w; sdata += w, count -= w, y++, h--) {
@@ -128,19 +249,21 @@ static int do_vram_io(uint32_t *data, int count, int is_read)
   if (h > 0 && count > 0) {
     y &= 511;
     do_vram_line(x, y, sdata, count, is_read);
-    gpu.dma.offset = count;
+    o = count;
     count = 0;
   }
-  else
-    gpu.dma.offset = 0;
   gpu.dma.y = y;
   gpu.dma.h = h;
+  gpu.dma.offset = o;
 
-  return count_initial - (count + 1) / 2;
+  return count_initial - count / 2;
 }
 
 static void start_vram_transfer(uint32_t pos_word, uint32_t size_word, int is_read)
 {
+  if (gpu.dma.h)
+    log_anomaly("start_vram_transfer while old unfinished\n");
+
   gpu.dma.x = pos_word & 1023;
   gpu.dma.y = (pos_word >> 16) & 511;
   gpu.dma.w = size_word & 0xffff; // ?
@@ -149,26 +272,32 @@ static void start_vram_transfer(uint32_t pos_word, uint32_t size_word, int is_re
 
   if (is_read)
     gpu.status.img = 1;
+  else
+    renderer_invalidate_caches(gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h);
 
-  //printf("start_vram_transfer %c (%d, %d) %dx%d\n", is_read ? 'r' : 'w',
-  //  gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h);
+  log_io("start_vram_transfer %c (%d, %d) %dx%d\n", is_read ? 'r' : 'w',
+    gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h);
 }
 
 static int check_cmd(uint32_t *data, int count)
 {
   int len, cmd, start, pos;
+  int vram_dirty = 0;
 
   // process buffer
-  for (start = pos = 0;; )
+  for (start = pos = 0; pos < count; )
   {
     cmd = -1;
     len = 0;
 
     if (gpu.dma.h) {
       pos += do_vram_io(data + pos, count - pos, 0);
+      if (pos == count)
+        break;
       start = pos;
     }
 
+    // do look-ahead pass to detect SR changes and VRAM i/o
     while (pos < count) {
       uint32_t *list = data + pos;
       cmd = list[0] >> 24;
@@ -177,25 +306,21 @@ static int check_cmd(uint32_t *data, int count)
       //printf("  %3d: %02x %d\n", pos, cmd, len);
       if ((cmd & 0xf4) == 0x24) {
         // flat textured prim
-        gpu.status.reg &= ~0x1ff;
-        gpu.status.reg |= list[4] & 0x1ff;
+        gpu.ex_regs[1] &= ~0x1ff;
+        gpu.ex_regs[1] |= list[4] & 0x1ff;
       }
       else if ((cmd & 0xf4) == 0x34) {
         // shaded textured prim
-        gpu.status.reg &= ~0x1ff;
-        gpu.status.reg |= list[5] & 0x1ff;
-      }
-      else switch (cmd)
-      {
-        case 0xe1:
-          gpu.status.reg &= ~0x7ff;
-          gpu.status.reg |= list[0] & 0x7ff;
-          break;
-        case 0xe6:
-          gpu.status.reg &= ~0x1800;
-          gpu.status.reg |= (list[0] & 3) << 11;
-          break;
+        gpu.ex_regs[1] &= ~0x1ff;
+        gpu.ex_regs[1] |= list[5] & 0x1ff;
       }
+      else if (cmd == 0xe3)
+        decide_frameskip_allow(list[0]);
+
+      if (2 <= cmd && cmd < 0xc0)
+        vram_dirty = 1;
+      else if ((cmd & 0xf8) == 0xe0)
+        gpu.ex_regs[cmd & 7] = list[0];
 
       if (pos + len > count) {
         cmd = -1;
@@ -207,7 +332,8 @@ static int check_cmd(uint32_t *data, int count)
     }
 
     if (pos - start > 0) {
-      do_cmd_list(data + start, pos - start);
+      if (!gpu.frameskip.active || !gpu.frameskip.allow)
+        do_cmd_list(data + start, pos - start);
       start = pos;
     }
 
@@ -216,15 +342,19 @@ static int check_cmd(uint32_t *data, int count)
       start_vram_transfer(data[pos + 1], data[pos + 2], cmd == 0xc0);
       pos += len;
     }
+    else if (cmd == -1)
+      break;
+  }
 
-    if (pos >= count)
-      return 0;
+  gpu.status.reg &= ~0x1fff;
+  gpu.status.reg |= gpu.ex_regs[1] & 0x7ff;
+  gpu.status.reg |= (gpu.ex_regs[6] & 3) << 11;
 
-    if (pos + len > count) {
-      //printf("discarding %d words\n", pos + len - count);
-      return pos + len - count;
-    }
-  }
+  if (gpu.frameskip.active)
+    renderer_sync_ecmds(gpu.ex_regs);
+  gpu.state.fb_dirty |= vram_dirty;
+
+  return count - pos;
 }
 
 static void flush_cmd_buffer(void)
@@ -257,29 +387,67 @@ void GPUwriteData(uint32_t data)
     flush_cmd_buffer();
 }
 
-long GPUdmaChain(uint32_t *base, uint32_t addr)
+long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
 {
-  uint32_t *list;
-  int len, left;
+  uint32_t addr, *list;
+  uint32_t *llist_entry = NULL;
+  int len, left, count;
+  long dma_words = 0;
 
   if (unlikely(gpu.cmd_len > 0))
     flush_cmd_buffer();
 
-  log_io("gpu_dma_chain\n");
-  while (addr != 0xffffff) {
-    log_io(".chain %08x\n", addr);
+  // ff7 sends it's main list twice, detect this
+  if (*gpu.state.frame_count == gpu.state.last_list.frame &&
+      *gpu.state.hcnt - gpu.state.last_list.hcnt <= 1 &&
+       gpu.state.last_list.words > 1024)
+  {
+    llist_entry = rambase + (gpu.state.last_list.addr & 0x1fffff) / 4;
+    *llist_entry |= 0x800000;
+  }
 
-    list = base + (addr & 0x1fffff) / 4;
+  log_io("gpu_dma_chain\n");
+  addr = start_addr & 0xffffff;
+  for (count = 0; addr != 0xffffff; count++)
+  {
+    list = rambase + (addr & 0x1fffff) / 4;
     len = list[0] >> 24;
     addr = list[0] & 0xffffff;
+    dma_words += 1 + len;
+
+    log_io(".chain %08x #%d\n", (list - rambase) * 4, len);
+
+    // loop detection marker
+    // (bit23 set causes DMA error on real machine, so
+    //  unlikely to be ever set by the game)
+    list[0] |= 0x800000;
+
     if (len) {
       left = check_cmd(list + 1, len);
       if (left)
-        log_anomaly("GPUwriteDataMem: discarded %d/%d words\n", left, len);
+        log_anomaly("GPUdmaChain: discarded %d/%d words\n", left, len);
     }
+
+    if (addr & 0x800000)
+      break;
+  }
+
+  // remove loop detection markers
+  addr = start_addr & 0x1fffff;
+  while (count-- > 0) {
+    list = rambase + addr / 4;
+    addr = list[0] & 0x1fffff;
+    list[0] &= ~0x800000;
   }
+  if (llist_entry)
+    *llist_entry &= ~0x800000;
 
-  return 0;
+  gpu.state.last_list.frame = *gpu.state.frame_count;
+  gpu.state.last_list.hcnt = *gpu.state.hcnt;
+  gpu.state.last_list.words = dma_words;
+  gpu.state.last_list.addr = start_addr;
+
+  return dma_words;
 }
 
 void GPUreadDataMem(uint32_t *mem, int count)
@@ -295,72 +463,65 @@ void GPUreadDataMem(uint32_t *mem, int count)
 
 uint32_t GPUreadData(void)
 {
-  uint32_t v = 0;
-
   log_io("gpu_read\n");
 
   if (unlikely(gpu.cmd_len > 0))
     flush_cmd_buffer();
 
   if (gpu.dma.h)
-    do_vram_io(&v, 1, 1);
+    do_vram_io(&gpu.gp0, 1, 1);
 
-  return v;
+  return gpu.gp0;
 }
 
 uint32_t GPUreadStatus(void)
 {
-  log_io("gpu_read_status\n");
+  uint32_t ret;
 
   if (unlikely(gpu.cmd_len > 0))
     flush_cmd_buffer();
 
-  return gpu.status.reg | (*gpu.lcf_hc << 31);
+  ret = gpu.status.reg;
+  log_io("gpu_read_status %08x\n", ret);
+  return ret;
 }
 
-typedef struct GPUFREEZETAG
+struct GPUFreeze
 {
   uint32_t ulFreezeVersion;      // should be always 1 for now (set by main emu)
   uint32_t ulStatus;             // current gpu status
   uint32_t ulControl[256];       // latest control register values
   unsigned char psxVRam[1024*1024*2]; // current VRam image (full 2 MB for ZN)
-} GPUFreeze_t;
+};
 
-long GPUfreeze(uint32_t type, GPUFreeze_t *freeze)
+long GPUfreeze(uint32_t type, struct GPUFreeze *freeze)
 {
+  int i;
+
   switch (type) {
     case 1: // save
       if (gpu.cmd_len > 0)
         flush_cmd_buffer();
       memcpy(freeze->psxVRam, gpu.vram, sizeof(gpu.vram));
       memcpy(freeze->ulControl, gpu.regs, sizeof(gpu.regs));
+      memcpy(freeze->ulControl + 0xe0, gpu.ex_regs, sizeof(gpu.ex_regs));
       freeze->ulStatus = gpu.status.reg;
       break;
     case 0: // load
+      renderer_invalidate_caches(0, 0, 1024, 512);
       memcpy(gpu.vram, freeze->psxVRam, sizeof(gpu.vram));
       memcpy(gpu.regs, freeze->ulControl, sizeof(gpu.regs));
+      memcpy(gpu.ex_regs, freeze->ulControl + 0xe0, sizeof(gpu.ex_regs));
       gpu.status.reg = freeze->ulStatus;
-      GPUwriteStatus((5 << 24) | gpu.regs[5]);
-      GPUwriteStatus((7 << 24) | gpu.regs[7]);
-      GPUwriteStatus((8 << 24) | gpu.regs[8]);
+      for (i = 8; i > 0; i--) {
+        gpu.regs[i] ^= 1; // avoid reg change detection
+        GPUwriteStatus((i << 24) | (gpu.regs[i] ^ 1));
+      }
+      renderer_sync_ecmds(gpu.ex_regs);
       break;
   }
 
   return 1;
 }
 
-void GPUvBlank(int val, uint32_t *hcnt)
-{
-  gpu.lcf_hc = &gpu.zero;
-  if (gpu.status.interlace) {
-    if (val)
-      gpu.status.lcf ^= 1;
-  }
-  else {
-    gpu.status.lcf = 0;
-    if (!val)
-      gpu.lcf_hc = hcnt;
-  }
-}
-
 // vim:shiftwidth=2:expandtab