X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=plugins%2Fgpu_neon%2Fgpu.c;h=5b16cd44e8e8738defb342627f319ccdfe5ee52b;hp=978f4d1e8c90f0fbc9770cde3f4344366344e75f;hb=5d834c089ea695dba7643cba8686ce2ac06d8db4;hpb=fb4c6fba4c83b2f00a78c331fd56e5d995ce02ab

diff --git a/plugins/gpu_neon/gpu.c b/plugins/gpu_neon/gpu.c
index 978f4d1e..5b16cd44 100644
--- a/plugins/gpu_neon/gpu.c
+++ b/plugins/gpu_neon/gpu.c
@@ -1,5 +1,5 @@
 /*
- * (C) Gražvydas "notaz" Ignotas, 2011
+ * (C) Gražvydas "notaz" Ignotas, 2011-2012
  *
  * This work is licensed under the terms of any of these licenses
  * (at your option):
@@ -24,11 +24,31 @@
 //#define log_anomaly gpu_log
 #define log_anomaly(...)
 
-struct psx_gpu gpu __attribute__((aligned(64)));
+struct psx_gpu gpu __attribute__((aligned(2048)));
+
+static noinline int do_cmd_buffer(uint32_t *data, int count);
+static void finish_vram_transfer(int is_read);
+
+static noinline void do_cmd_reset(void)
+{
+  if (unlikely(gpu.cmd_len > 0))
+    do_cmd_buffer(gpu.cmd_buffer, gpu.cmd_len);
+  gpu.cmd_len = 0;
+
+  if (unlikely(gpu.dma.h > 0))
+    finish_vram_transfer(gpu.dma_start.is_read);
+  gpu.dma.h = 0;
+}
 
 static noinline void do_reset(void)
 {
+  unsigned int i;
+
+  do_cmd_reset();
+
   memset(gpu.regs, 0, sizeof(gpu.regs));
+  for (i = 0; i < sizeof(gpu.ex_regs) / sizeof(gpu.ex_regs[0]); i++)
+    gpu.ex_regs[i] = (0xe0 + i) << 24;
   gpu.status.reg = 0x14802000;
   gpu.gp0 = 0;
   gpu.regs[3] = 1;
@@ -59,14 +79,32 @@ static noinline void update_height(void)
 
 static noinline void decide_frameskip(void)
 {
-  gpu.frameskip.frame_ready = !gpu.frameskip.active;
+  if (gpu.frameskip.active)
+    gpu.frameskip.cnt++;
+  else {
+    gpu.frameskip.cnt = 0;
+    gpu.frameskip.frame_ready = 1;
+  }
 
-  if (!gpu.frameskip.active && (*gpu.frameskip.advice || gpu.frameskip.set == 1))
+  if (!gpu.frameskip.active && *gpu.frameskip.advice)
+    gpu.frameskip.active = 1;
+  else if (gpu.frameskip.set > 0 && gpu.frameskip.cnt < gpu.frameskip.set)
     gpu.frameskip.active = 1;
   else
     gpu.frameskip.active = 0;
 }
 
+static noinline void decide_frameskip_allow(uint32_t cmd_e3)
+{
+  // no frameskip if it decides to draw to display area,
+  // but not for interlace since it'll most likely always do that
+  uint32_t x = cmd_e3 & 0x3ff;
+  uint32_t y = (cmd_e3 >> 10) & 0x3ff;
+  gpu.frameskip.allow = gpu.status.interlace ||
+    (uint32_t)(x - gpu.screen.x) >= (uint32_t)gpu.screen.w ||
+    (uint32_t)(y - gpu.screen.y) >= (uint32_t)gpu.screen.h;
+}
+
 static noinline void get_gpu_info(uint32_t data)
 {
   switch (data & 0x0f) {
@@ -96,7 +134,10 @@ long GPUinit(void)
 
   gpu.state.frame_count = &gpu.zero;
   gpu.state.hcnt = &gpu.zero;
+  gpu.frameskip.active = 0;
+  gpu.cmd_len = 0;
   do_reset();
+
   return ret;
 }
 
@@ -112,7 +153,7 @@ void GPUwriteStatus(uint32_t data)
   uint32_t cmd = data >> 24;
 
   if (cmd < ARRAY_SIZE(gpu.regs)) {
-    if (cmd != 0 && cmd != 5 && gpu.regs[cmd] == data)
+    if (cmd > 1 && cmd != 5 && gpu.regs[cmd] == data)
       return;
     gpu.regs[cmd] = data;
   }
@@ -123,6 +164,9 @@ void GPUwriteStatus(uint32_t data)
     case 0x00:
       do_reset();
       break;
+    case 0x01:
+      do_cmd_reset();
+      break;
     case 0x03:
       gpu.status.blanking = data & 1;
       break;
@@ -132,9 +176,12 @@ void GPUwriteStatus(uint32_t data)
     case 0x05:
       gpu.screen.x = data & 0x3ff;
       gpu.screen.y = (data >> 10) & 0x3ff;
-      if (gpu.frameskip.set && gpu.frameskip.last_flip_frame != *gpu.state.frame_count) {
-        decide_frameskip();
-        gpu.frameskip.last_flip_frame = *gpu.state.frame_count;
+      if (gpu.frameskip.set) {
+        decide_frameskip_allow(gpu.ex_regs[3]);
+        if (gpu.frameskip.last_flip_frame != *gpu.state.frame_count) {
+          decide_frameskip();
+          gpu.frameskip.last_flip_frame = *gpu.state.frame_count;
+        }
       }
       break;
     case 0x06:
@@ -167,9 +214,9 @@ const unsigned char cmd_lengths[256] =
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	3, 3, 3, 3, 6, 6, 6, 6, 4, 4, 4, 4, 8, 8, 8, 8, // 20
 	5, 5, 5, 5, 8, 8, 8, 8, 7, 7, 7, 7, 11, 11, 11, 11,
-	2, 2, 2, 2, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, // 40
-	3, 3, 3, 3, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4, 4,
-	2, 2, 2, 2, 3, 3, 3, 3, 1, 1, 1, 1, 2, 2, 2, 2, // 60
+	2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, // 40
+	3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4,
+	2, 2, 2, 2, 3, 3, 3, 3, 1, 1, 1, 1, 0, 0, 0, 0, // 60
 	1, 1, 1, 1, 2, 2, 2, 2, 1, 1, 1, 1, 2, 2, 2, 2,
 	3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 80
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -225,12 +272,16 @@ static int do_vram_io(uint32_t *data, int count, int is_read)
     do_vram_line(x, y, sdata, w, is_read);
   }
 
-  if (h > 0 && count > 0) {
-    y &= 511;
-    do_vram_line(x, y, sdata, count, is_read);
-    o = count;
-    count = 0;
+  if (h > 0) {
+    if (count > 0) {
+      y &= 511;
+      do_vram_line(x, y, sdata, count, is_read);
+      o = count;
+      count = 0;
+    }
   }
+  else
+    finish_vram_transfer(is_read);
   gpu.dma.y = y;
   gpu.dma.h = h;
   gpu.dma.offset = o;
@@ -243,22 +294,36 @@ static void start_vram_transfer(uint32_t pos_word, uint32_t size_word, int is_re
   if (gpu.dma.h)
     log_anomaly("start_vram_transfer while old unfinished\n");
 
-  gpu.dma.x = pos_word & 1023;
-  gpu.dma.y = (pos_word >> 16) & 511;
-  gpu.dma.w = size_word & 0xffff; // ?
-  gpu.dma.h = size_word >> 16;
+  gpu.dma.x = pos_word & 0x3ff;
+  gpu.dma.y = (pos_word >> 16) & 0x1ff;
+  gpu.dma.w = ((size_word - 1) & 0x3ff) + 1;
+  gpu.dma.h = (((size_word >> 16) - 1) & 0x1ff) + 1;
   gpu.dma.offset = 0;
+  gpu.dma.is_read = is_read;
+  gpu.dma_start = gpu.dma;
 
-  if (is_read)
+  renderer_flush_queues();
+  if (is_read) {
     gpu.status.img = 1;
-  else
-    renderer_invalidate_caches(gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h);
+    // XXX: wrong for width 1
+    memcpy(&gpu.gp0, VRAM_MEM_XY(gpu.dma.x, gpu.dma.y), 4);
+    gpu.state.last_vram_read_frame = *gpu.state.frame_count;
+  }
 
   log_io("start_vram_transfer %c (%d, %d) %dx%d\n", is_read ? 'r' : 'w',
     gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h);
 }
 
-static int check_cmd(uint32_t *data, int count)
+static void finish_vram_transfer(int is_read)
+{
+  if (is_read)
+    gpu.status.img = 0;
+  else
+    renderer_update_caches(gpu.dma_start.x, gpu.dma_start.y,
+                           gpu.dma_start.w, gpu.dma_start.h);
+}
+
+static noinline int do_cmd_buffer(uint32_t *data, int count)
 {
   int len, cmd, start, pos;
   int vram_dirty = 0;
@@ -294,15 +359,8 @@ static int check_cmd(uint32_t *data, int count)
         gpu.ex_regs[1] |= list[5] & 0x1ff;
       }
       else if (cmd == 0xe3)
-      {
-        // no frameskip if it decides to draw to display area,
-        // but not for interlace since it'll most likely always do that
-        uint32_t x = list[0] & 0x3ff;
-        uint32_t y = (list[0] >> 10) & 0x3ff;
-        gpu.frameskip.allow = gpu.status.interlace ||
-          (uint32_t)(x - gpu.screen.x) >= (uint32_t)gpu.screen.w ||
-          (uint32_t)(y - gpu.screen.y) >= (uint32_t)gpu.screen.h;
-      }
+        decide_frameskip_allow(list[0]);
+
       if (2 <= cmd && cmd < 0xc0)
         vram_dirty = 1;
       else if ((cmd & 0xf8) == 0xe0)
@@ -345,7 +403,7 @@ static int check_cmd(uint32_t *data, int count)
 
 static void flush_cmd_buffer(void)
 {
-  int left = check_cmd(gpu.cmd_buffer, gpu.cmd_len);
+  int left = do_cmd_buffer(gpu.cmd_buffer, gpu.cmd_len);
   if (left > 0)
     memmove(gpu.cmd_buffer, gpu.cmd_buffer + gpu.cmd_len - left, left * 4);
   gpu.cmd_len = left;
@@ -360,7 +418,7 @@ void GPUwriteDataMem(uint32_t *mem, int count)
   if (unlikely(gpu.cmd_len > 0))
     flush_cmd_buffer();
 
-  left = check_cmd(mem, count);
+  left = do_cmd_buffer(mem, count);
   if (left)
     log_anomaly("GPUwriteDataMem: discarded %d/%d words\n", left, count);
 }
@@ -378,7 +436,7 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
   uint32_t addr, *list;
   uint32_t *llist_entry = NULL;
   int len, left, count;
-  long dma_words = 0;
+  long cpu_cycles = 0;
 
   if (unlikely(gpu.cmd_len > 0))
     flush_cmd_buffer();
@@ -386,7 +444,7 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
   // ff7 sends it's main list twice, detect this
   if (*gpu.state.frame_count == gpu.state.last_list.frame &&
       *gpu.state.hcnt - gpu.state.last_list.hcnt <= 1 &&
-       gpu.state.last_list.words > 1024)
+       gpu.state.last_list.cycles > 2048)
   {
     llist_entry = rambase + (gpu.state.last_list.addr & 0x1fffff) / 4;
     *llist_entry |= 0x800000;
@@ -399,7 +457,9 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
     list = rambase + (addr & 0x1fffff) / 4;
     len = list[0] >> 24;
     addr = list[0] & 0xffffff;
-    dma_words += 1 + len;
+    cpu_cycles += 10;
+    if (len > 0)
+      cpu_cycles += 5 + len;
 
     log_io(".chain %08x #%d\n", (list - rambase) * 4, len);
 
@@ -409,7 +469,7 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
     list[0] |= 0x800000;
 
     if (len) {
-      left = check_cmd(list + 1, len);
+      left = do_cmd_buffer(list + 1, len);
       if (left)
         log_anomaly("GPUdmaChain: discarded %d/%d words\n", left, len);
     }
@@ -430,10 +490,10 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
 
   gpu.state.last_list.frame = *gpu.state.frame_count;
   gpu.state.last_list.hcnt = *gpu.state.hcnt;
-  gpu.state.last_list.words = dma_words;
+  gpu.state.last_list.cycles = cpu_cycles;
   gpu.state.last_list.addr = start_addr;
 
-  return dma_words;
+  return cpu_cycles;
 }
 
 void GPUreadDataMem(uint32_t *mem, int count)
@@ -449,15 +509,17 @@ void GPUreadDataMem(uint32_t *mem, int count)
 
 uint32_t GPUreadData(void)
 {
-  log_io("gpu_read\n");
+  uint32_t ret;
 
   if (unlikely(gpu.cmd_len > 0))
     flush_cmd_buffer();
 
+  ret = gpu.gp0;
   if (gpu.dma.h)
-    do_vram_io(&gpu.gp0, 1, 1);
+    do_vram_io(&ret, 1, 1);
 
-  return gpu.gp0;
+  log_io("gpu_read %08x\n", ret);
+  return ret;
 }
 
 uint32_t GPUreadStatus(void)
@@ -472,15 +534,15 @@ uint32_t GPUreadStatus(void)
   return ret;
 }
 
-typedef struct GPUFREEZETAG
+struct GPUFreeze
 {
   uint32_t ulFreezeVersion;      // should be always 1 for now (set by main emu)
   uint32_t ulStatus;             // current gpu status
   uint32_t ulControl[256];       // latest control register values
   unsigned char psxVRam[1024*1024*2]; // current VRam image (full 2 MB for ZN)
-} GPUFreeze_t;
+};
 
-long GPUfreeze(uint32_t type, GPUFreeze_t *freeze)
+long GPUfreeze(uint32_t type, struct GPUFreeze *freeze)
 {
   int i;
 
@@ -494,7 +556,6 @@ long GPUfreeze(uint32_t type, GPUFreeze_t *freeze)
       freeze->ulStatus = gpu.status.reg;
       break;
     case 0: // load
-      renderer_invalidate_caches(0, 0, 1024, 512);
       memcpy(gpu.vram, freeze->psxVRam, sizeof(gpu.vram));
       memcpy(gpu.regs, freeze->ulControl, sizeof(gpu.regs));
       memcpy(gpu.ex_regs, freeze->ulControl + 0xe0, sizeof(gpu.ex_regs));
@@ -504,10 +565,72 @@ long GPUfreeze(uint32_t type, GPUFreeze_t *freeze)
         GPUwriteStatus((i << 24) | (gpu.regs[i] ^ 1));
       }
       renderer_sync_ecmds(gpu.ex_regs);
+      renderer_update_caches(0, 0, 1024, 512);
       break;
   }
 
   return 1;
 }
 
+void GPUupdateLace(void)
+{
+  if (gpu.cmd_len > 0)
+    flush_cmd_buffer();
+  renderer_flush_queues();
+
+  if (gpu.status.blanking || !gpu.state.fb_dirty)
+    return;
+
+  if (gpu.frameskip.set) {
+    if (!gpu.frameskip.frame_ready) {
+      if (*gpu.state.frame_count - gpu.frameskip.last_flip_frame < 9)
+        return;
+      gpu.frameskip.active = 0;
+    }
+    gpu.frameskip.frame_ready = 0;
+  }
+
+  vout_update();
+  gpu.state.fb_dirty = 0;
+}
+
+void GPUvBlank(int is_vblank, int lcf)
+{
+  int interlace = gpu.state.allow_interlace
+    && gpu.status.interlace && gpu.status.dheight;
+  // interlace doesn't look nice on progressive displays,
+  // so we have this "auto" mode here for games that don't read vram
+  if (gpu.state.allow_interlace == 2
+      && *gpu.state.frame_count - gpu.state.last_vram_read_frame > 1)
+  {
+    interlace = 0;
+  }
+  if (interlace || interlace != gpu.state.old_interlace) {
+    gpu.state.old_interlace = interlace;
+
+    if (gpu.cmd_len > 0)
+      flush_cmd_buffer();
+    renderer_flush_queues();
+    renderer_set_interlace(interlace, !lcf);
+  }
+}
+
+#include "../../frontend/plugin_lib.h"
+
+void GPUrearmedCallbacks(const struct rearmed_cbs *cbs)
+{
+  gpu.frameskip.set = cbs->frameskip;
+  gpu.frameskip.advice = &cbs->fskip_advice;
+  gpu.frameskip.active = 0;
+  gpu.frameskip.frame_ready = 1;
+  gpu.state.hcnt = cbs->gpu_hcnt;
+  gpu.state.frame_count = cbs->gpu_frame_count;
+  gpu.state.allow_interlace = cbs->gpu_neon.allow_interlace;
+
+  if (cbs->pl_vout_set_raw_vram)
+    cbs->pl_vout_set_raw_vram(gpu.vram);
+  renderer_set_config(cbs);
+  vout_set_config(cbs);
+}
+
 // vim:shiftwidth=2:expandtab