X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=plugins%2Fgpu_neon%2Fgpu.c;h=a18e05ffd0d23fd2868c16701e6321420fa2f79b;hp=91a173805d81abe65ee366f6d991beea6e8bcdef;hb=9e1462065c70531c06f40af2fa74660a27f5b410;hpb=fc84f6188a55f2548956356c0eda64945183cafc

diff --git a/plugins/gpu_neon/gpu.c b/plugins/gpu_neon/gpu.c
index 91a17380..a18e05ff 100644
--- a/plugins/gpu_neon/gpu.c
+++ b/plugins/gpu_neon/gpu.c
@@ -16,27 +16,24 @@
 #define unlikely(x) __builtin_expect((x), 0)
 #define noinline __attribute__((noinline))
 
-//#define log_io printf
+#define gpu_log(fmt, ...) \
+  printf("%d:%03d: " fmt, *gpu.state.frame_count, *gpu.state.hcnt, ##__VA_ARGS__)
+
+//#define log_io gpu_log
 #define log_io(...)
-#define log_anomaly printf
+//#define log_anomaly gpu_log
+#define log_anomaly(...)
 
-struct psx_gpu gpu __attribute__((aligned(64)));
+struct psx_gpu gpu __attribute__((aligned(2048)));
 
-long GPUinit(void)
+static noinline void do_reset(void)
 {
-  int ret = vout_init();
+  memset(gpu.regs, 0, sizeof(gpu.regs));
   gpu.status.reg = 0x14802000;
-  gpu.status.blanking = 1;
+  gpu.gp0 = 0;
   gpu.regs[3] = 1;
-  gpu.screen.hres = gpu.screen.w = 320;
+  gpu.screen.hres = gpu.screen.w = 256;
   gpu.screen.vres = gpu.screen.h = 240;
-  gpu.lcf_hc = &gpu.zero;
-  return ret;
-}
-
-long GPUshutdown(void)
-{
-  return vout_finish();
 }
 
 static noinline void update_width(void)
@@ -62,14 +59,70 @@ static noinline void update_height(void)
 
 static noinline void decide_frameskip(void)
 {
-  gpu.frameskip.frame_ready = !gpu.frameskip.active;
+  if (gpu.frameskip.active)
+    gpu.frameskip.cnt++;
+  else {
+    gpu.frameskip.cnt = 0;
+    gpu.frameskip.frame_ready = 1;
+  }
 
   if (!gpu.frameskip.active && *gpu.frameskip.advice)
     gpu.frameskip.active = 1;
+  else if (gpu.frameskip.set > 0 && gpu.frameskip.cnt < gpu.frameskip.set)
+    gpu.frameskip.active = 1;
   else
     gpu.frameskip.active = 0;
 }
 
+static noinline void decide_frameskip_allow(uint32_t cmd_e3)
+{
+  // no frameskip if it decides to draw to display area,
+  // but not for interlace since it'll most likely always do that
+  uint32_t x = cmd_e3 & 0x3ff;
+  uint32_t y = (cmd_e3 >> 10) & 0x3ff;
+  gpu.frameskip.allow = gpu.status.interlace ||
+    (uint32_t)(x - gpu.screen.x) >= (uint32_t)gpu.screen.w ||
+    (uint32_t)(y - gpu.screen.y) >= (uint32_t)gpu.screen.h;
+}
+
+static noinline void get_gpu_info(uint32_t data)
+{
+  switch (data & 0x0f) {
+    case 0x02:
+    case 0x03:
+    case 0x04:
+    case 0x05:
+      gpu.gp0 = gpu.ex_regs[data & 7] & 0xfffff;
+      break;
+    case 0x06:
+      gpu.gp0 = gpu.ex_regs[5] & 0xfffff;
+      break;
+    case 0x07:
+      gpu.gp0 = 2;
+      break;
+    default:
+      gpu.gp0 = 0;
+      break;
+  }
+}
+
+long GPUinit(void)
+{
+  int ret;
+  ret  = vout_init();
+  ret |= renderer_init();
+
+  gpu.state.frame_count = &gpu.zero;
+  gpu.state.hcnt = &gpu.zero;
+  do_reset();
+  return ret;
+}
+
+long GPUshutdown(void)
+{
+  return vout_finish();
+}
+
 void GPUwriteStatus(uint32_t data)
 {
   static const short hres[8] = { 256, 368, 320, 384, 512, 512, 640, 640 };
@@ -77,7 +130,7 @@ void GPUwriteStatus(uint32_t data)
   uint32_t cmd = data >> 24;
 
   if (cmd < ARRAY_SIZE(gpu.regs)) {
-    if (cmd != 0 && gpu.regs[cmd] == data)
+    if (cmd != 0 && cmd != 5 && gpu.regs[cmd] == data)
       return;
     gpu.regs[cmd] = data;
   }
@@ -86,8 +139,7 @@ void GPUwriteStatus(uint32_t data)
 
   switch (cmd) {
     case 0x00:
-      gpu.status.reg = 0x14802000;
-      gpu.status.blanking = 1;
+      do_reset();
       break;
     case 0x03:
       gpu.status.blanking = data & 1;
@@ -98,8 +150,13 @@ void GPUwriteStatus(uint32_t data)
     case 0x05:
       gpu.screen.x = data & 0x3ff;
       gpu.screen.y = (data >> 10) & 0x3ff;
-      if (gpu.frameskip.enabled)
-        decide_frameskip();
+      if (gpu.frameskip.set) {
+        decide_frameskip_allow(gpu.ex_regs[3]);
+        if (gpu.frameskip.last_flip_frame != *gpu.state.frame_count) {
+          decide_frameskip();
+          gpu.frameskip.last_flip_frame = *gpu.state.frame_count;
+        }
+      }
       break;
     case 0x06:
       gpu.screen.x1 = data & 0xfff;
@@ -118,6 +175,10 @@ void GPUwriteStatus(uint32_t data)
       update_width();
       update_height();
       break;
+    default:
+      if ((cmd & 0xf0) == 0x10)
+        get_gpu_info(data);
+      break;
   }
 }
 
@@ -195,7 +256,7 @@ static int do_vram_io(uint32_t *data, int count, int is_read)
   gpu.dma.h = h;
   gpu.dma.offset = o;
 
-  return count_initial - (count + 1) / 2;
+  return count_initial - count / 2;
 }
 
 static void start_vram_transfer(uint32_t pos_word, uint32_t size_word, int is_read)
@@ -209,11 +270,18 @@ static void start_vram_transfer(uint32_t pos_word, uint32_t size_word, int is_re
   gpu.dma.h = size_word >> 16;
   gpu.dma.offset = 0;
 
-  if (is_read)
+  renderer_flush_queues();
+  if (is_read) {
     gpu.status.img = 1;
+    // XXX: wrong for width 1
+    memcpy(&gpu.gp0, VRAM_MEM_XY(gpu.dma.x, gpu.dma.y), 4);
+  }
+  else {
+    renderer_invalidate_caches(gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h);
+  }
 
-  //printf("start_vram_transfer %c (%d, %d) %dx%d\n", is_read ? 'r' : 'w',
-  //  gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h);
+  log_io("start_vram_transfer %c (%d, %d) %dx%d\n", is_read ? 'r' : 'w',
+    gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h);
 }
 
 static int check_cmd(uint32_t *data, int count)
@@ -243,27 +311,21 @@ static int check_cmd(uint32_t *data, int count)
       //printf("  %3d: %02x %d\n", pos, cmd, len);
       if ((cmd & 0xf4) == 0x24) {
         // flat textured prim
-        gpu.status.reg &= ~0x1ff;
-        gpu.status.reg |= list[4] & 0x1ff;
+        gpu.ex_regs[1] &= ~0x1ff;
+        gpu.ex_regs[1] |= list[4] & 0x1ff;
       }
       else if ((cmd & 0xf4) == 0x34) {
         // shaded textured prim
-        gpu.status.reg &= ~0x1ff;
-        gpu.status.reg |= list[5] & 0x1ff;
-      }
-      else switch (cmd)
-      {
-        case 0xe1:
-          gpu.status.reg &= ~0x7ff;
-          gpu.status.reg |= list[0] & 0x7ff;
-          break;
-        case 0xe6:
-          gpu.status.reg &= ~0x1800;
-          gpu.status.reg |= (list[0] & 3) << 11;
-          break;
+        gpu.ex_regs[1] &= ~0x1ff;
+        gpu.ex_regs[1] |= list[5] & 0x1ff;
       }
+      else if (cmd == 0xe3)
+        decide_frameskip_allow(list[0]);
+
       if (2 <= cmd && cmd < 0xc0)
         vram_dirty = 1;
+      else if ((cmd & 0xf8) == 0xe0)
+        gpu.ex_regs[cmd & 7] = list[0];
 
       if (pos + len > count) {
         cmd = -1;
@@ -275,7 +337,7 @@ static int check_cmd(uint32_t *data, int count)
     }
 
     if (pos - start > 0) {
-      if (!gpu.frameskip.active)
+      if (!gpu.frameskip.active || !gpu.frameskip.allow)
         do_cmd_list(data + start, pos - start);
       start = pos;
     }
@@ -285,17 +347,22 @@ static int check_cmd(uint32_t *data, int count)
       start_vram_transfer(data[pos + 1], data[pos + 2], cmd == 0xc0);
       pos += len;
     }
-
-    if (cmd == -1)
+    else if (cmd == -1)
       break;
   }
 
+  gpu.status.reg &= ~0x1fff;
+  gpu.status.reg |= gpu.ex_regs[1] & 0x7ff;
+  gpu.status.reg |= (gpu.ex_regs[6] & 3) << 11;
+
+  if (gpu.frameskip.active)
+    renderer_sync_ecmds(gpu.ex_regs);
   gpu.state.fb_dirty |= vram_dirty;
 
   return count - pos;
 }
 
-static void flush_cmd_buffer(void)
+void flush_cmd_buffer(void)
 {
   int left = check_cmd(gpu.cmd_buffer, gpu.cmd_len);
   if (left > 0)
@@ -328,20 +395,34 @@ void GPUwriteData(uint32_t data)
 long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
 {
   uint32_t addr, *list;
+  uint32_t *llist_entry = NULL;
   int len, left, count;
+  long cpu_cycles = 0;
 
   if (unlikely(gpu.cmd_len > 0))
     flush_cmd_buffer();
 
+  // ff7 sends it's main list twice, detect this
+  if (*gpu.state.frame_count == gpu.state.last_list.frame &&
+      *gpu.state.hcnt - gpu.state.last_list.hcnt <= 1 &&
+       gpu.state.last_list.cycles > 2048)
+  {
+    llist_entry = rambase + (gpu.state.last_list.addr & 0x1fffff) / 4;
+    *llist_entry |= 0x800000;
+  }
+
   log_io("gpu_dma_chain\n");
   addr = start_addr & 0xffffff;
   for (count = 0; addr != 0xffffff; count++)
   {
-    log_io(".chain %08x\n", addr);
-
     list = rambase + (addr & 0x1fffff) / 4;
     len = list[0] >> 24;
     addr = list[0] & 0xffffff;
+    cpu_cycles += 10;
+    if (len > 0)
+      cpu_cycles += 5 + len;
+
+    log_io(".chain %08x #%d\n", (list - rambase) * 4, len);
 
     // loop detection marker
     // (bit23 set causes DMA error on real machine, so
@@ -351,7 +432,7 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
     if (len) {
       left = check_cmd(list + 1, len);
       if (left)
-        log_anomaly("GPUwriteDataMem: discarded %d/%d words\n", left, len);
+        log_anomaly("GPUdmaChain: discarded %d/%d words\n", left, len);
     }
 
     if (addr & 0x800000)
@@ -365,8 +446,15 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
     addr = list[0] & 0x1fffff;
     list[0] &= ~0x800000;
   }
+  if (llist_entry)
+    *llist_entry &= ~0x800000;
+
+  gpu.state.last_list.frame = *gpu.state.frame_count;
+  gpu.state.last_list.hcnt = *gpu.state.hcnt;
+  gpu.state.last_list.cycles = cpu_cycles;
+  gpu.state.last_list.addr = start_addr;
 
-  return 0;
+  return cpu_cycles;
 }
 
 void GPUreadDataMem(uint32_t *mem, int count)
@@ -382,17 +470,17 @@ void GPUreadDataMem(uint32_t *mem, int count)
 
 uint32_t GPUreadData(void)
 {
-  uint32_t v = 0;
-
-  log_io("gpu_read\n");
+  uint32_t ret;
 
   if (unlikely(gpu.cmd_len > 0))
     flush_cmd_buffer();
 
+  ret = gpu.gp0;
   if (gpu.dma.h)
-    do_vram_io(&v, 1, 1);
+    do_vram_io(&ret, 1, 1);
 
-  return v;
+  log_io("gpu_read %08x\n", ret);
+  return ret;
 }
 
 uint32_t GPUreadStatus(void)
@@ -402,20 +490,20 @@ uint32_t GPUreadStatus(void)
   if (unlikely(gpu.cmd_len > 0))
     flush_cmd_buffer();
 
-  ret = gpu.status.reg | (*gpu.lcf_hc << 31);
+  ret = gpu.status.reg;
   log_io("gpu_read_status %08x\n", ret);
   return ret;
 }
 
-typedef struct GPUFREEZETAG
+struct GPUFreeze
 {
   uint32_t ulFreezeVersion;      // should be always 1 for now (set by main emu)
   uint32_t ulStatus;             // current gpu status
   uint32_t ulControl[256];       // latest control register values
   unsigned char psxVRam[1024*1024*2]; // current VRam image (full 2 MB for ZN)
-} GPUFreeze_t;
+};
 
-long GPUfreeze(uint32_t type, GPUFreeze_t *freeze)
+long GPUfreeze(uint32_t type, struct GPUFreeze *freeze)
 {
   int i;
 
@@ -425,34 +513,24 @@ long GPUfreeze(uint32_t type, GPUFreeze_t *freeze)
         flush_cmd_buffer();
       memcpy(freeze->psxVRam, gpu.vram, sizeof(gpu.vram));
       memcpy(freeze->ulControl, gpu.regs, sizeof(gpu.regs));
+      memcpy(freeze->ulControl + 0xe0, gpu.ex_regs, sizeof(gpu.ex_regs));
       freeze->ulStatus = gpu.status.reg;
       break;
     case 0: // load
+      renderer_invalidate_caches(0, 0, 1024, 512);
       memcpy(gpu.vram, freeze->psxVRam, sizeof(gpu.vram));
       memcpy(gpu.regs, freeze->ulControl, sizeof(gpu.regs));
+      memcpy(gpu.ex_regs, freeze->ulControl + 0xe0, sizeof(gpu.ex_regs));
       gpu.status.reg = freeze->ulStatus;
       for (i = 8; i > 0; i--) {
         gpu.regs[i] ^= 1; // avoid reg change detection
         GPUwriteStatus((i << 24) | (gpu.regs[i] ^ 1));
       }
+      renderer_sync_ecmds(gpu.ex_regs);
       break;
   }
 
   return 1;
 }
 
-void GPUvBlank(int val, uint32_t *hcnt)
-{
-  gpu.lcf_hc = &gpu.zero;
-  if (gpu.status.interlace) {
-    if (val)
-      gpu.status.lcf ^= 1;
-  }
-  else {
-    gpu.status.lcf = 0;
-    if (!val)
-      gpu.lcf_hc = hcnt;
-  }
-}
-
 // vim:shiftwidth=2:expandtab