X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=plugins%2Fgpu_neon%2Fgpu.c;h=a18e05ffd0d23fd2868c16701e6321420fa2f79b;hp=a5d0b876ae31242f77f36e4b5fd077c218961f6b;hb=9e1462065c70531c06f40af2fa74660a27f5b410;hpb=a3a9f519f75d195891d466f77ceb43f90e24f713 diff --git a/plugins/gpu_neon/gpu.c b/plugins/gpu_neon/gpu.c index a5d0b876..a18e05ff 100644 --- a/plugins/gpu_neon/gpu.c +++ b/plugins/gpu_neon/gpu.c @@ -24,7 +24,7 @@ //#define log_anomaly gpu_log #define log_anomaly(...) -struct psx_gpu gpu __attribute__((aligned(64))); +struct psx_gpu gpu __attribute__((aligned(2048))); static noinline void do_reset(void) { @@ -59,14 +59,32 @@ static noinline void update_height(void) static noinline void decide_frameskip(void) { - gpu.frameskip.frame_ready = !gpu.frameskip.active; + if (gpu.frameskip.active) + gpu.frameskip.cnt++; + else { + gpu.frameskip.cnt = 0; + gpu.frameskip.frame_ready = 1; + } - if (!gpu.frameskip.active && (*gpu.frameskip.advice || gpu.frameskip.set == 1)) + if (!gpu.frameskip.active && *gpu.frameskip.advice) + gpu.frameskip.active = 1; + else if (gpu.frameskip.set > 0 && gpu.frameskip.cnt < gpu.frameskip.set) gpu.frameskip.active = 1; else gpu.frameskip.active = 0; } +static noinline void decide_frameskip_allow(uint32_t cmd_e3) +{ + // no frameskip if it decides to draw to display area, + // but not for interlace since it'll most likely always do that + uint32_t x = cmd_e3 & 0x3ff; + uint32_t y = (cmd_e3 >> 10) & 0x3ff; + gpu.frameskip.allow = gpu.status.interlace || + (uint32_t)(x - gpu.screen.x) >= (uint32_t)gpu.screen.w || + (uint32_t)(y - gpu.screen.y) >= (uint32_t)gpu.screen.h; +} + static noinline void get_gpu_info(uint32_t data) { switch (data & 0x0f) { @@ -132,8 +150,13 @@ void GPUwriteStatus(uint32_t data) case 0x05: gpu.screen.x = data & 0x3ff; gpu.screen.y = (data >> 10) & 0x3ff; - if (gpu.frameskip.set) - decide_frameskip(); + if (gpu.frameskip.set) { + decide_frameskip_allow(gpu.ex_regs[3]); + if (gpu.frameskip.last_flip_frame != *gpu.state.frame_count) { + decide_frameskip(); + gpu.frameskip.last_flip_frame = *gpu.state.frame_count; + } + } break; case 0x06: gpu.screen.x1 = data & 0xfff; @@ -247,10 +270,15 @@ static void start_vram_transfer(uint32_t pos_word, uint32_t size_word, int is_re gpu.dma.h = size_word >> 16; gpu.dma.offset = 0; - if (is_read) + renderer_flush_queues(); + if (is_read) { gpu.status.img = 1; - else + // XXX: wrong for width 1 + memcpy(&gpu.gp0, VRAM_MEM_XY(gpu.dma.x, gpu.dma.y), 4); + } + else { renderer_invalidate_caches(gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h); + } log_io("start_vram_transfer %c (%d, %d) %dx%d\n", is_read ? 'r' : 'w', gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h); @@ -291,6 +319,9 @@ static int check_cmd(uint32_t *data, int count) gpu.ex_regs[1] &= ~0x1ff; gpu.ex_regs[1] |= list[5] & 0x1ff; } + else if (cmd == 0xe3) + decide_frameskip_allow(list[0]); + if (2 <= cmd && cmd < 0xc0) vram_dirty = 1; else if ((cmd & 0xf8) == 0xe0) @@ -306,7 +337,7 @@ static int check_cmd(uint32_t *data, int count) } if (pos - start > 0) { - if (!gpu.frameskip.active) + if (!gpu.frameskip.active || !gpu.frameskip.allow) do_cmd_list(data + start, pos - start); start = pos; } @@ -331,7 +362,7 @@ static int check_cmd(uint32_t *data, int count) return count - pos; } -static void flush_cmd_buffer(void) +void flush_cmd_buffer(void) { int left = check_cmd(gpu.cmd_buffer, gpu.cmd_len); if (left > 0) @@ -366,7 +397,7 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr) uint32_t addr, *list; uint32_t *llist_entry = NULL; int len, left, count; - long dma_words = 0; + long cpu_cycles = 0; if (unlikely(gpu.cmd_len > 0)) flush_cmd_buffer(); @@ -374,7 +405,7 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr) // ff7 sends it's main list twice, detect this if (*gpu.state.frame_count == gpu.state.last_list.frame && *gpu.state.hcnt - gpu.state.last_list.hcnt <= 1 && - gpu.state.last_list.words > 1024) + gpu.state.last_list.cycles > 2048) { llist_entry = rambase + (gpu.state.last_list.addr & 0x1fffff) / 4; *llist_entry |= 0x800000; @@ -387,7 +418,9 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr) list = rambase + (addr & 0x1fffff) / 4; len = list[0] >> 24; addr = list[0] & 0xffffff; - dma_words += 1 + len; + cpu_cycles += 10; + if (len > 0) + cpu_cycles += 5 + len; log_io(".chain %08x #%d\n", (list - rambase) * 4, len); @@ -418,10 +451,10 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr) gpu.state.last_list.frame = *gpu.state.frame_count; gpu.state.last_list.hcnt = *gpu.state.hcnt; - gpu.state.last_list.words = dma_words; + gpu.state.last_list.cycles = cpu_cycles; gpu.state.last_list.addr = start_addr; - return dma_words; + return cpu_cycles; } void GPUreadDataMem(uint32_t *mem, int count) @@ -437,15 +470,17 @@ void GPUreadDataMem(uint32_t *mem, int count) uint32_t GPUreadData(void) { - log_io("gpu_read\n"); + uint32_t ret; if (unlikely(gpu.cmd_len > 0)) flush_cmd_buffer(); + ret = gpu.gp0; if (gpu.dma.h) - do_vram_io(&gpu.gp0, 1, 1); + do_vram_io(&ret, 1, 1); - return gpu.gp0; + log_io("gpu_read %08x\n", ret); + return ret; } uint32_t GPUreadStatus(void) @@ -460,15 +495,15 @@ uint32_t GPUreadStatus(void) return ret; } -typedef struct GPUFREEZETAG +struct GPUFreeze { uint32_t ulFreezeVersion; // should be always 1 for now (set by main emu) uint32_t ulStatus; // current gpu status uint32_t ulControl[256]; // latest control register values unsigned char psxVRam[1024*1024*2]; // current VRam image (full 2 MB for ZN) -} GPUFreeze_t; +}; -long GPUfreeze(uint32_t type, GPUFreeze_t *freeze) +long GPUfreeze(uint32_t type, struct GPUFreeze *freeze) { int i;