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drc: attempt to support little endian
authornotaz <notasas@gmail.com>
Tue, 30 Nov 2010 21:36:18 +0000 (23:36 +0200)
committernotaz <notasas@gmail.com>
Wed, 1 Dec 2010 23:17:23 +0000 (01:17 +0200)
libpcsxcore/new_dynarec/assem_arm.c patch | blob | blame | history
libpcsxcore/new_dynarec/new_dynarec.c patch | blob | blame | history

diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c
index d0edaca..ea1da1b 100644 (file)
--- a/libpcsxcore/new_dynarec/assem_arm.c
+++ b/libpcsxcore/new_dynarec/assem_arm.c
@@ -3174,7 +3174,12 @@ void loadlr_assemble_arm(int i,struct regstat *i_regs)
       else
         inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
       emit_andimm(temp,24,temp);
       else
         inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
       emit_andimm(temp,24,temp);
-      if (opcode[i]==0x26) emit_xorimm(temp,24,temp); // LWR
+#ifdef BIG_ENDIAN_MIPS
+      if (opcode[i]==0x26) // LWR
+#else
+      if (opcode[i]==0x22) // LWL
+#endif
+        emit_xorimm(temp,24,temp);
       emit_movimm(-1,HOST_TEMPREG);
       if (opcode[i]==0x26) {
         emit_shr(temp2,temp,temp2);
       emit_movimm(-1,HOST_TEMPREG);
       if (opcode[i]==0x26) {
         emit_shr(temp2,temp,temp2);
@@ -3187,6 +3192,7 @@ void loadlr_assemble_arm(int i,struct regstat *i_regs)
       //emit_storereg(rt1[i],tl); // DEBUG
     }
     if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
       //emit_storereg(rt1[i],tl); // DEBUG
     }
     if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
+      // FIXME: little endian
       int temp2h=get_reg(i_regs->regmap,FTEMP|64);
       if(!c||memtarget) {
         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
       int temp2h=get_reg(i_regs->regmap,FTEMP|64);
       if(!c||memtarget) {
         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c
index 9e58ef0..6f7c567 100644 (file)
--- a/libpcsxcore/new_dynarec/new_dynarec.c
+++ b/libpcsxcore/new_dynarec/new_dynarec.c
@@ -2748,8 +2748,13 @@ void load_assemble(int i,struct regstat *i_regs)
           //gen_tlb_addr_r(tl,map);
           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
           int x=0;
           //gen_tlb_addr_r(tl,map);
           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
           int x=0;
+#ifdef BIG_ENDIAN_MIPS
           if(!c) emit_xorimm(addr,3,tl);
           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
           if(!c) emit_xorimm(addr,3,tl);
           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
+#else
+          if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
+          else if (tl!=addr) emit_mov(addr,tl);
+#endif
           emit_movsbl_indexed_tlb(x,tl,map,tl);
         }
         if(jaddr)
           emit_movsbl_indexed_tlb(x,tl,map,tl);
         }
         if(jaddr)
@@ -2767,8 +2772,13 @@ void load_assemble(int i,struct regstat *i_regs)
         #endif
         {
           int x=0;
         #endif
         {
           int x=0;
+#ifdef BIG_ENDIAN_MIPS
           if(!c) emit_xorimm(addr,2,tl);
           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
           if(!c) emit_xorimm(addr,2,tl);
           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
+#else
+          if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
+          else if (tl!=addr) emit_mov(addr,tl);
+#endif
           //#ifdef
           //emit_movswl_indexed_tlb(x,tl,map,tl);
           //else
           //#ifdef
           //emit_movswl_indexed_tlb(x,tl,map,tl);
           //else
@@ -2811,8 +2821,13 @@ void load_assemble(int i,struct regstat *i_regs)
           //gen_tlb_addr_r(tl,map);
           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
           int x=0;
           //gen_tlb_addr_r(tl,map);
           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
           int x=0;
+#ifdef BIG_ENDIAN_MIPS
           if(!c) emit_xorimm(addr,3,tl);
           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
           if(!c) emit_xorimm(addr,3,tl);
           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
+#else
+          if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
+          else if (tl!=addr) emit_mov(addr,tl);
+#endif
           emit_movzbl_indexed_tlb(x,tl,map,tl);
         }
         if(jaddr)
           emit_movzbl_indexed_tlb(x,tl,map,tl);
         }
         if(jaddr)
@@ -2830,8 +2845,13 @@ void load_assemble(int i,struct regstat *i_regs)
         #endif
         {
           int x=0;
         #endif
         {
           int x=0;
+#ifdef BIG_ENDIAN_MIPS
           if(!c) emit_xorimm(addr,2,tl);
           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
           if(!c) emit_xorimm(addr,2,tl);
           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
+#else
+          if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
+          else if (tl!=addr) emit_mov(addr,tl);
+#endif
           //#ifdef
           //emit_movzwl_indexed_tlb(x,tl,map,tl);
           //#else
           //#ifdef
           //emit_movzwl_indexed_tlb(x,tl,map,tl);
           //#else
@@ -2988,8 +3008,13 @@ void store_assemble(int i,struct regstat *i_regs)
   if (opcode[i]==0x28) { // SB
     if(!c||memtarget) {
       int x=0;
   if (opcode[i]==0x28) { // SB
     if(!c||memtarget) {
       int x=0;
+#ifdef BIG_ENDIAN_MIPS
       if(!c) emit_xorimm(addr,3,temp);
       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
       if(!c) emit_xorimm(addr,3,temp);
       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
+#else
+      if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
+      else if (addr!=temp) emit_mov(addr,temp);
+#endif
       //gen_tlb_addr_w(temp,map);
       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
       emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
       //gen_tlb_addr_w(temp,map);
       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
       emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
@@ -2999,8 +3024,13 @@ void store_assemble(int i,struct regstat *i_regs)
   if (opcode[i]==0x29) { // SH
     if(!c||memtarget) {
       int x=0;
   if (opcode[i]==0x29) { // SH
     if(!c||memtarget) {
       int x=0;
+#ifdef BIG_ENDIAN_MIPS
       if(!c) emit_xorimm(addr,2,temp);
       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
       if(!c) emit_xorimm(addr,2,temp);
       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
+#else
+      if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
+      else if (addr!=temp) emit_mov(addr,temp);
+#endif
       //#ifdef
       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
       //#else
       //#ifdef
       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
       //#else
@@ -3150,6 +3180,9 @@ void storelr_assemble(int i,struct regstat *i_regs)
       if(!rs2[i]) temp2=th=tl;
     }
 
       if(!rs2[i]) temp2=th=tl;
     }
 
+#ifndef BIG_ENDIAN_MIPS
+    emit_xorimm(temp,3,temp);
+#endif
     emit_testimm(temp,2);
     case2=(int)out;
     emit_jne(0);
     emit_testimm(temp,2);
     case2=(int)out;
     emit_jne(0);
ARM optimized PCSX fork