# dynarec
ifndef NO_NEW_DRC
OBJS += libpcsxcore/new_dynarec/new_dynarec.o libpcsxcore/new_dynarec/linkage_arm.o
+OBJS += libpcsxcore/new_dynarec/pcsxmem.o
endif
OBJS += libpcsxcore/new_dynarec/emu_if.o
libpcsxcore/new_dynarec/new_dynarec.o: libpcsxcore/new_dynarec/assem_arm.c
+/*
+ * (C) Gražvydas "notaz" Ignotas, 2010
+ *
+ * This work is licensed under the terms of GNU GPL version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
// pending_exception?
// swi 0 in do_unalignedwritestub?
#include <stdio.h>
#include "emu_if.h"
-#include "../psxmem.h"
+#include "pcsxmem.h"
#include "../psxhle.h"
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
-//#define memprintf printf
-#define memprintf(...)
//#define evprintf printf
#define evprintf(...)
printf("ari64_check_interupt\n");
}
-void read_nomem_new()
-{
- printf("ari64_read_nomem_new\n");
-}
-
-static void read_mem8()
-{
- memprintf("ari64_read_mem8 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
- readmem_word = psxMemRead8(address) & 0xff;
-}
-
-static void read_mem16()
-{
- memprintf("ari64_read_mem16 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
- readmem_word = psxMemRead16(address) & 0xffff;
-}
-
-static void read_mem32()
-{
- memprintf("ari64_read_mem32 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
- readmem_word = psxMemRead32(address);
-}
-
-static void write_mem8()
-{
- memprintf("ari64_write_mem8 %08x, %02x @%08x %u\n", address, byte, psxRegs.pc, psxRegs.cycle);
- psxMemWrite8(address, byte);
-}
-
-static void write_mem16()
-{
- memprintf("ari64_write_mem16 %08x, %04x @%08x %u\n", address, hword, psxRegs.pc, psxRegs.cycle);
- psxMemWrite16(address, hword);
-}
-
-static void write_mem32()
-{
- memprintf("ari64_write_mem32 %08x, %08x @%08x %u\n", address, word, psxRegs.pc, psxRegs.cycle);
- psxMemWrite32(address, word);
-}
-
-void (*readmem[0x10000])();
-void (*readmemb[0x10000])();
-void (*readmemh[0x10000])();
-void (*writemem[0x10000])();
-void (*writememb[0x10000])();
-void (*writememh[0x10000])();
-
void *gte_handlers[64];
/* from gte.txt.. not sure if this is any good. */
{
extern void (*psxCP2[64])();
extern void psxNULL();
+ extern void *psxH_ptr;
size_t i;
new_dynarec_init();
-
- for (i = 0; i < ARRAY_SIZE(readmem); i++) {
- readmemb[i] = read_mem8;
- readmemh[i] = read_mem16;
- readmem[i] = read_mem32;
- writememb[i] = write_mem8;
- writememh[i] = write_mem16;
- writemem[i] = write_mem32;
- }
+ new_dyna_pcsx_mem_init();
for (i = 0; i < ARRAY_SIZE(gte_handlers); i++)
if (psxCP2[i] != psxNULL)
gte_handlers[i] = psxCP2[i];
+ psxH_ptr = psxH;
+
return 0;
}
static void ari64_reset()
{
printf("ari64_reset\n");
+ new_dyna_pcsx_mem_reset();
invalidate_all_pages();
pending_exception = 1;
}
unsigned char byte;
int pending_exception, stop;
unsigned int next_interupt;
+void *psxH_ptr;
void new_dynarec_init() {}
void new_dyna_start() {}
void new_dynarec_cleanup() {}
void invalidate_all_pages() {}
void invalidate_block(unsigned int block) {}
+void new_dyna_pcsx_mem_init(void) {}
+void new_dyna_pcsx_mem_reset(void) {}
#endif
#ifdef DRC_DBG
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
- * Mupen64plus - linkage_arm.s *
+ * linkage_arm.s for PCSX *
* Copyright (C) 2009-2010 Ari64 *
+ * Copyright (C) 2010 Gražvydas "notaz" Ignotas *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
.global memory_map
/* psx */
.global psxRegs
+ .global nd_pcsx_io
+ .global psxH_ptr
.bss
.align 4
FCR31 = FCR0 + 4
.type FCR31, %object
.size FCR31, 4
-reg = FCR31 + 4
+psxRegs = FCR31 + 4
/* psxRegs */
-psxRegs = reg
+ .type psxRegs, %object
+ .size psxRegs, psxRegs_end-psxRegs
+reg = psxRegs
.type reg, %object
.size reg, 128
- .size psxRegs, psxRegs_end-psxRegs
lo = reg + 128
.type lo, %object
.size lo, 4
.size intCycle, 128
psxRegs_end = intCycle + 128
-align0 = psxRegs_end /* just for alignment */
+/* nd_pcsx_io */
+nd_pcsx_io = psxRegs_end
+ .type nd_pcsx_io, %object
+ .size nd_pcsx_io, nd_pcsx_io_end-nd_pcsx_io
+tab_read8 = nd_pcsx_io
+ .type tab_read8, %object
+ .size tab_read8, 4
+tab_read16 = tab_read8 + 4
+ .type tab_read16, %object
+ .size tab_read16, 4
+tab_read32 = tab_read16 + 4
+ .type tab_read32, %object
+ .size tab_read32, 4
+tab_write8 = tab_read32 + 4
+ .type tab_write8, %object
+ .size tab_write8, 4
+tab_write16 = tab_write8 + 4
+ .type tab_write16, %object
+ .size tab_write16, 4
+tab_write32 = tab_write16 + 4
+ .type tab_write32, %object
+ .size tab_write32, 4
+spu_readf = tab_write32 + 4
+ .type spu_readf, %object
+ .size spu_readf, 4
+spu_writef = spu_readf + 4
+ .type spu_writef, %object
+ .size spu_writef, 4
+nd_pcsx_io_end = spu_writef + 4
+
+psxH_ptr = nd_pcsx_io_end
+ .type psxH_ptr, %object
+ .size psxH_ptr, 4
+align0 = psxH_ptr + 4 /* just for alignment */
.type align0, %object
- .size align0, 8
-branch_target = align0 + 8
+ .size align0, 4
+branch_target = align0 + 4
.type branch_target, %object
.size branch_target, 4
mini_ht = branch_target + 4
.word dynarec_local
.size new_dyna_start, .-new_dyna_start
- .align 2
- .global write_rdram_new
- .type write_rdram_new, %function
-write_rdram_new:
- ldr r2, [fp, #address-dynarec_local]
- ldr r0, [fp, #word-dynarec_local]
- str r0, [r2]
- b .E12
- .size write_rdram_new, .-write_rdram_new
- .align 2
- .global write_rdramb_new
- .type write_rdramb_new, %function
-write_rdramb_new:
- ldr r2, [fp, #address-dynarec_local]
- ldrb r0, [fp, #byte-dynarec_local]
- eor r2, r2, #3
- strb r0, [r2]
- b .E12
- .size write_rdramb_new, .-write_rdramb_new
- .align 2
- .global write_rdramh_new
- .type write_rdramh_new, %function
-write_rdramh_new:
- ldr r2, [fp, #address-dynarec_local]
- ldrh r0, [fp, #hword-dynarec_local]
- eor r2, r2, #2
- strh r0, [r2]
- b .E12
- .size write_rdramh_new, .-write_rdramh_new
+/* --------------------------------------- */
- .align 2
- .global do_invalidate
- .type do_invalidate, %function
-do_invalidate:
- ldr r2, [fp, #address-dynarec_local]
-.E12:
- ldr r1, [fp, #invc_ptr-dynarec_local]
- lsr r0, r2, #12
- ldrb r2, [r1, r0]
- tst r2, r2
- beq invalidate_block
- mov pc, lr
- .size do_invalidate, .-do_invalidate
+.align 2
+.global ari_read_ram8
+.global ari_read_ram16
+.global ari_read_ram32
+.global ari_read_ram_mirror8
+.global ari_read_ram_mirror16
+.global ari_read_ram_mirror32
+.global ari_write_ram8
+.global ari_write_ram16
+.global ari_write_ram32
+.global ari_write_ram_mirror8
+.global ari_write_ram_mirror16
+.global ari_write_ram_mirror32
+.global ari_read_io8
+.global ari_read_io16
+.global ari_read_io32
+.global ari_write_io8
+.global ari_write_io16
+.global ari_write_io32
- .align 2
- .global read_nomem_new
- .type read_nomem_new, %function
-/*read_nomem_new:*/
-read_nomemb_new:
-read_nomemh_new:
-read_nomemd_new:
- /* should never happen */
- b read_nomem_new
-/*
- ldr r2, [fp, #address-dynarec_local]
- add r12, fp, #memory_map-dynarec_local
- lsr r0, r2, #12
- ldr r12, [r12, r0, lsl #2]
- mov r1, #8
- tst r12, r12
- bmi tlb_exception
- ldr r0, [r2, r12, lsl #2]
+.macro ari_read_ram bic_const op
+ ldr r0, [fp, #address-dynarec_local]
+.if \bic_const
+ bic r0, r0, #\bic_const
+.endif
+ \op r0, [r0]
str r0, [fp, #readmem_dword-dynarec_local]
mov pc, lr
-*/
- .size read_nomem_new, .-read_nomem_new
-/*
- .align 2
- .global read_nomemb_new
- .type read_nomemb_new, %function
-write_nomem_new:
- str r3, [fp, #24]
- str lr, [fp, #28]
- bl do_invalidate
- ldr r2, [fp, #address-dynarec_local]
- add r12, fp, #memory_map-dynarec_local
- ldr lr, [fp, #28]
- lsr r0, r2, #12
- ldr r3, [fp, #24]
- ldr r12, [r12, r0, lsl #2]
- mov r1, #0xc
- tst r12, #0x40000000
- bne tlb_exception
- ldr r0, [fp, #word-dynarec_local]
- str r0, [r2, r12, lsl #2]
+.endm
+
+ari_read_ram8:
+ ari_read_ram 0, ldrb
+
+ari_read_ram16:
+ ari_read_ram 1, ldrh
+
+ari_read_ram32:
+ ari_read_ram 3, ldr
+
+.macro ari_read_ram_mirror mvn_const, op
+ ldr r0, [fp, #address-dynarec_local]
+ mvn r1, #\mvn_const
+ and r0, r1, lsr #11
+ orr r0, r0, #1<<31
+ \op r0, [r0]
+ str r0, [fp, #readmem_dword-dynarec_local]
mov pc, lr
- .size write_nomem_new, .-write_nomem_new
+.endm
- .align 2
- .global write_nomemb_new
- .type write_nomemb_new, %function
-write_nomemb_new:
- str r3, [fp, #24]
- str lr, [fp, #28]
- bl do_invalidate
- ldr r2, [fp, #address-dynarec_local]
- add r12, fp, #memory_map-dynarec_local
- ldr lr, [fp, #28]
- lsr r0, r2, #12
- ldr r3, [fp, #24]
- ldr r12, [r12, r0, lsl #2]
- mov r1, #0xc
- tst r12, #0x40000000
- bne tlb_exception
- eor r2, r2, #3
- ldrb r0, [fp, #byte-dynarec_local]
- strb r0, [r2, r12, lsl #2]
+ari_read_ram_mirror8:
+ ari_read_ram_mirror 0, ldrb
+
+ari_read_ram_mirror16:
+ ari_read_ram_mirror (1<<11), ldrh
+
+ari_read_ram_mirror32:
+ ari_read_ram_mirror (3<<11), ldr
+
+/* invalidation is already taken care of by the caller */
+.macro ari_write_ram bic_const var op
+ ldr r0, [fp, #address-dynarec_local]
+ ldr r1, [fp, #\var-dynarec_local]
+.if \bic_const
+ bic r0, r0, #\bic_const
+.endif
+ \op r1, [r0]
mov pc, lr
- .size write_nomemb_new, .-write_nomemb_new
+.endm
- .align 2
- .global write_nomemh_new
- .type write_nomemh_new, %function
-write_nomemh_new:
- str r3, [fp, #24]
- str lr, [fp, #28]
- bl do_invalidate
- ldr r2, [fp, #address-dynarec_local]
- add r12, fp, #memory_map-dynarec_local
- ldr lr, [fp, #28]
- lsr r0, r2, #12
- ldr r3, [fp, #24]
- ldr r12, [r12, r0, lsl #2]
- mov r1, #0xc
- lsls r12, #2
- bcs tlb_exception
- eor r2, r2, #2
- ldrh r0, [fp, #hword-dynarec_local]
- strh r0, [r2, r12]
+ari_write_ram8:
+ ari_write_ram 0, byte, strb
+
+ari_write_ram16:
+ ari_write_ram 1, hword, strh
+
+ari_write_ram32:
+ ari_write_ram 3, word, str
+
+.macro ari_write_ram_mirror mvn_const var op
+ ldr r0, [fp, #address-dynarec_local]
+ mvn r3, #\mvn_const
+ ldr r1, [fp, #\var-dynarec_local]
+ and r0, r3, lsr #11
+ ldr r2, [fp, #invc_ptr-dynarec_local]
+ orr r0, r0, #1<<31
+ ldrb r2, [r2, r0, lsr #12]
+ \op r1, [r0]
+ tst r2, r2
+ movne pc, lr
+ lsr r0, r0, #12
+ b invalidate_block
+.endm
+
+ari_write_ram_mirror8:
+ ari_write_ram_mirror 0, byte, strb
+
+ari_write_ram_mirror16:
+ ari_write_ram_mirror (1<<11), hword, strh
+
+ari_write_ram_mirror32:
+ ari_write_ram_mirror (3<<11), word, str
+
+
+@ for testing
+.macro ari_read_io_old tab_shift
+ str lr, [sp, #-8]! @ EABI alignment..
+.if \tab_shift == 0
+ bl psxHwRead32
+.endif
+.if \tab_shift == 1
+ bl psxHwRead16
+.endif
+.if \tab_shift == 2
+ bl psxHwRead8
+.endif
+ str r0, [fp, #readmem_dword-dynarec_local]
+ ldr pc, [sp], #8
+.endm
+
+.macro ari_read_io readop mem_tab tab_shift
+ ldr r0, [fp, #address-dynarec_local]
+ ldr r1, [fp, #psxH_ptr-dynarec_local]
+.if \tab_shift == 0
+ bic r0, r0, #3
+.endif
+.if \tab_shift == 1
+ bic r0, r0, #1
+.endif
+ bic r2, r0, #0x1f800000
+ ldr r12,[fp, #\mem_tab-dynarec_local]
+ subs r3, r2, #0x1000
+ blo 2f
+@ ari_read_io_old \tab_shift
+ cmp r3, #0x880
+ bhs 1f
+ ldr r12,[r12, r3, lsl #\tab_shift]
+ tst r12,r12
+ beq 2f
+0:
+ str lr, [sp, #-8]! @ EABI alignment..
+ blx r12
+ str r0, [fp, #readmem_dword-dynarec_local]
+ ldr pc, [sp], #8
+
+1:
+.if \tab_shift == 1 @ read16
+ cmp r2, #0x1c00
+ blo 2f
+ cmp r2, #0x1e00
+ bhs 2f
+ ldr r12,[fp, #spu_readf-dynarec_local]
+ b 0b
+.endif
+2:
+ @ no handler, just read psxH
+ \readop r0, [r1, r2]
+ str r0, [fp, #readmem_dword-dynarec_local]
mov pc, lr
- .size write_nomemh_new, .-write_nomemh_new
-*/
- .align 2
- .global breakpoint
- .type breakpoint, %function
-breakpoint:
- /* Set breakpoint here for debugging */
+.endm
+
+ari_read_io8:
+ ari_read_io ldrb, tab_read8, 2
+
+ari_read_io16:
+ ari_read_io ldrh, tab_read16, 1
+
+ari_read_io32:
+ ari_read_io ldr, tab_read32, 0
+
+.macro ari_write_io_old tab_shift
+.if \tab_shift == 0
+ b psxHwWrite32
+.endif
+.if \tab_shift == 1
+ b psxHwWrite16
+.endif
+.if \tab_shift == 2
+ b psxHwWrite8
+.endif
+.endm
+
+.macro ari_write_io opvl opst var mem_tab tab_shift
+ ldr r0, [fp, #address-dynarec_local]
+ \opvl r1, [fp, #\var-dynarec_local]
+.if \tab_shift == 0
+ bic r0, r0, #3
+.endif
+.if \tab_shift == 1
+ bic r0, r0, #1
+.endif
+ bic r2, r0, #0x1f800000
+ ldr r12,[fp, #\mem_tab-dynarec_local]
+ subs r3, r2, #0x1000
+ blo 0f
+@ ari_write_io_old \tab_shift
+ cmp r3, #0x880
+ bhs 1f
+ ldr r12,[r12, r3, lsl #\tab_shift]
+ mov r0, r1
+ tst r12,r12
+ bxne r12
+0:
+ ldr r3, [fp, #psxH_ptr-dynarec_local]
+ \opst r1, [r2, r3]
mov pc, lr
- .size breakpoint, .-breakpoint
- .section .note.GNU-stack,"",%progbits
+1:
+.if \tab_shift == 1 @ write16
+ cmp r2, #0x1c00
+ blo 0b
+ cmp r2, #0x1e00
+ ldrlo pc, [fp, #spu_writef-dynarec_local]
+ nop
+.endif
+ b 0b
+.endm
+
+ari_write_io8:
+ ari_write_io ldrb, strb, byte, tab_write8, 2
+
+ari_write_io16:
+ ari_write_io ldrh, strh, hword, tab_write16, 1
+
+ari_write_io32:
+ ari_write_io ldr, str, word, tab_write32, 0
+
+@ vim:filetype=armasm
--- /dev/null
+/*
+ * (C) Gražvydas "notaz" Ignotas, 2010
+ *
+ * This work is licensed under the terms of GNU GPL version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include <stdio.h>
+#include "../psxhw.h"
+#include "../cdrom.h"
+#include "../mdec.h"
+#include "emu_if.h"
+#include "pcsxmem.h"
+
+//#define memprintf printf
+#define memprintf(...)
+
+static void read_mem8()
+{
+ memprintf("ari64_read_mem8 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
+ readmem_word = psxMemRead8(address) & 0xff;
+}
+
+static void read_mem16()
+{
+ memprintf("ari64_read_mem16 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
+ readmem_word = psxMemRead16(address) & 0xffff;
+}
+
+static void read_mem32()
+{
+ memprintf("ari64_read_mem32 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
+ readmem_word = psxMemRead32(address);
+}
+
+static void write_mem8()
+{
+ memprintf("ari64_write_mem8 %08x, %02x @%08x %u\n", address, byte, psxRegs.pc, psxRegs.cycle);
+ psxMemWrite8(address, byte);
+}
+
+static void write_mem16()
+{
+ memprintf("ari64_write_mem16 %08x, %04x @%08x %u\n", address, hword, psxRegs.pc, psxRegs.cycle);
+ psxMemWrite16(address, hword);
+}
+
+static void write_mem32()
+{
+ memprintf("ari64_write_mem32 %08x, %08x @%08x %u\n", address, word, psxRegs.pc, psxRegs.cycle);
+ psxMemWrite32(address, word);
+}
+
+static void read_mem_dummy()
+{
+ readmem_word = 0;
+}
+
+static void write_mem_dummy()
+{
+}
+
+extern void ari_read_ram8();
+extern void ari_read_ram16();
+extern void ari_read_ram32();
+extern void ari_read_ram_mirror8();
+extern void ari_read_ram_mirror16();
+extern void ari_read_ram_mirror32();
+extern void ari_write_ram8();
+extern void ari_write_ram16();
+extern void ari_write_ram32();
+extern void ari_write_ram_mirror8();
+extern void ari_write_ram_mirror16();
+extern void ari_write_ram_mirror32();
+extern void ari_read_io8();
+extern void ari_read_io16();
+extern void ari_read_io32();
+extern void ari_write_io8();
+extern void ari_write_io16();
+extern void ari_write_io32();
+
+void (*readmem[0x10000])();
+void (*readmemb[0x10000])();
+void (*readmemh[0x10000])();
+void (*writemem[0x10000])();
+void (*writememb[0x10000])();
+void (*writememh[0x10000])();
+
+/* IO handlers */
+static u32 io_read_sio16()
+{
+ return sioRead8() | (sioRead8() << 8);
+}
+
+static u32 io_read_sio32()
+{
+ return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24);
+}
+
+static void io_write_sio16(u32 value)
+{
+ sioWrite8((unsigned char)value);
+ sioWrite8((unsigned char)(value>>8));
+}
+
+static void io_write_sio32(u32 value)
+{
+ sioWrite8((unsigned char)value);
+ sioWrite8((unsigned char)((value&0xff) >> 8));
+ sioWrite8((unsigned char)((value&0xff) >> 16));
+ sioWrite8((unsigned char)((value&0xff) >> 24));
+}
+
+#define make_rcnt_funcs(i) \
+static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \
+static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \
+static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
+static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \
+static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); } \
+static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
+
+make_rcnt_funcs(0)
+make_rcnt_funcs(1)
+make_rcnt_funcs(2)
+
+static void io_write_ireg16(u32 value)
+{
+ if (Config.Sio) psxHu16ref(0x1070) |= 0x80;
+ if (Config.SpuIrq) psxHu16ref(0x1070) |= 0x200;
+ psxHu16ref(0x1070) &= psxHu16(0x1074) & value;
+}
+
+static void io_write_imask16(u32 value)
+{
+ psxHu16ref(0x1074) = value;
+ if (psxHu16ref(0x1070) & value)
+ new_dyna_set_event(6, 1);
+}
+
+static void io_write_ireg32(u32 value)
+{
+ if (Config.Sio) psxHu32ref(0x1070) |= 0x80;
+ if (Config.SpuIrq) psxHu32ref(0x1070) |= 0x200;
+ psxHu32ref(0x1070) &= psxHu32(0x1074) & value;
+}
+
+static void io_write_imask32(u32 value)
+{
+ psxHu32ref(0x1074) = value;
+ if (psxHu32ref(0x1070) & value)
+ new_dyna_set_event(6, 1);
+}
+
+static void io_write_dma_icr32(u32 value)
+{
+ u32 tmp = ~value & HW_DMA_ICR;
+ HW_DMA_ICR = ((tmp ^ value) & 0xffffff) ^ tmp;
+}
+
+#define make_dma_func(n) \
+static void io_write_chcr##n(u32 value) \
+{ \
+ HW_DMA##n##_CHCR = value; \
+ if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
+ psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
+ } \
+}
+
+make_dma_func(0)
+make_dma_func(1)
+make_dma_func(2)
+make_dma_func(3)
+make_dma_func(4)
+make_dma_func(6)
+
+/* IO tables for 1000-1880 */
+#define IOADR8(a) ((a) & 0xfff)
+#define IOADR16(a) (((a) & 0xfff) >> 1)
+#define IOADR32(a) (((a) & 0xfff) >> 2)
+
+static const void *io_read8 [0x880] = {
+ [IOADR8(0x1040)] = sioRead8,
+ [IOADR8(0x1800)] = cdrRead0,
+ [IOADR8(0x1801)] = cdrRead1,
+ [IOADR8(0x1802)] = cdrRead2,
+ [IOADR8(0x1803)] = cdrRead3,
+};
+static const void *io_read16[0x880/2] = {
+ [IOADR16(0x1040)] = io_read_sio16,
+ [IOADR16(0x1044)] = sioReadStat16,
+ [IOADR16(0x1048)] = sioReadMode16,
+ [IOADR16(0x104a)] = sioReadCtrl16,
+ [IOADR16(0x104e)] = sioReadBaud16,
+ [IOADR16(0x1100)] = io_rcnt_read_count0,
+ [IOADR16(0x1104)] = io_rcnt_read_mode0,
+ [IOADR16(0x1108)] = io_rcnt_read_target0,
+ [IOADR16(0x1110)] = io_rcnt_read_count1,
+ [IOADR16(0x1114)] = io_rcnt_read_mode1,
+ [IOADR16(0x1118)] = io_rcnt_read_target1,
+ [IOADR16(0x1120)] = io_rcnt_read_count2,
+ [IOADR16(0x1124)] = io_rcnt_read_mode2,
+ [IOADR16(0x1128)] = io_rcnt_read_target2,
+};
+static const void *io_read32[0x880/4] = {
+ [IOADR32(0x1040)] = io_read_sio32,
+ [IOADR32(0x1100)] = io_rcnt_read_count0,
+ [IOADR32(0x1104)] = io_rcnt_read_mode0,
+ [IOADR32(0x1108)] = io_rcnt_read_target0,
+ [IOADR32(0x1110)] = io_rcnt_read_count1,
+ [IOADR32(0x1114)] = io_rcnt_read_mode1,
+ [IOADR32(0x1118)] = io_rcnt_read_target1,
+ [IOADR32(0x1120)] = io_rcnt_read_count2,
+ [IOADR32(0x1124)] = io_rcnt_read_mode2,
+ [IOADR32(0x1128)] = io_rcnt_read_target2,
+// [IOADR32(0x1810)] = GPU_readData,
+// [IOADR32(0x1814)] = GPU_readStatus,
+ [IOADR32(0x1820)] = mdecRead0,
+ [IOADR32(0x1824)] = mdecRead1,
+};
+// write(u32 val)
+static const void *io_write8 [0x880] = {
+ [IOADR8(0x1040)] = sioWrite8,
+ [IOADR8(0x1800)] = cdrWrite0,
+ [IOADR8(0x1801)] = cdrWrite1,
+ [IOADR8(0x1802)] = cdrWrite2,
+ [IOADR8(0x1803)] = cdrWrite3,
+};
+static const void *io_write16[0x880/2] = {
+ [IOADR16(0x1040)] = io_write_sio16,
+ [IOADR16(0x1044)] = sioWriteStat16,
+ [IOADR16(0x1048)] = sioWriteMode16,
+ [IOADR16(0x104a)] = sioWriteCtrl16,
+ [IOADR16(0x104e)] = sioWriteBaud16,
+ [IOADR16(0x1070)] = io_write_ireg16,
+ [IOADR16(0x1074)] = io_write_imask16,
+ [IOADR16(0x1100)] = io_rcnt_write_count0,
+ [IOADR16(0x1104)] = io_rcnt_write_mode0,
+ [IOADR16(0x1108)] = io_rcnt_write_target0,
+ [IOADR16(0x1110)] = io_rcnt_write_count1,
+ [IOADR16(0x1114)] = io_rcnt_write_mode1,
+ [IOADR16(0x1118)] = io_rcnt_write_target1,
+ [IOADR16(0x1120)] = io_rcnt_write_count2,
+ [IOADR16(0x1124)] = io_rcnt_write_mode2,
+ [IOADR16(0x1128)] = io_rcnt_write_target2,
+};
+static const void *io_write32[0x880/4] = {
+ [IOADR32(0x1040)] = io_write_sio32,
+ [IOADR32(0x1070)] = io_write_ireg32,
+ [IOADR32(0x1074)] = io_write_imask32,
+ [IOADR32(0x1088)] = io_write_chcr0,
+ [IOADR32(0x1098)] = io_write_chcr1,
+ [IOADR32(0x10a8)] = io_write_chcr2,
+ [IOADR32(0x10b8)] = io_write_chcr3,
+ [IOADR32(0x10c8)] = io_write_chcr4,
+ [IOADR32(0x10e8)] = io_write_chcr6,
+ [IOADR32(0x10f4)] = io_write_dma_icr32,
+ [IOADR32(0x1100)] = io_rcnt_write_count0,
+ [IOADR32(0x1104)] = io_rcnt_write_mode0,
+ [IOADR32(0x1108)] = io_rcnt_write_target0,
+ [IOADR32(0x1110)] = io_rcnt_write_count1,
+ [IOADR32(0x1114)] = io_rcnt_write_mode1,
+ [IOADR32(0x1118)] = io_rcnt_write_target1,
+ [IOADR32(0x1120)] = io_rcnt_write_count2,
+ [IOADR32(0x1124)] = io_rcnt_write_mode2,
+ [IOADR32(0x1128)] = io_rcnt_write_target2,
+// [IOADR32(0x1810)] = GPU_writeData,
+// [IOADR32(0x1814)] = GPU_writeStatus,
+ [IOADR32(0x1820)] = mdecWrite0,
+ [IOADR32(0x1824)] = mdecWrite1,
+};
+
+// this has to be in .bss to link into dynarec_local
+struct {
+ void *tab_read8;
+ void *tab_read16;
+ void *tab_read32;
+ void *tab_write8;
+ void *tab_write16;
+ void *tab_write32;
+ void *spu_readf;
+ void *spu_writef;
+} nd_pcsx_io;
+
+void new_dyna_pcsx_mem_init(void)
+{
+ int i;
+
+ // default/unmapped handlers
+ for (i = 0; i < 0x10000; i++) {
+ readmemb[i] = read_mem8;
+ readmemh[i] = read_mem16;
+ readmem[i] = read_mem32;
+ writememb[i] = write_mem8;
+ writememh[i] = write_mem16;
+ writemem[i] = write_mem32;
+#if 1
+ readmemb[i] = readmemh[i] = readmem[i] = read_mem_dummy;
+ readmemb[i] = readmemh[i] = readmem[i] = write_mem_dummy;
+#endif
+ }
+
+#if 1
+ // RAM mirrors
+ for (i = 0; i < 0x80; i++) {
+ readmemb[i] = readmemb[0x8000|i] = readmemb[0xa000|i] = ari_read_ram_mirror8;
+ readmemh[i] = readmemh[0x8000|i] = readmemh[0xa000|i] = ari_read_ram_mirror16;
+ readmem[i] = readmem [0x8000|i] = readmem [0xa000|i] = ari_read_ram_mirror32;
+ writememb[i] = writememb[0x8000|i] = writememb[0xa000|i] = ari_write_ram_mirror8;
+ writememh[i] = writememh[0x8000|i] = writememh[0xa000|i] = ari_write_ram_mirror16;
+ writemem[i] = writemem [0x8000|i] = writemem [0xa000|i] = ari_write_ram_mirror32;
+ }
+
+ // RAM direct
+ for (i = 0x8000; i < 0x8020; i++) {
+ readmemb[i] = ari_read_ram8;
+ readmemh[i] = ari_read_ram16;
+ readmem[i] = ari_read_ram32;
+ writememb[i] = ari_write_ram8;
+ writememh[i] = ari_write_ram16;
+ writemem[i] = ari_write_ram32;
+ }
+
+ // I/O
+ readmemb[0x1f80] = ari_read_io8;
+ readmemh[0x1f80] = ari_read_io16;
+ readmem[0x1f80] = ari_read_io32;
+ writememb[0x1f80] = ari_write_io8;
+ writememh[0x1f80] = ari_write_io16;
+ writemem[0x1f80] = ari_write_io32;
+
+ writemem[0xfffe] = write_mem32;
+#endif
+
+ // fill IO tables
+ nd_pcsx_io.tab_read8 = io_read8;
+ nd_pcsx_io.tab_read16 = io_read16;
+ nd_pcsx_io.tab_read32 = io_read32;
+ nd_pcsx_io.tab_write8 = io_write8;
+ nd_pcsx_io.tab_write16 = io_write16;
+ nd_pcsx_io.tab_write32 = io_write32;
+}
+
+void new_dyna_pcsx_mem_reset(void)
+{
+ // plugins might change so update the pointers
+ nd_pcsx_io.spu_readf = SPU_readRegister;
+ nd_pcsx_io.spu_writef = SPU_writeRegister;
+
+ io_read32[IOADR32(0x1810)] = GPU_readData;
+ io_read32[IOADR32(0x1814)] = GPU_readStatus;
+ io_write32[IOADR32(0x1810)] = GPU_writeData;
+ io_write32[IOADR32(0x1814)] = GPU_writeStatus;
+}
+
--- /dev/null
+
+void new_dyna_pcsx_mem_init(void);
+void new_dyna_pcsx_mem_reset(void);
notaz.gp2x.de / pcsx_rearmed.git / commitdiff