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drc: adjust bogus looking check
authornotaz <notasas@gmail.com>
Wed, 10 Nov 2021 21:44:25 +0000 (23:44 +0200)
committernotaz <notasas@gmail.com>
Sun, 14 Nov 2021 00:05:06 +0000 (02:05 +0200)
not really sure what's going on, but at the start of
"Pass 3 - Register allocation" zero reg allocations are removed,
so "regmap_pre[i+1][hr] != regs[i].regmap[hr]" assert will not hold.


No differences found
ARM optimized PCSX fork