From: notaz Date: Tue, 8 Mar 2011 14:09:02 +0000 (+0200) Subject: pcsxmem: fix ro write handler X-Git-Tag: r8~22 X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=commitdiff_plain;h=274c424338d914fdc0076306c769ba4fadeebdaa;ds=sidebyside pcsxmem: fix ro write handler also refactor things a bit (as usual) --- diff --git a/libpcsxcore/new_dynarec/linkage_arm.s b/libpcsxcore/new_dynarec/linkage_arm.s index 57fb3d22..6107e270 100644 --- a/libpcsxcore/new_dynarec/linkage_arm.s +++ b/libpcsxcore/new_dynarec/linkage_arm.s @@ -203,6 +203,15 @@ memory_map = restore_candidate + 512 .size memory_map, 4194304 dynarec_local_end = memory_map + 4194304 +.macro load_var_adr reg var +.if HAVE_ARMV7 + movw \reg, #:lower16:\var + movt \reg, #:upper16:\var +.else + ldr \reg, =\var +.endif +.endm + .text .align 2 .global dyna_linker @@ -856,12 +865,7 @@ invalidate_addr_call: new_dyna_start: /* ip is stored to conform EABI alignment */ stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr} -.if HAVE_ARMV7 - movw fp, #:lower16:dynarec_local - movt fp, #:upper16:dynarec_local -.else - ldr fp, .dlptr -.endif + load_var_adr fp, dynarec_local ldr r0, [fp, #pcaddr-dynarec_local] bl get_addr_ht ldr r1, [fp, #next_interupt-dynarec_local] @@ -869,8 +873,6 @@ new_dyna_start: str r1, [fp, #last_count-dynarec_local] sub r10, r10, r1 mov pc, r0 -.dlptr: - .word dynarec_local .size new_dyna_start, .-new_dyna_start /* --------------------------------------- */ @@ -888,6 +890,7 @@ new_dyna_start: .global ari_write_ram_mirror8 .global ari_write_ram_mirror16 .global ari_write_ram_mirror32 +.global ari_write_ram_mirror_ro32 .global ari_read_bios8 .global ari_read_bios16 .global ari_read_bios32 @@ -980,6 +983,14 @@ ari_write_ram_mirror16: ari_write_ram_mirror32: ari_write_ram_mirror (3<<11), word, +ari_write_ram_mirror_ro32: + load_var_adr r0, pcsx_ram_is_ro + ldr r0, [r0] + tst r0, r0 + movne pc, lr + nop + b ari_write_ram_mirror32 + .macro ari_read_bios_mirror bic_const op ldr r0, [fp, #address-dynarec_local] diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c index ae35f2df..8b6714bf 100644 --- a/libpcsxcore/new_dynarec/pcsxmem.c +++ b/libpcsxcore/new_dynarec/pcsxmem.c @@ -1,5 +1,5 @@ /* - * (C) Gražvydas "notaz" Ignotas, 2010 + * (C) Gražvydas "notaz" Ignotas, 2010-2011 * * This work is licensed under the terms of GNU GPL version 2 or later. * See the COPYING file in the top-level directory. @@ -15,7 +15,7 @@ //#define memprintf printf #define memprintf(...) -static int ram_is_ro; +int pcsx_ram_is_ro; static void read_mem8() { @@ -74,6 +74,7 @@ extern void ari_write_ram32(); extern void ari_write_ram_mirror8(); extern void ari_write_ram_mirror16(); extern void ari_write_ram_mirror32(); +extern void ari_write_ram_mirror_ro32(); extern void ari_read_bios8(); extern void ari_read_bios16(); extern void ari_read_bios32(); @@ -91,12 +92,6 @@ void (*writemem[0x10000])(); void (*writememb[0x10000])(); void (*writememh[0x10000])(); -static void write_mem_check_ro32() -{ - if (!ram_is_ro) - *(u32 *)(address | 0x80000000) = word; -} - static void write_biu() { memprintf("write_biu %08x, %08x @%08x %u\n", address, word, psxRegs.pc, psxRegs.cycle); @@ -106,10 +101,10 @@ static void write_biu() switch (word) { case 0x800: case 0x804: - ram_is_ro = 1; + pcsx_ram_is_ro = 1; break; case 0: case 0x1e988: - ram_is_ro = 0; + pcsx_ram_is_ro = 0; break; default: memprintf("write_biu: unexpected val: %08x\n", word); @@ -342,8 +337,8 @@ void new_dyna_pcsx_mem_init(void) } // stupid BIOS RAM check - writemem[0] = write_mem_check_ro32; - ram_is_ro = 0; + writemem[0] = ari_write_ram_mirror_ro32; + pcsx_ram_is_ro = 0; // RAM direct for (i = 0x8000; i < 0x8020; i++) { diff --git a/libpcsxcore/new_dynarec/pcsxmem_inline.c b/libpcsxcore/new_dynarec/pcsxmem_inline.c index 90dafa05..30338eb8 100644 --- a/libpcsxcore/new_dynarec/pcsxmem_inline.c +++ b/libpcsxcore/new_dynarec/pcsxmem_inline.c @@ -104,7 +104,7 @@ static int pcsx_direct_write(int type, u_int addr, int rs, int rt, signed char * int ir=get_reg(regmap,INVCP); assert(ir>=0); - emit_cmpmem_indexedsr12_reg(ir,rs,1); + emit_cmpmem_indexedsr12_reg(ir,HOST_TEMPREG,1); emit_callne(invalidate_addr_reg[rs]); return 1; }