From: notaz Date: Sun, 15 Apr 2012 16:49:49 +0000 (+0300) Subject: support emulated RAM mapped at offset X-Git-Tag: r15~55 X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=commitdiff_plain;h=a327ad27099341fb6eed61aa0419dff418429f96 support emulated RAM mapped at offset Thanks to CatalystG for some initial code and testing. --- diff --git a/Makefile b/Makefile index 5f65f384..f08d9d76 100644 --- a/Makefile +++ b/Makefile @@ -11,6 +11,7 @@ ARM926 ?= 0 ARM_CORTEXA8 ?= 1 PLATFORM ?= pandora USE_OSS ?= 1 +RAM_FIXED ?= 1 #USE_ALSA = 1 #DRC_DBG = 1 #PCNT = 1 @@ -75,6 +76,9 @@ ifdef DRC_DBG libpcsxcore/new_dynarec/emu_if.o: CFLAGS += -D_FILE_OFFSET_BITS=64 CFLAGS += -DDRC_DBG endif +ifeq "$(RAM_FIXED)" "1" +CFLAGS += -DRAM_FIXED +endif # spu OBJS += plugins/dfsound/dma.o plugins/dfsound/freeze.o \ diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c index 0b7cee82..a88b396b 100644 --- a/libpcsxcore/new_dynarec/assem_arm.c +++ b/libpcsxcore/new_dynarec/assem_arm.c @@ -29,7 +29,7 @@ #include "pcnt.h" #endif -#ifndef BASE_ADDR_FIXED +#if !BASE_ADDR_FIXED char translation_cache[1 << TARGET_SIZE_2] __attribute__((aligned(4096))); #endif @@ -4001,6 +4001,10 @@ static int emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override) else #endif emit_jno(0); + if(ram_offset!=0) { + emit_addimm(addr,ram_offset,HOST_TEMPREG); + addr=*addr_reg_override=HOST_TEMPREG; + } } return jaddr; @@ -4052,6 +4056,10 @@ void loadlr_assemble_arm(int i,struct regstat *i_regs) jaddr=emit_fastpath_cmp_jump(i,temp2,&fastload_reg_override); } else { + if(ram_offset&&memtarget) { + emit_addimm(temp2,ram_offset,HOST_TEMPREG); + fastload_reg_override=HOST_TEMPREG; + } if (opcode[i]==0x22||opcode[i]==0x26) { emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR }else{ diff --git a/libpcsxcore/new_dynarec/assem_arm.h b/libpcsxcore/new_dynarec/assem_arm.h index 7ed8caff..0148a953 100644 --- a/libpcsxcore/new_dynarec/assem_arm.h +++ b/libpcsxcore/new_dynarec/assem_arm.h @@ -22,8 +22,12 @@ //#undef USE_MINI_HT #endif +#ifndef BASE_ADDR_FIXED #ifndef __ANDROID__ #define BASE_ADDR_FIXED 1 +#else +#define BASE_ADDR_FIXED 0 +#endif #endif #ifdef FORCE32 @@ -61,13 +65,10 @@ extern char *invc_ptr; #define TARGET_SIZE_2 24 // 2^24 = 16 megabytes // Code generator target address -#ifdef BASE_ADDR_FIXED +#if BASE_ADDR_FIXED // "round" address helpful for debug #define BASE_ADDR 0x1000000 #else extern char translation_cache[1 << TARGET_SIZE_2]; #define BASE_ADDR translation_cache #endif - -// This is defined in linkage_arm.s, but gcc -O3 likes this better -#define rdram ((unsigned int *)0x80000000) diff --git a/libpcsxcore/new_dynarec/emu_if.h b/libpcsxcore/new_dynarec/emu_if.h index 6b6305cf..72f6c27f 100644 --- a/libpcsxcore/new_dynarec/emu_if.h +++ b/libpcsxcore/new_dynarec/emu_if.h @@ -97,3 +97,9 @@ void pcsx_mtc0_ds(u32 reg, u32 val); /* misc */ extern void (*psxHLEt[])(); + +#ifdef RAM_FIXED +#define rdram ((u_int)0x80000000) +#else +#define rdram ((u_int)psxM) +#endif diff --git a/libpcsxcore/new_dynarec/linkage_arm.s b/libpcsxcore/new_dynarec/linkage_arm.s index 5c1adc9f..bd5a03d4 100644 --- a/libpcsxcore/new_dynarec/linkage_arm.s +++ b/libpcsxcore/new_dynarec/linkage_arm.s @@ -21,8 +21,6 @@ /* .equiv HAVE_ARMV7, 1 */ - .global rdram -rdram = 0x80000000 .global dynarec_local .global reg .global hi diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index cafa4a42..a736d565 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -141,6 +141,11 @@ struct ll_entry int new_dynarec_did_compile; int new_dynarec_hacks; u_int stop_after_jal; +#ifndef RAM_FIXED + static u_int ram_offset; +#else + static const u_int ram_offset=0; +#endif extern u_char restore_candidate[512]; extern int cycle_count; @@ -2917,6 +2922,10 @@ void load_assemble(int i,struct regstat *i_regs) jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override); } } + else if(ram_offset&&memtarget) { + emit_addimm(addr,ram_offset,HOST_TEMPREG); + fastload_reg_override=HOST_TEMPREG; + } }else{ // using tlb int x=0; if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU @@ -2982,7 +2991,7 @@ void load_assemble(int i,struct regstat *i_regs) gen_tlb_addr_r(a,map); emit_movswl_indexed(x,a,tl); }else{ - #ifdef RAM_OFFSET + #if 1 //def RAM_OFFSET emit_movswl_indexed(x,a,tl); #else emit_movswl_indexed((int)rdram-0x80000000+x,a,tl); @@ -3069,7 +3078,7 @@ void load_assemble(int i,struct regstat *i_regs) gen_tlb_addr_r(a,map); emit_movzwl_indexed(x,a,tl); }else{ - #ifdef RAM_OFFSET + #if 1 //def RAM_OFFSET emit_movzwl_indexed(x,a,tl); #else emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl); @@ -3226,6 +3235,10 @@ void store_assemble(int i,struct regstat *i_regs) jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override); #endif } + else if(ram_offset&&memtarget) { + emit_addimm(addr,ram_offset,HOST_TEMPREG); + faststore_reg_override=HOST_TEMPREG; + } }else{ // using tlb int x=0; if (opcode[i]==0x28) x=3; // SB @@ -3270,7 +3283,8 @@ void store_assemble(int i,struct regstat *i_regs) gen_tlb_addr_w(a,map); emit_writehword_indexed(tl,x,a); }else - emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a); + //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a); + emit_writehword_indexed(tl,x,a); } type=STOREH_STUB; } @@ -3874,6 +3888,10 @@ void c2ls_assemble(int i,struct regstat *i_regs) if(!c) { jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override); } + else if(ram_offset&&memtarget) { + emit_addimm(ar,ram_offset,HOST_TEMPREG); + fastio_reg_override=HOST_TEMPREG; + } if (opcode[i]==0x32) { // LWC2 #ifdef HOST_IMM_ADDR32 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl); @@ -7993,7 +8011,7 @@ void new_dynarec_init() { printf("Init new dynarec\n"); out=(u_char *)BASE_ADDR; -#ifdef BASE_ADDR_FIXED +#if BASE_ADDR_FIXED if (mmap (out, 1<