From 045a4c528a71e5513acc2cfb8a77e31efcad5d87 Mon Sep 17 00:00:00 2001 From: notaz Date: Mon, 5 Aug 2013 02:31:47 +0300 Subject: [PATCH] 32x: move sh2 peripheral emu code to it's own file also adds 16byte dma --- pico/32x/32x.c | 4 +- pico/32x/memory.c | 345 +---------------------------- pico/32x/pwm.c | 55 +---- pico/32x/sh2soc.c | 436 +++++++++++++++++++++++++++++++++++++ pico/pico_int.h | 17 +- platform/common/common.mak | 2 +- 6 files changed, 460 insertions(+), 399 deletions(-) create mode 100644 pico/32x/sh2soc.c diff --git a/pico/32x/32x.c b/pico/32x/32x.c index 7a4d7b3..a6f0a51 100644 --- a/pico/32x/32x.c +++ b/pico/32x/32x.c @@ -74,6 +74,7 @@ void Pico32xStartup(void) ssh2.irq_callback = sh2_irq_cb; PicoMemSetup32x(); + p32x_pwm_ctl_changed(); p32x_timers_recalc(); if (!Pico.m.pal) @@ -172,6 +173,7 @@ void PicoReset32x(void) p32x_update_irls(NULL); p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0); p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0); + p32x_pwm_ctl_changed(); p32x_timers_recalc(); } } @@ -433,7 +435,7 @@ void sync_sh2s_normal(unsigned int m68k_target) } } - p32x_timers_do(now, now - timer_cycles); + p32x_timers_do(now - timer_cycles); timer_cycles = now; } diff --git a/pico/32x/memory.c b/pico/32x/memory.c index 6d6bbb7..2c62e11 100644 --- a/pico/32x/memory.c +++ b/pico/32x/memory.c @@ -171,213 +171,6 @@ static u32 sh2_comm_faker(u32 a) } #endif -// DMAC handling -struct dma_chan { - unsigned int sar, dar; // src, dst addr - unsigned int tcr; // transfer count - unsigned int chcr; // chan ctl - // -- dm dm sm sm ts ts ar am al ds dl tb ta ie te de - // ts - transfer size: 1, 2, 4, 16 bytes - // ar - auto request if 1, else dreq signal - // ie - irq enable - // te - transfer end - // de - dma enable - #define DMA_AR (1 << 9) - #define DMA_IE (1 << 2) - #define DMA_TE (1 << 1) - #define DMA_DE (1 << 0) -}; - -struct dmac { - struct dma_chan chan[2]; - unsigned int vcrdma0; - unsigned int unknown0; - unsigned int vcrdma1; - unsigned int unknown1; - unsigned int dmaor; - // -- pr ae nmif dme - // pr - priority: chan0 > chan1 or round-robin - // ae - address error - // nmif - nmi occurred - // dme - DMA master enable - #define DMA_DME (1 << 0) -}; - -static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan) -{ - char *regs = (void *)Pico32xMem->sh2_peri_regs[sh2->is_slave]; - struct dmac *dmac = (void *)(regs + 0x180); - int level = PREG8(regs, 0xe2) & 0x0f; // IPRA - int vector = (chan == &dmac->chan[0]) ? - dmac->vcrdma0 : dmac->vcrdma1; - - elprintf(EL_32X, "dmac irq %d %d", level, vector); - sh2_internal_irq(sh2, level, vector & 0x7f); -} - -static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan) -{ - chan->chcr |= DMA_TE; // DMA has ended normally - - p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDoneT()); - if (chan->chcr & DMA_IE) - dmac_te_irq(sh2, chan); -} - -static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan) -{ - u32 size, d; - - size = (chan->chcr >> 10) & 3; - switch (size) { - case 0: - d = p32x_sh2_read8(chan->sar, sh2); - p32x_sh2_write8(chan->dar, d, sh2); - case 1: - d = p32x_sh2_read16(chan->sar, sh2); - p32x_sh2_write16(chan->dar, d, sh2); - break; - case 2: - d = p32x_sh2_read32(chan->sar, sh2); - p32x_sh2_write32(chan->dar, d, sh2); - break; - case 3: - elprintf(EL_32X|EL_ANOMALY, "TODO: 16byte DMA"); - chan->sar += 16; // always? - chan->tcr -= 4; - return; - } - chan->tcr--; - - size = 1 << size; - if (chan->chcr & (1 << 15)) - chan->dar -= size; - if (chan->chcr & (1 << 14)) - chan->dar += size; - if (chan->chcr & (1 << 13)) - chan->sar -= size; - if (chan->chcr & (1 << 12)) - chan->sar += size; -} - -static void dreq0_do(SH2 *sh2, struct dma_chan *chan) -{ - unsigned short *dreqlen = &Pico32x.regs[0x10 / 2]; - int i; - - // debug/sanity checks - if (chan->tcr != *dreqlen) - elprintf(EL_32X|EL_ANOMALY, "dreq0: tcr0 and len differ: %d != %d", - chan->tcr, *dreqlen); - // note: DACK is not connected, single addr mode should not be used - if ((chan->chcr & 0x3f08) != 0x0400) - elprintf(EL_32X|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr); - if (chan->sar != 0x20004012) - elprintf(EL_32X|EL_ANOMALY, "dreq0: bad sar?: %08x\n", chan->sar); - - // HACK: assume bus is busy and SH2 is halted - sh2->state |= SH2_STATE_SLEEP; - - for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) { - elprintf(EL_32X, "dmaw [%08x] %04x, left %d", - chan->dar, Pico32x.dmac_fifo[i], *dreqlen); - p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2); - chan->dar += 2; - chan->tcr--; - (*dreqlen)--; - } - - if (Pico32x.dmac0_fifo_ptr != i) - memmove(Pico32x.dmac_fifo, &Pico32x.dmac_fifo[i], - (Pico32x.dmac0_fifo_ptr - i) * 2); - Pico32x.dmac0_fifo_ptr -= i; - - Pico32x.regs[6 / 2] &= ~P32XS_FULL; - if (*dreqlen == 0) - Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete - if (chan->tcr == 0) - dmac_transfer_complete(sh2, chan); - else - sh2_end_run(sh2, 16); -} - -static void dreq1_do(SH2 *sh2, struct dma_chan *chan) -{ - // debug/sanity checks - if ((chan->chcr & 0xc308) != 0x0000) - elprintf(EL_32X|EL_ANOMALY, "dreq1: bad control: %04x", chan->chcr); - if ((chan->dar & ~0xf) != 0x20004030) - elprintf(EL_32X|EL_ANOMALY, "dreq1: bad dar?: %08x\n", chan->dar); - - dmac_transfer_one(sh2, chan); - if (chan->tcr == 0) - dmac_transfer_complete(sh2, chan); -} - -static void dreq0_trigger(void) -{ - struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4]; - struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4]; - - elprintf(EL_32X, "dreq0_trigger\n"); - if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) { - dreq0_do(&msh2, &mdmac->chan[0]); - } - if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[0].chcr & 3) == DMA_DE) { - dreq0_do(&ssh2, &sdmac->chan[0]); - } -} - -void p32x_dreq1_trigger(void) -{ - struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4]; - struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4]; - int hit = 0; - - elprintf(EL_32X, "dreq1_trigger\n"); - if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[1].chcr & 3) == DMA_DE) { - dreq1_do(&msh2, &mdmac->chan[1]); - hit = 1; - } - if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[1].chcr & 3) == DMA_DE) { - dreq1_do(&ssh2, &sdmac->chan[1]); - hit = 1; - } - - if (!hit) - elprintf(EL_32X|EL_ANOMALY, "dreq1: nobody cared"); -} - -// DMA trigger by SH2 register write -static void dmac_trigger(SH2 *sh2, struct dma_chan *chan) -{ - elprintf(EL_32X, "sh2 DMA %08x->%08x, cnt %d, chcr %04x @%06x", - chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc); - chan->tcr &= 0xffffff; - - if (chan->chcr & DMA_AR) { - // auto-request transfer - while ((int)chan->tcr > 0) - dmac_transfer_one(sh2, chan); - dmac_transfer_complete(sh2, chan); - return; - } - - // DREQ0 is only sent after first 4 words are written. - // we do multiple of 4 words to avoid messing up alignment - if (chan->sar == 0x20004012) { - if (Pico32x.dmac0_fifo_ptr && (Pico32x.dmac0_fifo_ptr & 3) == 0) { - elprintf(EL_32X, "68k -> sh2 DMA"); - dreq0_trigger(); - } - return; - } - - elprintf(EL_32X|EL_ANOMALY, "unhandled DMA: " - "%08x->%08x, cnt %d, chcr %04x @%06x", - chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc); -} - // ------------------------------------------------------------------ // 68k regs @@ -518,7 +311,7 @@ static void p32x_reg_write16(u32 a, u32 d) if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) { Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d; if ((Pico32x.dmac0_fifo_ptr & 3) == 0) - dreq0_trigger(); + p32x_dreq0_trigger(); if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN) r[6 / 2] |= P32XS_FULL; } @@ -765,142 +558,6 @@ irls: p32x_update_irls(&sh2s[cpuid]); } -// ------------------------------------------------------------------ -// SH2 internal peripherals -// we keep them in little endian format -static u32 sh2_peripheral_read8(u32 a, int id) -{ - u8 *r = (void *)Pico32xMem->sh2_peri_regs[id]; - u32 d; - - a &= 0x1ff; - d = PREG8(r, a); - - elprintf(EL_32X, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id)); - return d; -} - -static u32 sh2_peripheral_read16(u32 a, int id) -{ - u16 *r = (void *)Pico32xMem->sh2_peri_regs[id]; - u32 d; - - a &= 0x1ff; - d = r[(a / 2) ^ 1]; - - elprintf(EL_32X, "%csh2 peri r16 [%08x] %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id)); - return d; -} - -static u32 sh2_peripheral_read32(u32 a, int id) -{ - u32 d; - a &= 0x1fc; - d = Pico32xMem->sh2_peri_regs[id][a / 4]; - - elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id)); - return d; -} - -static int REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, int id) -{ - u8 *r = (void *)Pico32xMem->sh2_peri_regs[id]; - elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id)); - - a &= 0x1ff; - PREG8(r, a) = d; - - // X-men SCI hack - if ((a == 2 && (d & 0x20)) || // transmiter enabled - (a == 4 && !(d & 0x80))) { // valid data in TDR - void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1]; - if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled - int level = PREG8(oregs, 0x60) >> 4; - int vector = PREG8(oregs, 0x63) & 0x7f; - elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector); - sh2_internal_irq(&sh2s[id ^ 1], level, vector); - return 1; - } - } - return 0; -} - -static int REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, int id) -{ - u16 *r = (void *)Pico32xMem->sh2_peri_regs[id]; - elprintf(EL_32X, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id)); - - a &= 0x1ff; - - // evil WDT - if (a == 0x80) { - if ((d & 0xff00) == 0xa500) { // WTCSR - PREG8(r, 0x80) = d; - p32x_timers_recalc(); - } - if ((d & 0xff00) == 0x5a00) // WTCNT - PREG8(r, 0x81) = d; - return 0; - } - - r[(a / 2) ^ 1] = d; - return 0; -} - -static void sh2_peripheral_write32(u32 a, u32 d, int id) -{ - u32 *r = Pico32xMem->sh2_peri_regs[id]; - elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id)); - - a &= 0x1fc; - r[a / 4] = d; - - switch (a) { - // division unit (TODO: verify): - case 0x104: // DVDNT: divident L, starts divide - elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]); - if (r[0x100 / 4]) { - signed int divisor = r[0x100 / 4]; - r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor; - r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor; - } - else - r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ? - break; - case 0x114: - elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x", - id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id)); - if (r[0x100 / 4]) { - signed long long divident = (signed long long)r[0x110 / 4] << 32 | d; - signed int divisor = r[0x100 / 4]; - // XXX: undocumented mirroring to 0x118,0x11c? - r[0x118 / 4] = r[0x110 / 4] = divident % divisor; - divident /= divisor; - r[0x11c / 4] = r[0x114 / 4] = divident; - divident >>= 31; - if ((unsigned long long)divident + 1 > 1) { - //elprintf(EL_32X, "%csh2 divide overflow! @%08x", id ? 's' : 'm', sh2_pc(id)); - r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow - } - } - else - r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ? - break; - } - - // perhaps starting a DMA? - if (a == 0x1b0 || a == 0x18c || a == 0x19c) { - struct dmac *dmac = (void *)&Pico32xMem->sh2_peri_regs[id][0x180 / 4]; - if (!(dmac->dmaor & DMA_DME)) - return; - - if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE) - dmac_trigger(&sh2s[id], &dmac->chan[0]); - if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE) - dmac_trigger(&sh2s[id], &dmac->chan[1]); - } -} - // ------------------------------------------------------------------ // 32x handlers diff --git a/pico/32x/pwm.c b/pico/32x/pwm.c index 5684924..dc7c4d6 100644 --- a/pico/32x/pwm.c +++ b/pico/32x/pwm.c @@ -12,15 +12,10 @@ static int pwm_mult; static int pwm_ptr; static int pwm_irq_reload; -static int timer_cycles[2]; -static int timer_tick_cycles[2]; - -// timers. This includes PWM timer in 32x and internal SH2 timers -void p32x_timers_recalc(void) +void p32x_pwm_ctl_changed(void) { int control = Pico32x.regs[0x30 / 2]; int cycles = Pico32x.regs[0x32 / 2]; - int tmp, i; cycles = (cycles - 1) & 0x0fff; pwm_cycles = cycles; @@ -31,18 +26,6 @@ void p32x_timers_recalc(void) if (Pico32x.pwm_irq_cnt == 0) Pico32x.pwm_irq_cnt = pwm_irq_reload; - - // SH2 timer step - for (i = 0; i < 2; i++) { - tmp = PREG8(Pico32xMem->sh2_peri_regs[i], 0x80) & 7; - // Sclk cycles per timer tick - if (tmp) - cycles = 0x20 << tmp; - else - cycles = 2; - timer_tick_cycles[i] = cycles; - elprintf(EL_32X, "WDT cycles[%d] = %d", i, cycles); - } } static void do_pwm_irq(unsigned int m68k_cycles) @@ -118,36 +101,6 @@ static void consume_fifo_do(unsigned int m68k_cycles, int sh2_cycles_diff) do_pwm_irq(m68k_cycles); } -void p32x_timers_do(unsigned int m68k_now, unsigned int m68k_slice) -{ - unsigned int cycles = m68k_slice * 3; - int cnt, i; - - //consume_fifo(m68k_now); - - // WDT timers - for (i = 0; i < 2; i++) { - void *pregs = Pico32xMem->sh2_peri_regs[i]; - if (PREG8(pregs, 0x80) & 0x20) { // TME - timer_cycles[i] += cycles; - cnt = PREG8(pregs, 0x81); - while (timer_cycles[i] >= timer_tick_cycles[i]) { - timer_cycles[i] -= timer_tick_cycles[i]; - cnt++; - } - if (cnt >= 0x100) { - int level = PREG8(pregs, 0xe3) >> 4; - int vector = PREG8(pregs, 0xe4) & 0x7f; - elprintf(EL_32X, "%csh2 WDT irq (%d, %d)", - i ? 's' : 'm', level, vector); - sh2_internal_irq(&sh2s[i], level, vector); - cnt &= 0xff; - } - PREG8(pregs, 0x81) = cnt; - } - } -} - static int p32x_pwm_schedule_(unsigned int m68k_now) { unsigned int sh2_now = m68k_now * 3; @@ -236,12 +189,12 @@ void p32x_pwm_write16(unsigned int a, unsigned int d, // supposedly we should stop FIFO when xMd is 0, // but mars test disagrees Pico32x.regs[0x30 / 2] = d; - p32x_timers_recalc(); + p32x_pwm_ctl_changed(); Pico32x.pwm_irq_cnt = pwm_irq_reload; // ? } else if (a == 2) { // cycle Pico32x.regs[0x32 / 2] = d & 0x0fff; - p32x_timers_recalc(); + p32x_pwm_ctl_changed(); } else if (a <= 8) { d = (d - 1) & 0x0fff; @@ -332,7 +285,7 @@ void p32x_pwm_state_loaded(void) { int cycles_diff_sh2; - p32x_timers_recalc(); + p32x_pwm_ctl_changed(); // for old savestates cycles_diff_sh2 = SekCycleCntT * 3 - Pico32x.pwm_cycle_p; diff --git a/pico/32x/sh2soc.c b/pico/32x/sh2soc.c new file mode 100644 index 0000000..ab4ac52 --- /dev/null +++ b/pico/32x/sh2soc.c @@ -0,0 +1,436 @@ +/* + * SH2 peripherals/"system on chip" + * (C) notaz, 2013 + * + * This work is licensed under the terms of MAME license. + * See COPYING file in the top-level directory. + * + * rough fffffe00-ffffffff map: + * e00-e05 SCI serial communication interface + * e10-e1a FRT free-running timer + * e60-e68 VCRx irq vectors + * e71-e72 DRCR dma selection + * e80-e83 WDT watchdog timer + * e91 SBYCR standby control + * e92 CCR cache control + * ee0 ICR irq control + * ee2 IPRA irq priorities + * ee4 VCRWDT WDT irq vectors + * f00-f17 DIVU + * f40-f7b UBC user break controller + * f80-fb3 DMAC + * fe0-ffb BSC bus state controller + */ + +#include "../pico_int.h" +#include "../memory.h" + +// DMAC handling +struct dma_chan { + unsigned int sar, dar; // src, dst addr + unsigned int tcr; // transfer count + unsigned int chcr; // chan ctl + // -- dm dm sm sm ts ts ar am al ds dl tb ta ie te de + // ts - transfer size: 1, 2, 4, 16 bytes + // ar - auto request if 1, else dreq signal + // ie - irq enable + // te - transfer end + // de - dma enable + #define DMA_AR (1 << 9) + #define DMA_IE (1 << 2) + #define DMA_TE (1 << 1) + #define DMA_DE (1 << 0) +}; + +struct dmac { + struct dma_chan chan[2]; + unsigned int vcrdma0; + unsigned int unknown0; + unsigned int vcrdma1; + unsigned int unknown1; + unsigned int dmaor; + // -- pr ae nmif dme + // pr - priority: chan0 > chan1 or round-robin + // ae - address error + // nmif - nmi occurred + // dme - DMA master enable + #define DMA_DME (1 << 0) +}; + +static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan) +{ + char *regs = (void *)Pico32xMem->sh2_peri_regs[sh2->is_slave]; + struct dmac *dmac = (void *)(regs + 0x180); + int level = PREG8(regs, 0xe2) & 0x0f; // IPRA + int vector = (chan == &dmac->chan[0]) ? + dmac->vcrdma0 : dmac->vcrdma1; + + elprintf(EL_32XP, "dmac irq %d %d", level, vector); + sh2_internal_irq(sh2, level, vector & 0x7f); +} + +static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan) +{ + chan->chcr |= DMA_TE; // DMA has ended normally + + p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDoneT()); + if (chan->chcr & DMA_IE) + dmac_te_irq(sh2, chan); +} + +static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan) +{ + u32 size, d; + + size = (chan->chcr >> 10) & 3; + switch (size) { + case 0: + d = p32x_sh2_read8(chan->sar, sh2); + p32x_sh2_write8(chan->dar, d, sh2); + case 1: + d = p32x_sh2_read16(chan->sar, sh2); + p32x_sh2_write16(chan->dar, d, sh2); + break; + case 2: + d = p32x_sh2_read32(chan->sar, sh2); + p32x_sh2_write32(chan->dar, d, sh2); + break; + case 3: + d = p32x_sh2_read32(chan->sar + 0x00, sh2); + p32x_sh2_write32(chan->dar + 0x00, d, sh2); + d = p32x_sh2_read32(chan->sar + 0x04, sh2); + p32x_sh2_write32(chan->dar + 0x04, d, sh2); + d = p32x_sh2_read32(chan->sar + 0x08, sh2); + p32x_sh2_write32(chan->dar + 0x08, d, sh2); + d = p32x_sh2_read32(chan->sar + 0x0c, sh2); + p32x_sh2_write32(chan->dar + 0x0c, d, sh2); + chan->sar += 16; // always? + if (chan->chcr & (1 << 15)) + chan->dar -= 16; + if (chan->chcr & (1 << 14)) + chan->dar += 16; + chan->tcr -= 4; + return; + } + chan->tcr--; + + size = 1 << size; + if (chan->chcr & (1 << 15)) + chan->dar -= size; + if (chan->chcr & (1 << 14)) + chan->dar += size; + if (chan->chcr & (1 << 13)) + chan->sar -= size; + if (chan->chcr & (1 << 12)) + chan->sar += size; +} + +// DMA trigger by SH2 register write +static void dmac_trigger(SH2 *sh2, struct dma_chan *chan) +{ + elprintf(EL_32XP, "sh2 DMA %08x->%08x, cnt %d, chcr %04x @%06x", + chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc); + chan->tcr &= 0xffffff; + + if (chan->chcr & DMA_AR) { + // auto-request transfer + while ((int)chan->tcr > 0) + dmac_transfer_one(sh2, chan); + dmac_transfer_complete(sh2, chan); + return; + } + + // DREQ0 is only sent after first 4 words are written. + // we do multiple of 4 words to avoid messing up alignment + if (chan->sar == 0x20004012) { + if (Pico32x.dmac0_fifo_ptr && (Pico32x.dmac0_fifo_ptr & 3) == 0) { + elprintf(EL_32XP, "68k -> sh2 DMA"); + p32x_dreq0_trigger(); + } + return; + } + + elprintf(EL_32XP|EL_ANOMALY, "unhandled DMA: " + "%08x->%08x, cnt %d, chcr %04x @%06x", + chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc); +} + +// timer state - FIXME +static int timer_cycles[2]; +static int timer_tick_cycles[2]; + +// timers +void p32x_timers_recalc(void) +{ + int cycles; + int tmp, i; + + // SH2 timer step + for (i = 0; i < 2; i++) { + tmp = PREG8(Pico32xMem->sh2_peri_regs[i], 0x80) & 7; + // Sclk cycles per timer tick + if (tmp) + cycles = 0x20 << tmp; + else + cycles = 2; + timer_tick_cycles[i] = cycles; + timer_cycles[i] = 0; + elprintf(EL_32XP, "WDT cycles[%d] = %d", i, cycles); + } +} + +void p32x_timers_do(unsigned int m68k_slice) +{ + unsigned int cycles = m68k_slice * 3; + int cnt, i; + + // WDT timers + for (i = 0; i < 2; i++) { + void *pregs = Pico32xMem->sh2_peri_regs[i]; + if (PREG8(pregs, 0x80) & 0x20) { // TME + timer_cycles[i] += cycles; + cnt = PREG8(pregs, 0x81); + while (timer_cycles[i] >= timer_tick_cycles[i]) { + timer_cycles[i] -= timer_tick_cycles[i]; + cnt++; + } + if (cnt >= 0x100) { + int level = PREG8(pregs, 0xe3) >> 4; + int vector = PREG8(pregs, 0xe4) & 0x7f; + elprintf(EL_32XP, "%csh2 WDT irq (%d, %d)", + i ? 's' : 'm', level, vector); + sh2_internal_irq(&sh2s[i], level, vector); + cnt &= 0xff; + } + PREG8(pregs, 0x81) = cnt; + } + } +} + +// ------------------------------------------------------------------ +// SH2 internal peripheral memhandlers +// we keep them in little endian format + +u32 sh2_peripheral_read8(u32 a, int id) +{ + u8 *r = (void *)Pico32xMem->sh2_peri_regs[id]; + u32 d; + + a &= 0x1ff; + d = PREG8(r, a); + + elprintf(EL_32XP, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id)); + return d; +} + +u32 sh2_peripheral_read16(u32 a, int id) +{ + u16 *r = (void *)Pico32xMem->sh2_peri_regs[id]; + u32 d; + + a &= 0x1ff; + d = r[(a / 2) ^ 1]; + + elprintf(EL_32XP, "%csh2 peri r16 [%08x] %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id)); + return d; +} + +u32 sh2_peripheral_read32(u32 a, int id) +{ + u32 d; + a &= 0x1fc; + d = Pico32xMem->sh2_peri_regs[id][a / 4]; + + elprintf(EL_32XP, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id)); + return d; +} + +int REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, int id) +{ + u8 *r = (void *)Pico32xMem->sh2_peri_regs[id]; + elprintf(EL_32XP, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id)); + + a &= 0x1ff; + PREG8(r, a) = d; + + // X-men SCI hack + if ((a == 2 && (d & 0x20)) || // transmiter enabled + (a == 4 && !(d & 0x80))) { // valid data in TDR + void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1]; + if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled + int level = PREG8(oregs, 0x60) >> 4; + int vector = PREG8(oregs, 0x63) & 0x7f; + elprintf(EL_32XP, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector); + sh2_internal_irq(&sh2s[id ^ 1], level, vector); + return 1; + } + } + return 0; +} + +int REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, int id) +{ + u16 *r = (void *)Pico32xMem->sh2_peri_regs[id]; + elprintf(EL_32XP, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id)); + + a &= 0x1ff; + + // evil WDT + if (a == 0x80) { + if ((d & 0xff00) == 0xa500) { // WTCSR + PREG8(r, 0x80) = d; + p32x_timers_recalc(); + } + if ((d & 0xff00) == 0x5a00) // WTCNT + PREG8(r, 0x81) = d; + return 0; + } + + r[(a / 2) ^ 1] = d; + return 0; +} + +void sh2_peripheral_write32(u32 a, u32 d, int id) +{ + u32 *r = Pico32xMem->sh2_peri_regs[id]; + elprintf(EL_32XP, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id)); + + a &= 0x1fc; + r[a / 4] = d; + + switch (a) { + // division unit (TODO: verify): + case 0x104: // DVDNT: divident L, starts divide + elprintf(EL_32XP, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]); + if (r[0x100 / 4]) { + signed int divisor = r[0x100 / 4]; + r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor; + r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor; + } + else + r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ? + break; + case 0x114: + elprintf(EL_32XP, "%csh2 divide %08x%08x / %08x @%08x", + id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id)); + if (r[0x100 / 4]) { + signed long long divident = (signed long long)r[0x110 / 4] << 32 | d; + signed int divisor = r[0x100 / 4]; + // XXX: undocumented mirroring to 0x118,0x11c? + r[0x118 / 4] = r[0x110 / 4] = divident % divisor; + divident /= divisor; + r[0x11c / 4] = r[0x114 / 4] = divident; + divident >>= 31; + if ((unsigned long long)divident + 1 > 1) { + //elprintf(EL_32XP, "%csh2 divide overflow! @%08x", id ? 's' : 'm', sh2_pc(id)); + r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow + } + } + else + r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ? + break; + } + + // perhaps starting a DMA? + if (a == 0x1b0 || a == 0x18c || a == 0x19c) { + struct dmac *dmac = (void *)&Pico32xMem->sh2_peri_regs[id][0x180 / 4]; + if (!(dmac->dmaor & DMA_DME)) + return; + + if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE) + dmac_trigger(&sh2s[id], &dmac->chan[0]); + if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE) + dmac_trigger(&sh2s[id], &dmac->chan[1]); + } +} + +/* 32X specific */ +static void dreq0_do(SH2 *sh2, struct dma_chan *chan) +{ + unsigned short *dreqlen = &Pico32x.regs[0x10 / 2]; + int i; + + // debug/sanity checks + if (chan->tcr != *dreqlen) + elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0 and len differ: %d != %d", + chan->tcr, *dreqlen); + // note: DACK is not connected, single addr mode should not be used + if ((chan->chcr & 0x3f08) != 0x0400) + elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr); + if (chan->sar != 0x20004012) + elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad sar?: %08x\n", chan->sar); + + // HACK: assume bus is busy and SH2 is halted + sh2->state |= SH2_STATE_SLEEP; + + for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) { + elprintf(EL_32XP, "dmaw [%08x] %04x, left %d", + chan->dar, Pico32x.dmac_fifo[i], *dreqlen); + p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2); + chan->dar += 2; + chan->tcr--; + (*dreqlen)--; + } + + if (Pico32x.dmac0_fifo_ptr != i) + memmove(Pico32x.dmac_fifo, &Pico32x.dmac_fifo[i], + (Pico32x.dmac0_fifo_ptr - i) * 2); + Pico32x.dmac0_fifo_ptr -= i; + + Pico32x.regs[6 / 2] &= ~P32XS_FULL; + if (*dreqlen == 0) + Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete + if (chan->tcr == 0) + dmac_transfer_complete(sh2, chan); + else + sh2_end_run(sh2, 16); +} + +static void dreq1_do(SH2 *sh2, struct dma_chan *chan) +{ + // debug/sanity checks + if ((chan->chcr & 0xc308) != 0x0000) + elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad control: %04x", chan->chcr); + if ((chan->dar & ~0xf) != 0x20004030) + elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad dar?: %08x\n", chan->dar); + + dmac_transfer_one(sh2, chan); + if (chan->tcr == 0) + dmac_transfer_complete(sh2, chan); +} + +void p32x_dreq0_trigger(void) +{ + struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4]; + struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4]; + + elprintf(EL_32XP, "dreq0_trigger"); + if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) { + dreq0_do(&msh2, &mdmac->chan[0]); + } + if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[0].chcr & 3) == DMA_DE) { + dreq0_do(&ssh2, &sdmac->chan[0]); + } +} + +void p32x_dreq1_trigger(void) +{ + struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4]; + struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4]; + int hit = 0; + + elprintf(EL_32XP, "dreq1_trigger"); + if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[1].chcr & 3) == DMA_DE) { + dreq1_do(&msh2, &mdmac->chan[1]); + hit = 1; + } + if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[1].chcr & 3) == DMA_DE) { + dreq1_do(&ssh2, &sdmac->chan[1]); + hit = 1; + } + + if (!hit) + elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared"); +} + +// vim:shiftwidth=2:ts=2:expandtab diff --git a/pico/pico_int.h b/pico/pico_int.h index 08e3769..6566532 100644 --- a/pico/pico_int.h +++ b/pico/pico_int.h @@ -781,12 +781,24 @@ extern int Pico32xDrawMode; unsigned int p32x_pwm_read16(unsigned int a, unsigned int cycles); void p32x_pwm_write16(unsigned int a, unsigned int d, unsigned int cycles); void p32x_pwm_update(int *buf32, int length, int stereo); -void p32x_timers_do(unsigned int m68k_now, unsigned int m68k_slice); -void p32x_timers_recalc(void); +void p32x_pwm_ctl_changed(void); void p32x_pwm_schedule(unsigned int m68k_now); void p32x_pwm_schedule_sh2(SH2 *sh2); void p32x_pwm_irq_event(unsigned int m68k_now); void p32x_pwm_state_loaded(void); + +// 32x/sh2soc.c +void p32x_dreq0_trigger(void); +void p32x_dreq1_trigger(void); +void p32x_timers_recalc(void); +void p32x_timers_do(unsigned int m68k_slice); +unsigned int sh2_peripheral_read8(unsigned int a, int id); +unsigned int sh2_peripheral_read16(unsigned int a, int id); +unsigned int sh2_peripheral_read32(unsigned int a, int id); +int sh2_peripheral_write8(unsigned int a, unsigned int d, int id); +int sh2_peripheral_write16(unsigned int a, unsigned int d, int id); +void sh2_peripheral_write32(unsigned int a, unsigned int d, int id); + #else #define Pico32xInit() #define PicoPower32x() @@ -839,6 +851,7 @@ static __inline int isspace_(int c) #define EL_CDREG3 0x00040000 /* MCD: register 3 only */ #define EL_32X 0x00080000 #define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */ +#define EL_32XP 0x00200000 /* 32X peripherals */ #define EL_STATUS 0x40000000 /* status messages */ #define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */ diff --git a/platform/common/common.mak b/platform/common/common.mak index 6376dca..17e540f 100644 --- a/platform/common/common.mak +++ b/platform/common/common.mak @@ -92,7 +92,7 @@ SRCS_COMMON += $(R)pico/cd/pico.c $(R)pico/cd/memory.c $(R)pico/cd/sek.c \ # 32X ifneq "$(no_32x)" "1" SRCS_COMMON += $(R)pico/32x/32x.c $(R)pico/32x/memory.c $(R)pico/32x/draw.c \ - $(R)pico/32x/pwm.c + $(R)pico/32x/sh2soc.c $(R)pico/32x/pwm.c else DEFINES += NO_32X endif -- 2.39.2