0x00000000 - 0x00027fff RAM 0x00028000 - 0x0002ffff scratchpad RAM 0? [.=3,7] 0x000.0000 - 0x000.7fff scratchpad RAM 1? 0x000.8000 - 0x000.9fff scratchpad RAM 3? 0x000.a000 - 0x000.bfff scratchpad RAM 2? 0x000.c000 - 0x000.dfff scratchpad RAM 3? 0x000.e000 - 0x000.ffff ??? not writeble? [.=4,5,6] 0x000.0000 - 0x000.1fff scratchpad RAM 1? 0x000.2000 - 0x000.7fff ??? not writeble? 0x000.8000 - 0x000.ffff scratchpad RAM 0? 0x00300000 - 0x0030ffff registers 0x003C0000 - ? PHY_BASE /* 0000 - HOST_SLAVE_BASE */ 0x0000 ACX_REG_SLV_SOFT_RESET, /* 0400 - INT_BASE */ 0x0474 ACX_REG_INTERRUPT_TRIG, 0x0478 ACX_REG_INTERRUPT_TRIG_H, 0x0494 ACX_REG_INTERRUPT_MASK, 0x0498 ACX_REG_HINT_MASK_SET, 0x049C ACX_REG_HINT_MASK_CLR, 0x04B0 ACX_REG_INTERRUPT_NO_CLEAR, 0x04A4 ACX_REG_INTERRUPT_CLEAR, 0x04A8 ACX_REG_INTERRUPT_ACK, /* 0800 - REG_CONFIG_BASE */ 0x0800 SOR_CFG 0x0804 ACX_REG_ECPU_CONTROL, ECPU_CTRL 0x0808 HI_CFG 0x080C ACX_REG_EE_START, EE_START 0x0810 SYSTEM 0x0814 PCI_ARB_CFG 0x0818 BOOT_IRAM_CFG 0x0820 EE_CFG - SEEPROM? 0x0994 SPARE_A1 0x0998 SPARE_A2 0x099C SPARE_A3 0x09A0 SPARE_A4 0x09A4 SPARE_A5 0x09A8 SPARE_A6 0x09AC SPARE_A7 0x09B0 SPARE_A8 /* 0C00 - CLK_BASE */ /* 1000 - SDMA_BASE */ /* 1400 - AES_BASE */ /* 1800 - WEP_BASE */ /* 1C00 - TKIP_BASE */ /* 2000 - SEEPROM_BASE (2K) */ 0x2000 EE_CTL 0x2004 EE_DATA 0x2008 EE_ADDR /* 2400 - PAR_HOST_BASE */ /* 2800 - SDIO_BASE */ /* 2C00 - UART_BASE */ /* 4000 - USB11_BASE */ /* 4400 - LDMA_BASE */ /* 4800 - RX_BASE */ /* 4c00 - ACCESS_BASE */ /* 5000 - TX_BASE */ /* 5400 - RMAC_CSR_BASE */ 0x5420 SPARE_B1 0x5424 SPARE_B2 0x5428 SPARE_B3 0x542C SPARE_B4 0x5430 SPARE_B5 0x5434 SPARE_B6 0x5438 SPARE_B7 0x543C SPARE_B8 0x5450 ENABLE 0x546c STA_ADDR_L 0x5470 STA_ADDR_H /* Scratch Pad registers*/ 0x5608 SCR_PAD0 - Ptr to Firmware NVS Data 0x560C SCR_PAD1 - Offset to NVS Pointer Table 0x5610 SCR_PAD2 0x5614 SCR_PAD3 0x5618 SCR_PAD4, ACX_EEPROMLESS_IND_REG 0x561C SCR_PAD4_SET 0x5620 SCR_PAD4_CLR 0x5624 SCR_PAD5 0x5628 SCR_PAD5_SET 0x562C SCR_PAD5_CLR 0x5630 SCR_PAD6 0x5634 SCR_PAD7 0x5638 SCR_PAD8 0x563C SCR_PAD9 0x5674 CHIP_ID_B /* 5800 - AFE_PM */ 0x5804 ELP_CFG_MODE 0x5808 ELP_CMD 0x5810 PLL_CAL_TIME 0x5814 CLK_REQ_TIME, CLK_REQ - External clock settling time 0x5818 CLK_BUF_TIME 0x5820 CFG_PLL_SYNC_CNT /* 8000 - VLYNQ_BASE */ /* 8400 - PCI_BASE */ /* A000 - USB20_BASE */ /* fixed */ 0x1FFC0 HW_ACCESS_PART0_SIZE_ADDR 0x1FFC4 HW_ACCESS_PART0_START_ADDR 0x1FFC8 HW_ACCESS_PART1_SIZE_ADDR 0x1FFCC HW_ACCESS_PART1_START_ADDR 0x1FFFC HW_ACCESS_ELP_CTRL_REG_ADDR Host Bus Interface: 6 SDIO Radio ID: 1c // SoC TNETW1251 EEPROM Major Ver: 6 Support for b/g only -> 0; a/b/g -> 1 SCR_PAD2 Ref Dsn ID: 166 // EEPROM minor ver: 3 EEPROM default data ver: 7 SCR_PAD3 Ref Freq [MHz]: 0->19.2, 1->26, 2->38.4 Clk Source Type: 0->IO Buffer, 1-> Reserved; 2->Ref Clock, 3-> Crystal Ref Freq Offset: Max is +/- 50ppm (LSB) Format: 2's complement in 0.1ppm units => -500 to +500 (MSB) SCR_PAD6 0 - DVPS, 1 - HDK, 2 - DVPC, 3 - DVPC_LIGHT, 4 - HDK_V2 Bit0 ->0 not used,1 - PD Cal on/off default(on),PG1.2:Bit4-Bin offset,Bit5-Toggle(off),Bit6-ADC bias,Bit7-LNB Bit0 : B band FE chip sel (0 - PG 1.0 & 2.0, 1 - PG 3.0), Bit1: A band FE chip sel (0 - PG 1.0, 1 - PG 2.0) 0 - VCO default 1.55,1- VCO 1.35, 2- VCO 1.45, 3- VCO 1.55 SCR_PAD7 /*============================================= Host Interrupt Mask Register - 32bit (RW) ------------------------------------------ Setting a bit in this register masks the corresponding interrupt to the host. 0 - RX0 - Rx first dubble buffer Data Interrupt 1 - TXD - Tx Data Interrupt 2 - TXXFR - Tx Transfer Interrupt 3 - RX1 - Rx second dubble buffer Data Interrupt 4 - RXXFR - Rx Transfer Interrupt 5 - EVENT_A - Event Mailbox interrupt 6 - EVENT_B - Event Mailbox interrupt 7 - WNONHST - Wake On Host Interrupt 8 - TRACE_A - Debug Trace interrupt 9 - TRACE_B - Debug Trace interrupt 10 - CDCMP - Command Complete Interrupt 11 - 12 - 13 - 14 - ICOMP - Initialization Complete Interrupt 16 - SG SE - Soft Gemini - Sense enable interrupt 17 - SG SD - Soft Gemini - Sense disable interrupt 18 - - 19 - - 20 - - 21- - Default: 0x0001 *==============================================*/ ACX_REG_INTERRUPT_MASK /*============================================= Host Interrupt Mask Set 16bit, (Write only) ------------------------------------------ Setting a bit in this register sets the corresponding bin in ACX_HINT_MASK register without effecting the mask state of other bits (0 = no effect). ==============================================*/ ACX_HINT_MASK_SET_REG /*============================================= Host Interrupt Mask Clear 16bit,(Write only) ------------------------------------------ Setting a bit in this register clears the corresponding bin in ACX_HINT_MASK register without effecting the mask state of other bits (0 = no effect). =============================================*/ ACX_HINT_MASK_CLR_REG /*============================================= Host Interrupt Status Nondestructive Read 16bit,(Read only) ------------------------------------------ The host can read this register to determine which interrupts are active. Reading this register doesn't effect its content. =============================================*/ ACX_REG_INTERRUPT_NO_CLEAR /*============================================= Host Interrupt Status Clear on Read Register 16bit,(Read only) ------------------------------------------ The host can read this register to determine which interrupts are active. Reading this register clears it, thus making all interrupts inactive. ==============================================*/ ACX_REG_INTERRUPT_CLEAR /*============================================= Host Interrupt Acknowledge Register 16bit,(Write only) ------------------------------------------ The host can set individual bits in this register to clear (acknowledge) the corresp. interrupt status bits in the HINT_STS_CLR and HINT_STS_ND registers, thus making the assotiated interrupt inactive. (0-no effect) ==============================================*/ ACX_REG_INTERRUPT_ACK /*=============================================== Host Software Reset - 32bit RW ------------------------------------------ [31:1] Reserved 0 SOFT_RESET Soft Reset - When this bit is set, it holds the Wlan hardware in a soft reset state. This reset disables all MAC and baseband processor clocks except the CardBus/PCI interface clock. It also initializes all MAC state machines except the host interface. It does not reload the contents of the EEPROM. When this bit is cleared (not self-clearing), the Wlan hardware exits the software reset state. ===============================================*/ ACX_REG_SLV_SOFT_RESET /*=============================================== EEPROM Burst Read Start - 32bit RW ------------------------------------------ [31:1] Reserved 0 ACX_EE_START - EEPROM Burst Read Start 0 Setting this bit starts a burst read from the external EEPROM. If this bit is set (after reset) before an EEPROM read/write, the burst read starts at EEPROM address 0. Otherwise, it starts at the address following the address of the previous access. TheWlan hardware hardware clears this bit automatically. Default: 0x00000000 *================================================*/ ACX_REG_EE_START /*======================================================================= Embedded ARM CPU Control ========================================================================*/ /*=============================================== Halt eCPU - 32bit RW ------------------------------------------ 0 HALT_ECPU Halt Embedded CPU - This bit is the compliment of bit 1 (MDATA2) in the SOR_CFG register. During a hardware reset, this bit holds the inverse of MDATA2. When downloading firmware from the host, set this bit (pull down MDATA2). The host clears this bit after downloading the firmware into zero-wait-state SSRAM. When loading firmware from Flash, clear this bit (pull up MDATA2) so that the eCPU can run the bootloader code in Flash HALT_ECPU eCPU State -------------------- 1 halt eCPU 0 enable eCPU ===============================================*/ ACX_REG_ECPU_CONTROL /*======================================================================= Command/Information Mailbox Pointers ========================================================================*/ /*=============================================== Command Mailbox Pointer - 32bit RW ------------------------------------------ This register holds the start address of the command mailbox located in the Wlan hardware memory. The host must read this pointer after a reset to find the location of the command mailbox. The Wlan hardware initializes the command mailbox pointer with the default address of the command mailbox. The command mailbox pointer is not valid until after the host receives the Init Complete interrupt from the Wlan hardware. ===============================================*/ REG_COMMAND_MAILBOX_PTR ( SCR_PAD0 ) /*=============================================== Information Mailbox Pointer - 32bit RW ------------------------------------------ This register holds the start address of the information mailbox located in the Wlan hardware memory. The host must read this pointer after a reset to find the location of the information mailbox. The Wlan hardware initializes the information mailbox pointer with the default address of the information mailbox. The information mailbox pointer is not valid until after the host receives the Init Complete interrupt from the Wlan hardware. ===============================================*/ REG_EVENT_MAILBOX_PTR ( SCR_PAD1 ) /*=============================================== EEPROM Read/Write Request 32bit RW ------------------------------------------ 1 EE_READ - EEPROM Read Request 1 - Setting this bit loads a single byte of data into the EE_DATA register from the EEPROM location specified in the EE_ADDR register. The Wlan hardware hardware clears this bit automatically. EE_DATA is valid when this bit is cleared. 0 EE_WRITE - EEPROM Write Request - Setting this bit writes a single byte of data from the EE_DATA register into the EEPROM location specified in the EE_ADDR register. The Wlan hardware hardware clears this bit automatically. *===============================================*/ #define ACX_EE_CTL_REG EE_CTL #define EE_WRITE 0x00000001ul #define EE_READ 0x00000002ul /*=============================================== EEPROM Address - 32bit RW ------------------------------------------ This register specifies the address within the EEPROM from/to which to read/write data. ===============================================*/ #define ACX_EE_ADDR_REG EE_ADDR /*=============================================== EEPROM Data - 32bit RW ------------------------------------------ This register either holds the read 8 bits of data from the EEPROM or the write data to be written to the EEPROM. ===============================================*/ #define ACX_EE_DATA_REG EE_DATA /*=============================================== EEPROM Base Address - 32bit RW ------------------------------------------ This register holds the upper nine bits [23:15] of the 24-bit Wlan hardware memory address for burst reads from EEPROM accesses. The EEPROM provides the lower 15 bits of this address. The MSB of the address from the EEPROM is ignored. ===============================================*/ #define ACX_EE_CFG EE_CFG /*=============================================== GPIO Output Values -32bit, RW ------------------------------------------ [31:16] Reserved [15: 0] Specify the output values (at the output driver inputs) for GPIO[15:0], respectively. ===============================================*/ #define ACX_GPIO_OUT_REG GPIO_OUT #define ACX_MAX_GPIO_LINES 15 /*=============================================== Contention window -32bit, RW ------------------------------------------ [31:26] Reserved [25:16] Max (0x3ff) [15:07] Reserved [06:00] Current contention window value - default is 0x1F ===============================================*/ #define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG #define ACX_CONT_WIND_MIN_MASK 0x0000007f #define ACX_CONT_WIND_MAX 0x03ff0000 /*=============================================== HI_CFG Interface Configuration Register Values ------------------------------------------ ===============================================*/ #define HI_CFG_UART_ENABLE 0x00000004 #define HI_CFG_RST232_ENABLE 0x00000008 #define HI_CFG_CLOCK_REQ_SELECT 0x00000010 #define HI_CFG_HOST_INT_ENABLE 0x00000020 #define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040 #define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080 #define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100 #define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200 #define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400 HW_ACCESS_ELP_CTRL_REG_ADDR 0: WLAN_WUP (w) - wake up 1: WLAN_RDY (r) 2: IRQ_SRC (rw) - 0 host irq, 1 wlan ready