avoid using msr

causes pipeline flush on newer ARMs, and we don't want that

diff --git a/OpArith.cpp b/OpArith.cpp
index d762049..ca279da 100644 (file)
--- a/OpArith.cpp
+++ b/OpArith.cpp
@@ -373,7 +373,7 @@ int GetXBit(int subtract)
   ot(";@ Get X bit:\n");\r
   ot("  ldr r2,[r7,#0x4c]\n");\r
   if (subtract) ot("  mvn r2,r2 ;@ Invert it\n");\r
-  ot("  msr cpsr_flg,r2 ;@ Get into Carry\n");\r
+  ot("  tst r2,r2,lsl #3 ;@ Get into Carry\n");\r
   ot("\n");\r
   return 0;\r
 }\r

diff --git a/OpBranch.cpp b/OpBranch.cpp
index fb4f561..051c373 100644 (file)
--- a/OpBranch.cpp
+++ b/OpBranch.cpp
@@ -312,6 +312,7 @@ static const char * const Cond[16]=
 // Emit a Dbra opcode, 0101cccc 11001nnn vv\r
 int OpDbra(int op)\r
 {\r
+  const char *cond;\r
   int use=0;\r
   int cc=0;\r
 \r
@@ -321,25 +322,12 @@ int OpDbra(int op)
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
   OpStart(op);\r
 \r
-  switch (cc)\r
+  if (cc>=2)\r
   {\r
-    case 0: // T\r
-    case 1: // F\r
-      break;\r
-    case 2: // hi\r
-      ot("  tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
-      ot("  beq DbraTrue\n\n");\r
-      break;\r
-    case 3: // ls\r
-      ot("  tst r10,#0x60000000 ;@ ls: C || Z\n");\r
-      ot("  bne DbraTrue\n\n");\r
-      break;\r
-    default:\r
-      ot(";@ Is the condition true?\n");\r
-      ot("  msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
-      ot(";@ If so, don't dbra\n");\r
-      ot("  b%s DbraTrue\n\n",Cond[cc]);\r
-      break;\r
+    ot(";@ Is the condition true?\n");\r
+    cond=TestCond(cc);\r
+    ot(";@ If so, don't dbra\n");\r
+    ot("  b%s DbraTrue\n\n",cond);\r
   }\r
 \r
   if (cc!=0)\r
@@ -419,6 +407,7 @@ int OpBranch(int op)
   int offset=0;\r
   int cc=0;\r
   const char *asr_r11="";\r
+  const char *cond;\r
   int pc_reg=0;\r
 \r
   offset=(char)(op&0xff);\r
@@ -436,24 +425,10 @@ int OpBranch(int op)
   OpStart(op,size?0x10:0);\r
   Cycles=10; // Assume branch taken\r
 \r
-  switch (cc)\r
+  if (cc>=2)\r
   {\r
-    case 0: // T\r
-    case 1: // F\r
-      break;\r
-    case 2: // hi\r
-      ot("  tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
-      ot("  bne BccDontBranch%i\n\n",8<<size);\r
-      break;\r
-    case 3: // ls\r
-      ot("  tst r10,#0x60000000 ;@ ls: C || Z\n");\r
-      ot("  beq BccDontBranch%i\n\n",8<<size);\r
-      break;\r
-    default:\r
-      ot(";@ Is the condition true?\n");\r
-      ot("  msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
-      ot("  b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);\r
-      break;\r
+    cond=TestCond(cc,1);\r
+    ot("  b%s BccDontBranch%i\n\n",cond,8<<size);\r
   }\r
 \r
   if (size) \r

diff --git a/OpLogic.cpp b/OpLogic.cpp
index d4d9b13..19ec569 100644 (file)
--- a/OpLogic.cpp
+++ b/OpLogic.cpp
@@ -12,6 +12,84 @@
 \r
 #include "app.h"\r
 \r
+// trashes r0\r
+const char *TestCond(int m68k_cc, int invert)\r
+{\r
+  const char *cond="";\r
+  const char *icond="";\r
+\r
+  // ARM: NZCV\r
+  switch (m68k_cc)\r
+  {\r
+    case 0x00: // T\r
+    case 0x01: // F\r
+      break;\r
+    case 0x02: // hi\r
+      ot("  tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
+      cond="eq", icond="ne";\r
+      break;\r
+    case 0x03: // ls\r
+      ot("  tst r10,#0x60000000 ;@ ls: C || Z\n");\r
+      cond="ne", icond="eq";\r
+      break;\r
+    case 0x04: // cc\r
+      ot("  tst r10,#0x20000000 ;@ cc: !C\n");\r
+      cond="eq", icond="ne";\r
+      break;\r
+    case 0x05: // cs\r
+      ot("  tst r10,#0x20000000 ;@ cs: C\n");\r
+      cond="ne", icond="eq";\r
+      break;\r
+    case 0x06: // ne\r
+      ot("  tst r10,#0x40000000 ;@ ne: !Z\n");\r
+      cond="eq", icond="ne";\r
+      break;\r
+    case 0x07: // eq\r
+      ot("  tst r10,#0x40000000 ;@ eq: Z\n");\r
+      cond="ne", icond="eq";\r
+      break;\r
+    case 0x08: // vc\r
+      ot("  tst r10,#0x10000000 ;@ vc: !V\n");\r
+      cond="eq", icond="ne";\r
+      break;\r
+    case 0x09: // vs\r
+      ot("  tst r10,#0x10000000 ;@ vs: V\n");\r
+      cond="ne", icond="eq";\r
+      break;\r
+    case 0x0a: // pl\r
+      ot("  tst r10,r10 ;@ pl: !N\n");\r
+      cond="pl", icond="mi";\r
+      break;\r
+    case 0x0b: // mi\r
+      ot("  tst r10,r10 ;@ mi: N\n");\r
+      cond="mi", icond="pl";\r
+      break;\r
+    case 0x0c: // ge\r
+      ot("  teq r10,r10,lsl #3 ;@ ge: N == V\n");\r
+      cond="pl", icond="mi";\r
+      break;\r
+    case 0x0d: // lt\r
+      ot("  teq r10,r10,lsl #3 ;@ lt: N != V\n");\r
+      cond="mi", icond="pl";\r
+      break;\r
+    case 0x0e: // gt\r
+      ot("  eor r0,r10,r10,lsl #3 ;@ gt: !Z && N == V\n");\r
+      ot("  orrs r0,r10,lsl #1\n");\r
+      cond="pl", icond="mi";\r
+      break;\r
+    case 0x0f: // le\r
+      ot("  eor r0,r10,r10,lsl #3 ;@ le: Z || N != V\n");\r
+      ot("  orrs r0,r10,lsl #1\n");\r
+      cond="mi", icond="pl";\r
+      break;\r
+    default:\r
+      printf("invalid m68k_cc: %x\n", m68k_cc);\r
+      exit(1);\r
+      break;\r
+  }\r
+  return invert?icond:cond;\r
+}\r
+\r
 // --------------------- Opcodes 0x0100+ ---------------------\r
 // Emit a Btst (Register) opcode 0000nnn1 ttaaaaaa\r
 int OpBtstReg(int op)\r
@@ -318,11 +396,7 @@ int OpSet(int op)
 {\r
   int cc=0,ea=0;\r
   int size=0,use=0,changed_cycles=0;\r
-  static const char * const cond[16]=\r
-  {\r
-    "al","", "hi","ls","cc","cs","ne","eq",\r
-    "vc","vs","pl","mi","ge","lt","gt","le"\r
-  };\r
+  const char *cond;\r
 \r
   cc=(op>>8)&15;\r
   ea=op&0x003f;\r
@@ -339,32 +413,20 @@ int OpSet(int op)
   OpStart(op,ea,0,changed_cycles); Cycles=8;\r
   if (ea<8) Cycles=4;\r
 \r
-  if (cc)\r
-    ot("  mov r1,#0\n");\r
-\r
   switch (cc)\r
   {\r
-    case 0: // T\r
+    case 0x00: // T\r
       ot("  mvn r1,#0\n");\r
       if (ea<8) Cycles+=2;\r
       break;\r
-    case 1: // F\r
-      break;\r
-    case 2: // hi\r
-      ot("  tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
-      ot("  mvneq r1,r1\n");\r
-      if (ea<8) ot("  subeq r5,r5,#2 ;@ Extra cycles\n");\r
-      break;\r
-    case 3: // ls\r
-      ot("  tst r10,#0x60000000 ;@ ls: C || Z\n");\r
-      ot("  mvnne r1,r1\n");\r
-      if (ea<8) ot("  subne r5,r5,#2 ;@ Extra cycles\n");\r
+    case 0x01: // F\r
+      ot("  mov r1,#0\n");\r
       break;\r
     default:\r
-      ot(";@ Is the condition true?\n");\r
-      ot("  msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
-      ot("  mvn%s r1,r1\n",cond[cc]);\r
-      if (ea<8) ot("  sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);\r
+      ot("  mov r1,#0\n");\r
+      cond=TestCond(cc);\r
+      ot("  mvn%s r1,#0\n",cond);\r
+      if (ea<8) ot("  sub%s r5,r5,#2 ;@ Extra cycles\n",cond);\r
       break;\r
   }\r
 \r

diff --git a/app.h b/app.h
index 3528b7b..4a23630 100644 (file)
--- a/app.h
+++ b/app.h
@@ -102,6 +102,7 @@ int OpSet(int op);
 int OpAsr(int op);\r
 int OpAsrEa(int op);\r
 int OpTas(int op, int gen_special=0);\r
+const char *TestCond(int m68k_cc, int invert=0);\r
 \r
 // OpMove.cpp\r
 int OpMove(int op);\r

diff --git a/tools/idle.s b/tools/idle.s
index e970d2e..e55b5f1 100644 (file)
--- a/tools/idle.s
+++ b/tools/idle.s
@@ -104,15 +104,15 @@ idle_bra:
     b       Op6002
 
 idle_bne:
-    msr     cpsr_flg, r10
-    movne   r5, #2                @ 2 is intentional due to strange timing issues
-    inc_counter ne
+    tst     r10, #0x40000000      @ Z set?
+    moveq   r5, #2                @ 2 is intentional due to strange timing issues
+    inc_counter eq
     b       Op6602
 
 idle_beq:
-    msr     cpsr_flg, r10 ;@ ARM flags = 68000 flags
-    moveq   r5, #2
-    inc_counter eq
+    tst     r10, #0x40000000      @ Z set?
+    movne   r5, #2
+    inc_counter ne
     b       Op6702